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Author SHA1 Message Date
merryandGitHub 8d41402fa6 A32: Implement VCVTT, VCVTB (#3710) 
* A32: Implement VCVTT, VCVTB

* A32: F16C implementation of VCVTT/VCVTB
 2022-10-19 02:36:04 +02:00
merryandGitHub fbcf802fbc A32/T32/A64: Implement Hint instructions (CSDB, SEV, SEVL, WFE, WFI, YIELD) (#3694) 
* OpCodeTable: Implement Hint instructions (CSDB, SEV, SEVL, WFE, WFI, YIELD)

* A64: Remove catch-all Hint instruction

* T16: Handle unallocated hint instructions

Some thumb tests execute these assuming that they're nops.

* T32: Fill out other Hint instructions

* A32: Fill out other hint instructions
 2022-09-14 18:18:15 -03:00
merryandGitHub e05bf90af6 T32: Implement Asimd instructions (#3692) 2022-09-13 18:25:37 -03:00
merryandGitHub 1529e6cf0d T32: Add Vfp instructions (#3690) 2022-09-10 23:03:14 -03:00
merryandGitHub f5235fff29 ARMeilleure: Hardware accelerate SHA256 (#3585) 
* ARMeilleure/HardwareCapabilities: Add Sha

* ARMeilleure/Intrinsic: Add X86Sha256Rnds2

* ARmeilleure: Hardware accelerate SHA256H/SHA256H2

* ARMeilleure/Intrinsic: Add X86Sha256Msg1, X86Sha256Msg2

* ARMeilleure/Intrinsic: Add X86Palignr

* ARMeilleure: Hardware accelerate SHA256SU0, SHA256SU1

* PTC: Bump InternalVersion
 2022-08-25 10:12:13 +00:00
merryandGitHub 6dfb6ccf8c PreAllocator: Check if instruction supports a Vex prefix in IsVexSameOperandDestSrc1 (#3587) 2022-08-14 17:35:08 -03:00
merryandGitHub 7853faa334 Ava/MainWindow: Do not show Show Console menu item on non-Windows (#3461) 2022-07-12 12:58:31 +00:00
merryandGitHub 6a1a03566a T32: Implement load/store single (immediate) (#3186) 
* T32: Implement load/store single (immediate)

* tests

* tidy formatting

* address comments
 2022-04-21 01:25:43 +02:00
merryandGitHub 610fc84f3e ReactiveObject: Handle case when oldValue is null (#3268) 2022-04-15 12:58:27 +02:00
merryandGitHub 247d26b4b5 ForceDpiAware: X11 implementation (#3269) 
* ForceDpiAware: X11 implementation

* address comments
 2022-04-10 19:04:22 +02:00
merryandGitHub a4e8bea866 Lop3Expression: Optimize expressions (#3184) 
* lut3

* bugfixes

* TruthTable

* false/true -> 0/-1

* add or to expressions

* fix inversions

* increment cache version
 2022-04-08 11:17:38 +02:00
merryandGitHub ba0171d054 Memory.Tests: Make Multithreading test explicit (#3220) 2022-03-21 09:21:05 +01:00
merryandGitHub df70442c46 InstEmitMemoryEx: Barrier after write on ordered store (#3193) 
* InstEmitMemoryEx: Barrier after write on ordered store

* increment ptc version

* 32
 2022-03-19 10:32:35 -03:00
merryandGitHub 223172ac0b Ui: Add option to show/hide console window (Windows-only) (#3170) 
* Ui: Add option to show/hide console window (Windows-only)

* Ui: Only display Show Console menu item on Windows

* ConsoleHelper: Handle NULL case

This will never happen

* Address nits

* Address comments

* Address comments 2
 2022-03-15 02:35:41 +01:00
merryandGitHub bb2f9df0a1 KThread: Fix GetPsr mask (#3180) 
* ExecutionContext: GetPstate / SetPstate

* Put it in NativeContext

* KThread: Fix GetPsr mask

* ExecutionContext: Turn methods into Pstate property

* Address nit
 2022-03-11 03:16:32 +01:00
merryandGitHub 7af9fcbc06 T32: Implement Data Processing (Modified Immediate) instructions (#3178) 
* T32: Implement Data Processing (Modified Immediate) instructions

* Update tests

* switch -> lookup table
 2022-03-06 22:25:01 +01:00
merryandGitHub b97ff4da5e A32: Fix ALU immediate instructions (#3179) 
* Tests: Add A32 tests for immediate ADC/ADCS/RSC/RSCS/SBC/SBCS

* A32: Fix bug in ADC/ADCS/RSC/RSCS/SBC/SBCS

* CpuTestAluImm32: Add more opcodes

* Increment PTC version
 2022-03-05 15:23:10 -03:00
merryandGitHub 747081d2c7 Decoders: Fix instruction lengths for 16-bit B instructions (#3177) 2022-03-05 16:20:24 +01:00
merryandGitHub 497199bb50 Decoder: Exit on trapping instructions, and resume execution at trapping instruction (#3153) 
* Decoder: Exit on trapping instructions, and resume execution at trapping instruction

* Resume at trapping address

* remove mustExit
 2022-03-04 23:16:58 +01:00
merryandGitHub bd9ac0fdaa T32: Implement B, B.cond, BL, BLX (#3155) 
* Decoders: Make IsThumb a function of OpCode32

* OpCode32: Fix GetPc

* T32: Implement B, B.cond, BL, BLX

* rm usings
 2022-03-04 23:05:08 +01:00
merryandGitHub 7b35ebc64a T32: Implement ALU (shifted register) instructions (#3135) 
* T32: Implement ADC, ADD, AND, BIC, CMN, CMP, EOR, MOV, MVN, ORN, ORR, RSB, SBC, SUB, TEQ, TST (shifted register)

* OpCodeTable: Sort T32 list

* Tests: Rename RandomTestCase to PrecomputedThumbTestCase

* T32: Tests for AluRsImm instructions

* fix nit

* fix nit 2
 2022-02-22 19:11:28 -03:00
merryandGitHub dc063eac83 ARMeilleure: Implement single stepping (#3133) 
* Decoder: Implement SingleInstruction decoder mode

* Translator: Implement Step

* DecoderMode: Rename Normal to MultipleBlocks
 2022-02-22 11:11:42 -03:00
merryandGitHub f1460d5494 A32: Fix BLX and BXWritePC (#3151) 2022-02-22 10:41:56 -03:00
merryandGitHub 747876dc67 Decoders: Add IOpCode32HasSetFlags (#3136) 2022-02-18 01:33:43 +01:00
merryandGitHub 98e05ee4b7 ARMeilleure: Thumb support (All T16 instructions) (#3105) 
* Decoders: Add InITBlock argument

* OpCodeTable: Minor cleanup

* OpCodeTable: Remove existing thumb instruction implementations

* OpCodeTable: Prepare for thumb instructions

* OpCodeTables: Improve thumb fast lookup

* Tests: Prepare for thumb tests

* T16: Implement BX

* T16: Implement LSL/LSR/ASR (imm)

* T16: Implement ADDS, SUBS (reg)

* T16: Implement ADDS, SUBS (3-bit immediate)

* T16: Implement MOVS, CMP, ADDS, SUBS (8-bit immediate)

* T16: Implement ANDS, EORS, LSLS, LSRS, ASRS, ADCS, SBCS, RORS, TST, NEGS, CMP, CMN, ORRS, MULS, BICS, MVNS (low registers)

* T16: Implement ADD, CMP, MOV (high reg)

* T16: Implement BLX (reg)

* T16: Implement LDR (literal)

* T16: Implement {LDR,STR}{,H,B,SB,SH} (register)

* T16: Implement {LDR,STR}{,B,H} (immediate)

* T16: Implement LDR/STR (SP)

* T16: Implement ADR

* T16: Implement Add to SP (immediate)

* T16: Implement ADD/SUB (SP)

* T16: Implement SXTH, SXTB, UXTH, UTXB

* T16: Implement CBZ, CBNZ

* T16: Implement PUSH, POP

* T16: Implement REV, REV16, REVSH

* T16: Implement NOP

* T16: Implement LDM, STM

* T16: Implement SVC

* T16: Implement B (conditional)

* T16: Implement B (unconditional)

* T16: Implement IT

* fixup! T16: Implement ADD/SUB (SP)

* fixup! T16: Implement Add to SP (immediate)

* fixup! T16: Implement IT

* CpuTestThumb: Add randomized tests

* Remove inITBlock argument

* Address nits

* Use index to handle IfThenBlockState

* Reduce line noise

* fixup

* nit
 2022-02-17 19:39:45 -03:00
merryandGitHub ce71f9144e InstEmitMemory32: Literal loads always have word-aligned PC (#3104) 2022-02-11 17:51:03 -03:00
merryandGitHub 86b37d0ff7 ARMeilleure: A32: Implement SHSUB8 and UHSUB8 (#3089) 
* ARMeilleure: A32: Implement UHSUB8

* ARMeilleure: A32: Implement SHSUB8
 2022-02-08 10:46:42 +01:00
merryandGitHub 88d3ffb97c ARMeilleure: A32: Implement SHADD8 (#3086) 2022-02-06 12:25:45 -03:00
merryandGitHub 222b1ad7da ARMeilleure: OpCodeTable: Add CMN (RsReg) (#3087) 2022-02-06 02:01:05 +01:00