merry and GitHub
610fc84f3e
ReactiveObject: Handle case when oldValue is null ( #3268 )
2022-04-15 12:58:27 +02:00
merry and GitHub
247d26b4b5
ForceDpiAware: X11 implementation ( #3269 )
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* ForceDpiAware: X11 implementation
* address comments
2022-04-10 19:04:22 +02:00
merry and GitHub
a4e8bea866
Lop3Expression: Optimize expressions ( #3184 )
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* lut3
* bugfixes
* TruthTable
* false/true -> 0/-1
* add or to expressions
* fix inversions
* increment cache version
2022-04-08 11:17:38 +02:00
merry and GitHub
ba0171d054
Memory.Tests: Make Multithreading test explicit ( #3220 )
2022-03-21 09:21:05 +01:00
merry and GitHub
df70442c46
InstEmitMemoryEx: Barrier after write on ordered store ( #3193 )
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* InstEmitMemoryEx: Barrier after write on ordered store
* increment ptc version
* 32
2022-03-19 10:32:35 -03:00
merry and GitHub
223172ac0b
Ui: Add option to show/hide console window (Windows-only) ( #3170 )
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* Ui: Add option to show/hide console window (Windows-only)
* Ui: Only display Show Console menu item on Windows
* ConsoleHelper: Handle NULL case
This will never happen
* Address nits
* Address comments
* Address comments 2
2022-03-15 02:35:41 +01:00
merry and GitHub
bb2f9df0a1
KThread: Fix GetPsr mask ( #3180 )
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* ExecutionContext: GetPstate / SetPstate
* Put it in NativeContext
* KThread: Fix GetPsr mask
* ExecutionContext: Turn methods into Pstate property
* Address nit
2022-03-11 03:16:32 +01:00
merry and GitHub
7af9fcbc06
T32: Implement Data Processing (Modified Immediate) instructions ( #3178 )
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* T32: Implement Data Processing (Modified Immediate) instructions
* Update tests
* switch -> lookup table
2022-03-06 22:25:01 +01:00
merry and GitHub
b97ff4da5e
A32: Fix ALU immediate instructions ( #3179 )
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* Tests: Add A32 tests for immediate ADC/ADCS/RSC/RSCS/SBC/SBCS
* A32: Fix bug in ADC/ADCS/RSC/RSCS/SBC/SBCS
* CpuTestAluImm32: Add more opcodes
* Increment PTC version
2022-03-05 15:23:10 -03:00
merry and GitHub
747081d2c7
Decoders: Fix instruction lengths for 16-bit B instructions ( #3177 )
2022-03-05 16:20:24 +01:00
merry and GitHub
497199bb50
Decoder: Exit on trapping instructions, and resume execution at trapping instruction ( #3153 )
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* Decoder: Exit on trapping instructions, and resume execution at trapping instruction
* Resume at trapping address
* remove mustExit
2022-03-04 23:16:58 +01:00
merry and GitHub
bd9ac0fdaa
T32: Implement B, B.cond, BL, BLX ( #3155 )
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* Decoders: Make IsThumb a function of OpCode32
* OpCode32: Fix GetPc
* T32: Implement B, B.cond, BL, BLX
* rm usings
2022-03-04 23:05:08 +01:00
merry and GitHub
7b35ebc64a
T32: Implement ALU (shifted register) instructions ( #3135 )
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* T32: Implement ADC, ADD, AND, BIC, CMN, CMP, EOR, MOV, MVN, ORN, ORR, RSB, SBC, SUB, TEQ, TST (shifted register)
* OpCodeTable: Sort T32 list
* Tests: Rename RandomTestCase to PrecomputedThumbTestCase
* T32: Tests for AluRsImm instructions
* fix nit
* fix nit 2
2022-02-22 19:11:28 -03:00
merry and GitHub
dc063eac83
ARMeilleure: Implement single stepping ( #3133 )
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* Decoder: Implement SingleInstruction decoder mode
* Translator: Implement Step
* DecoderMode: Rename Normal to MultipleBlocks
2022-02-22 11:11:42 -03:00
merry and GitHub
f1460d5494
A32: Fix BLX and BXWritePC ( #3151 )
2022-02-22 10:41:56 -03:00
merry and GitHub
747876dc67
Decoders: Add IOpCode32HasSetFlags ( #3136 )
2022-02-18 01:33:43 +01:00
merry and GitHub
98e05ee4b7
ARMeilleure: Thumb support (All T16 instructions) ( #3105 )
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* Decoders: Add InITBlock argument
* OpCodeTable: Minor cleanup
* OpCodeTable: Remove existing thumb instruction implementations
* OpCodeTable: Prepare for thumb instructions
* OpCodeTables: Improve thumb fast lookup
* Tests: Prepare for thumb tests
* T16: Implement BX
* T16: Implement LSL/LSR/ASR (imm)
* T16: Implement ADDS, SUBS (reg)
* T16: Implement ADDS, SUBS (3-bit immediate)
* T16: Implement MOVS, CMP, ADDS, SUBS (8-bit immediate)
* T16: Implement ANDS, EORS, LSLS, LSRS, ASRS, ADCS, SBCS, RORS, TST, NEGS, CMP, CMN, ORRS, MULS, BICS, MVNS (low registers)
* T16: Implement ADD, CMP, MOV (high reg)
* T16: Implement BLX (reg)
* T16: Implement LDR (literal)
* T16: Implement {LDR,STR}{,H,B,SB,SH} (register)
* T16: Implement {LDR,STR}{,B,H} (immediate)
* T16: Implement LDR/STR (SP)
* T16: Implement ADR
* T16: Implement Add to SP (immediate)
* T16: Implement ADD/SUB (SP)
* T16: Implement SXTH, SXTB, UXTH, UTXB
* T16: Implement CBZ, CBNZ
* T16: Implement PUSH, POP
* T16: Implement REV, REV16, REVSH
* T16: Implement NOP
* T16: Implement LDM, STM
* T16: Implement SVC
* T16: Implement B (conditional)
* T16: Implement B (unconditional)
* T16: Implement IT
* fixup! T16: Implement ADD/SUB (SP)
* fixup! T16: Implement Add to SP (immediate)
* fixup! T16: Implement IT
* CpuTestThumb: Add randomized tests
* Remove inITBlock argument
* Address nits
* Use index to handle IfThenBlockState
* Reduce line noise
* fixup
* nit
2022-02-17 19:39:45 -03:00
merry and GitHub
ce71f9144e
InstEmitMemory32: Literal loads always have word-aligned PC ( #3104 )
2022-02-11 17:51:03 -03:00
merry and GitHub
86b37d0ff7
ARMeilleure: A32: Implement SHSUB8 and UHSUB8 ( #3089 )
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* ARMeilleure: A32: Implement UHSUB8
* ARMeilleure: A32: Implement SHSUB8
2022-02-08 10:46:42 +01:00
merry and GitHub
88d3ffb97c
ARMeilleure: A32: Implement SHADD8 ( #3086 )
2022-02-06 12:25:45 -03:00
merry and GitHub
222b1ad7da
ARMeilleure: OpCodeTable: Add CMN (RsReg) ( #3087 )
2022-02-06 02:01:05 +01:00
merryandGitHub