  LDj3SNuDandgdkchan
|
51ea6fa583
|
Add Smaxv_V, Sminv_V, Umaxv_V, Uminv_V Inst.; add Tests. (#691)
* Update InstEmitSimdHelper.cs
* Update InstEmitSimdArithmetic.cs
* Update OpCodeTable.cs
* Update CpuTestSimd.cs
|
2019-05-29 21:29:24 -03:00 |
|
 LDj3SNuDandjduncanator
|
16de171c44
|
Sse optimized the Scalar & Vector fp-to-fp conversion instructions (MNPZ & IX); added the related Tests (AMNPZ & IX). Small refactoring of existing instructions. (#676)
* Nit.
* Update InstEmitSimdCvt.cs
* Update VectorHelper.cs
* Update InstEmitSimdArithmetic.cs
* Update CpuTestSimd.cs
* Superseded.
|
2019-04-26 08:58:29 +10:00 |
|
|
LDj3SNuDandgdkchan
|
74da8785a5
|
Sse optimized the 32-bit Vector & Scalar integer-to-fp conversion instructions (signed & unsigned); added the related Gp & V_Fixed Tests (signed & unsigned). (#662)
* Update CpuTestSimdCvt.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdShImm.cs
* Update InstEmitSimdCvt.cs
* Update OpCodeTable.cs
* Update InstEmitSimdCvt.cs
|
2019-04-20 23:07:35 -03:00 |
|
|
LDj3SNuDandgdkchan
|
233fc95e1e
|
Sse optimized the Vector & Scalar fp-to-integer conversion instructions (unsigned); improved the related Tests. (#656)
* Update InstEmitSimdCvt.cs
* Update CpuTestSimdCvt.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdShImm.cs
* Update InstEmitSimdCvt.cs
|
2019-04-12 13:14:16 -03:00 |
|
|
LDj3SNuDandgdkchan
|
febc2ad6f4
|
Sse optimized all the fp to integer conversion instructions (signed) with Tests (signed & unsigned). (#655)
* Update CpuTestSimdCvt.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdShImm.cs
* Update InstEmitSimdCvt.cs
* Update InstEmitSimdMove.cs
* Update InstEmitSimdCmp.cs
* Update VectorHelper.cs
* Update InstEmitSimdHelper.cs
* Update OpCodeTable.cs
* Update InstEmitSimdCvt.cs
* Update InstEmitSimdHelper.cs
* Update InstEmitSimdMove.cs
|
2019-04-03 09:21:22 -03:00 |
|
|
LDj3SNuDandjduncanator
|
464ec7ced8
|
Add Cmeq_V, Cmge_V, Cmgt_V, Cmle_V & Cmlt_V (Z & ~Z) Sse opt.. (#646)
* Follow-up (Neg_V).
* Follow-up (Not_V & Orn_V).
* Add Cmeq/ge/gt/le/lt_V (Z & ~Z) Sse opt..
* Add EmitLd/Stvectmp2/3.
* Remove Dup (EmitVectorPairwiseSseOrSse2OpF).
* Remove Dup (EmitFcmpOrFcmpe).
* Add S/Uabd/l_V Sse opt.. Remove Dup (Srhadd_V).
* Nit.
|
2019-03-25 10:23:27 +11:00 |
|
|
LDj3SNuDandgdkchan
|
c106ae9944
|
Add Tbl_V Sse opt. with Tests. (#651)
* Add v4, v5, v30, v31 required for Tbl_V Tests.
* Add Tests for Tbl_V.
* Add Tbl_V Sse opt..
* Nit.
* Small opt. on comparison constant vector.
* Nit.
* Add EmitLd/Stvectmp2/3.
* Nit.
|
2019-03-23 15:50:19 -03:00 |
|
|
LDj3SNuDandjduncanator
|
1bef70c068
|
Add Rshrn_V & Shrn_V Sse opt.. Add Mla_V, Mls_V & Mul_V Sse opt.; add Tests. (#614)
* Update CountLeadingZeros().
* Remove obsolete Tests.
* Follow-up.
* Follow-up.
* Follow-up.
* Add Mla_V, Mls_V & Mul_V Tests.
* Update PackageReferences.
* Remove EmitLd/Stvectmp2().
* Remove Dup. Nits.
* Remove EmitLd/Stvectmp2() & Dup; nits.
* Remove Tmp stuff & Dup; rework Fcvtz() as Fcvtn().
* Remove Tmp stuff, EmitLd/Stvectmp2() & Dup. Nits.
* Add (R)shrn_V Sse opt.; add "Part" & "Shift" opt..
Remove Tmp stuff; remove Dup.
Nits.
* Add Mla/Mls/Mul_V Sse opt.. Add "Part" opt..
Remove EmitLd/Stvectmp2(), remove Dup.
Nits.
* Nits.
* Nits.
* Nit.
* Add "Part" opt.. Nit.
* Nit.
* Nit.
* Add Cmhi_V & Cmhs_V Sse opt..
|
2019-03-13 19:23:52 +11:00 |
|
|
LDj3SNuDandjduncanator
|
dbc105eafb
|
Create CpuTestSimdImm.cs (#608)
|
2019-03-01 20:12:09 +11:00 |
|
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LDj3SNuDandgdkchan
|
a3d46e4133
|
Add Tests for instructions Fcvtzs_Gp_Fixed & Fcvtzu_Gp_Fixed, Scvtf_Gp_Fixed & Ucvtf_Gp_Fixed. (#603)
* Create CpuTestSimdCvt.cs
* Update CpuTestMisc.cs
* Update CpuTestSimdCvt.cs
|
2019-02-23 20:53:27 -03:00 |
|
 LDj3SNuDandGitHub
|
1b4809bde1
|
Update CpuTestMisc.cs
|
2019-02-18 00:52:01 +01:00 |
|
|
LDj3SNuDandgdkchan
|
8f7fcede7f
|
Add Smlal_Ve, Smlsl_Ve, Smull_Ve, Umlal_Ve, Umlsl_Ve, Umull_Ve Inst.; add Tests. Add Sse Opt. for Trn1/2_V and Uzp1/2_V Inst. Nits. (#566)
* Update OpCodeTable.cs
* Update InstEmitSimdArithmetic.cs
* Update InstEmitSimdHelper.cs
* Update CpuTestSimdRegElem.cs
* Update InstEmitSimdMove.cs
* Update InstEmitSimdCvt.cs
* Update SoftFallback.cs
* Update InstEmitSimdHelper.cs
* Update SoftFloat.cs
* Update CryptoHelper.cs
* Update InstEmitSimdArithmetic.cs
* Update InstEmitSimdCmp.cs
* Address PR feedback.
* Address PR feedback.
|
2019-01-29 10:54:39 -03:00 |
|
|
LDj3SNuDandgdkchan
|
0f5b6dfbe8
|
Fix Frecpe_S/V and Frsqrte_S/V (full FP emu.). Add Sse Opt. & SoftFloat Impl. for Fcmeq/ge/gt/le/lt_S/V (Reg & Zero), Faddp_S/V, Fmaxp_V, Fminp_V Inst.; add Sse Opt. for Shll_V, S/Ushll_V Inst.; improve Sse Opt. for Xtn_V Inst.. Add Tests. (#543)
* Update Optimizations.cs
* Update InstEmitSimdShift.cs
* Update InstEmitSimdHelper.cs
* Update InstEmitSimdArithmetic.cs
* Update InstEmitSimdMove.cs
* Update SoftFloat.cs
* Update InstEmitSimdCmp.cs
* Update CpuTestSimdShImm.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Nit.
* Update SoftFloat.cs
* Update InstEmitSimdArithmetic.cs
* Update InstEmitSimdHelper.cs
* Update CpuTestSimd.cs
* Explicit some implicit casts.
* Simplify some powers; nits.
* Update OpCodeTable.cs
* Update InstEmitSimdArithmetic.cs
* Update CpuTestSimdReg.cs
* Update InstEmitSimdArithmetic.cs
|
2018-12-26 15:11:36 -02:00 |
|
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LDj3SNuDandgdkchan
|
ad00fd0244
|
Fix Sshl_V; Add S/Uqrshl_V, S/Uqshl_V, S/Urshl_V; Add Tests. (#516)
* Update OpCodeTable.cs
* Update InstEmitSimdShift.cs
* Update SoftFallback.cs
* Update CpuTestSimdReg.cs
* Nit.
* Update SoftFallback.cs
* Update Optimizations.cs
* Update InstEmitSimdLogical.cs
* Update InstEmitSimdArithmetic.cs
|
2018-12-01 22:34:43 -02:00 |
|
|
LDj3SNuDandgdkchan
|
e603b7afbc
|
Add Sse Opt. for S/Umax_V, S/Umin_V, S/Uaddw_V, S/Usubw_V, Fabs_S/V, Fneg_S/V Inst.; for Fcvtl_V, Fcvtn_V Inst.; and for Fcmp_S Inst.. Add/Improve other Sse Opt.. Add Tests. (#496)
* Update CpuTest.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Update InstEmitSimdCmp.cs
* Update SoftFloat.cs
* Update InstEmitAluHelper.cs
* Update InstEmitSimdArithmetic.cs
* Update InstEmitSimdHelper.cs
* Update VectorHelper.cs
* Update InstEmitSimdCvt.cs
* Update InstEmitSimdArithmetic.cs
* Update CpuTestSimd.cs
* Update InstEmitSimdArithmetic.cs
* Update OpCodeTable.cs
* Update InstEmitSimdArithmetic.cs
* Update InstEmitSimdCmp.cs
* Update InstEmitSimdCvt.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Create CpuTestSimdFcond.cs
* Update OpCodeTable.cs
* Update InstEmitSimdMove.cs
* Update CpuTestSimdIns.cs
* Create CpuTestSimdExt.cs
* Nit.
* Update PackageReference.
|
2018-11-18 00:41:16 -02:00 |
|
|
LDj3SNuDandgdkchan
|
1e7ea76f14
|
Add Flush-to-zero mode (input, output) to FP instructions (slow paths); update FP Tests. Update Naming Conventions for Tests project. (#489)
* Update SoftFloat.cs
* Update SoftFallback.cs
* Update InstEmitSimdShift.cs
* Update InstEmitSimdCvt.cs
* Update InstEmitSimdArithmetic.cs
* Update CryptoHelper.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Update CpuThreadState.cs
* Update OpCodeTable.cs
* Add files via upload
* Nit.
* Remove unused using. Nit.
* Remove unused using. FZ update.
* Nit.
* Remove unused using.
|
2018-11-01 01:22:09 -03:00 |
|
|
LDj3SNuDandgdkchan
|
b956bbc32c
|
Add SHA1C, SHA1H, SHA1M, SHA1P, SHA1SU0, SHA1SU1 and Isb instructions; add 6 Tests (closed box). (#483)
* Update AOpCodeTable.cs
* Update AInstEmitSystem.cs
* Update AInstEmitSimdHash.cs
* Update ASoftFallback.cs
* Update CpuTestSimdReg.cs
* Update CpuTestSimd.cs
|
2018-10-28 19:27:50 -03:00 |
|
|
LDj3SNuDandgdkchan
|
00d4f44bbb
|
Add Sse Opt. for S/Uaddl_V, S/Uhadd_V, S/Uhsub_V, S/Umlal_V, S/Umlsl_V, S/Urhadd_V, S/Usubl_V Inst.; and for S/Urshr_V, S/Ursra_V Inst.. (#480)
* Update AILEmitterCtx.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdShift.cs
|
2018-10-25 19:10:41 -03:00 |
|
|
LDj3SNuDandgdkchan
|
e674b37710
|
Fix Fcvtl_V and Fcvtn_V; fix half to float conv. and add float to half conv. (full FP emu.). Add 4 FP Tests. (#468)
* Update CpuTest.cs
* Update CpuTestSimd.cs
* Superseded.
* Update AInstEmitSimdCvt.cs
* Update ASoftFloat.cs
* Nit.
* Update PackageReferences.
* Update AInstEmitSimdArithmetic.cs
* Update AVectorHelper.cs
* Update ASoftFloat.cs
* Update ASoftFallback.cs
* Update AThreadState.cs
* Create FPType.cs
* Create FPExc.cs
* Create FPCR.cs
* Create FPSR.cs
* Update ARoundMode.cs
* Update APState.cs
* Avoid an unwanted implicit cast of the operator >= to long, continuing to check for negative values. Remove a leftover.
* Nits.
|
2018-10-23 11:12:45 -03:00 |
|
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LDj3SNuDandgdkchan
|
894459fcd7
|
Add Fmls_Se, Fmulx_Se/Ve, Smov_S Inst.; Opt. Clz/Clz_V, Cnt_V, Shl_V, S/Ushr_V, S/Usra_V Inst.; Add 11 Tests. Some fixes. (#449)
* Update AOpCodeTable.cs
* Update AInstEmitSimdMove.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdShift.cs
* Update ASoftFallback.cs
* Update ASoftFloat.cs
* Update AOpCodeSimdRegElemF.cs
* Update CpuTestSimdIns.cs
* Update CpuTestSimdRegElem.cs
* Create CpuTestSimdRegElemF.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Superseded Fmul_Se Test. Nit.
* Address PR feedback.
* Address PR feedback.
* Update AInstEmitSimdArithmetic.cs
* Update ASoftFallback.cs
* Update AInstEmitAlu.cs
* Update AInstEmitSimdShift.cs
|
2018-10-13 23:35:16 -03:00 |
|
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LDj3SNuDandgdkchan
|
bba9bf97d0
|
Add 9+7 fast/slow FP inst. impls.; add 14 FP Tests. (#437)
* Update CpuTest.cs
* Delete CpuTestSimdCmp.cs
Obsolete.
* Update CpuTestSimdArithmetic.cs
Superseded.
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdHelper.cs
* Update ASoftFloat.cs
* Nit.
* Update AOpCodeTable.cs
* Update AOptimizations.cs
* Update AInstEmitSimdArithmetic.cs
* Update ASoftFloat.cs
* Update CpuTest.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update ASoftFloat.cs
* Update CpuTestSimdReg.cs
* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update ASoftFloat.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
|
2018-10-05 22:45:59 -03:00 |
|
|
LDj3SNuDandgdkchan
|
c7387be0d2
|
Fix/Add 1+12 [Saturating] [Rounded] Shift Right Narrow (imm.) Instructions; add 14 Tests. Add 6 Tests for PR#405. Add 2 Tests for PR#412. (#409)
* Update AOpCodeTable.cs
* Update AInstEmitSimdShift.cs
* Update CpuTestSimdShImm.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdHelper.cs
* Create CpuTestSimdIns.cs
* Update CpuTest.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Update CpuTest.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Update CpuTest.cs
* Update CpuTestSimdReg.cs
* Update CpuTestSimd.cs
|
2018-09-17 01:54:05 -03:00 |
|
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LDj3SNuDandgdkchan
|
a0c78f7920
|
Fix/Add 10 Shift Right and Mls_Ve Instructions; add 14 Tests. (#407)
* Update AOpCodeTable.cs
* Update AInstEmitSimdShift.cs
* Update ASoftFallback.cs
* Update AOpCodeSimdShImm.cs
* Update ABitUtils.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdHelper.cs
* Create CpuTestSimdShImm.cs
* Create CpuTestSimdRegElem.cs
* Address PR feedback.
* Nit.
* Nit.
|
2018-09-08 14:24:29 -03:00 |
|
|
LDj3SNuDandgdkchan
|
ca1e37a295
|
Remove old Tester, update Tests (some reworks). (#400)
* Delete Bits.cs
* Delete Integer.cs
* Delete Instructions.cs
* Delete Pseudocode.cs
* Add files via upload
* Add mnemonic.
* Literals all uppercase.
* Nit.
* Allow FPSR control.
* Allow FPSR control.
* Allow FPSR control.
|
2018-09-08 14:23:07 -03:00 |
|
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LDj3SNuDandgdkchan
|
42e4e02a64
|
Add Fcvtns_S, Fcvtns_V, Fcvtnu_S, Fcvtnu_V (AOpCodeSimd) FP & Umlal_V, Umlsl_V, Saddl_V, Ssubl_V, Usubl_V instructions; add 8 FP & 16 S/Umlal_V, S/Umlsl_V, S/Uaddl_V, S/Usubl_V Tests. (#390)
* Update AOpCodeTable.cs
* Update AInstEmitSimdCvt.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update Instructions.cs
* Update CpuTestSimdReg.cs
* Update CpuTestSimd.cs
* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update Instructions.cs
* Update CpuTestSimdReg.cs
* Add QCFlagBit.
* Add QCFlagBit.
|
2018-09-01 11:52:51 -03:00 |
|
|
LDj3SNuDandgdkchan
|
68300368d7
|
Add SHADD, SHSUB, UHSUB, SRHADD, URHADD, instructions; add 12 Tests. (#380)
* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update Instructions.cs
* Update CpuTestSimdReg.cs
* Update CpuTest.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdCrypto.cs
|
2018-08-27 03:44:01 -03:00 |
|
|
LDj3SNuDandgdkchan
|
d021d5dfa9
|
Add AESD, AESE, AESIMC, AESMC instructions; add 4 simple Tests (closed box). (#365)
* Create CpuTestSimdCrypto.cs
* Update AOpCodeTable.cs
* Create AInstEmitSimdCrypto.cs
* Update ASoftFallback.cs
* Create ACryptoHelper.cs
|
2018-08-20 01:20:26 -03:00 |
|
|
LDj3SNuDandgdkchan
|
34100051e4
|
Add SHA256H, SHA256H2, SHA256SU0, SHA256SU1 instructions; add 4 Tests (closed box). (#352)
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update Bits.cs
* Update Integer.cs
* Update AOpCodeTable.cs
* Create AInstEmitSimdHash.cs
* Update ASoftFallback.cs
|
2018-08-16 21:44:44 -03:00 |
|
|
LDj3SNuDandgdkchan
|
4518c52c65
|
Add Sadalp_V, Saddlp_V, Uadalp_V, Uaddlp_V instructions; add 8 Tests. (#340)
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
|
2018-08-13 18:10:02 -03:00 |
|
|
LDj3SNuDandgdkchan
|
02a6fdcd13
|
Add Sqdmulh_S, Sqdmulh_V, Sqrdmulh_S, Sqrdmulh_V instructions; add 6 Tests. Now all saturating methods are on ASoftFallback. (#334)
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdHelper.cs
* Update ASoftFallback.cs
* Update CpuTestAlu.cs
* Update CpuTestAluImm.cs
* Update CpuTestAluRs.cs
* Update CpuTestAluRx.cs
* Update CpuTestBfm.cs
* Update CpuTestCcmpImm.cs
* Update CpuTestCcmpReg.cs
* Update CpuTestCsel.cs
* Update CpuTestMov.cs
* Update CpuTestMul.cs
* Update Ryujinx.Tests.csproj
* Update Ryujinx.csproj
* Update Luea.csproj
* Update Ryujinx.ShaderTools.csproj
* Address PR feedback (further tested).
* Address PR feedback.
|
2018-08-10 14:27:15 -03:00 |
|
|
LDj3SNuDandgdkchan
|
5f34353dce
|
Add SQADD, UQADD, SQSUB, UQSUB, SUQADD, USQADD, SQABS, SQNEG (Scalar, Vector) instructions; add 24 Tests. Most saturation instructions now on ASoftFallback. (#314)
* Update AOpCodeTable.cs
* Update AInstEmitSimdHelper.cs
* Update AInstEmitSimdArithmetic.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Update AInstEmitSimdHelper.cs
* Update AInstEmitSimdHelper.cs
* Update AInstEmitSimdHelper.cs
* Update AInstEmitSimdHelper.cs
* Update ASoftFallback.cs
* Update AInstEmitSimdHelper.cs
* Update ASoftFallback.cs
* Update AInstEmitSimdHelper.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Update ASoftFallback.cs
* Update AInstEmitSimdHelper.cs
* Opt. (retest).
|
2018-08-04 16:58:54 -03:00 |
|
|
LDj3SNuDandgdkchan
|
fa5545aab8
|
Implement Ssubw_V and Usubw_V instructions. (#287)
* Update AOpCodeTable.cs
* Update AInstEmitSimdHelper.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdMove.cs
* Update AInstEmitSimdCmp.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
|
2018-07-18 21:06:28 -03:00 |
|
|
LDj3SNuDandgdkchan
|
063fae50fe
|
Fix EmitHighNarrow(), EmitSaturatingNarrowOp() when Rd == Rn || Rd == Rm (& Part != 0). Optimization of EmitVectorTranspose(), EmitVectorUnzip(), EmitVectorZip() algorithms (reduction of the number of operations and their complexity). Add 12 Tests about Trn1/2, Uzp1/2, Zip1/2 (V) instructions. (#268)
* Update CpuTestSimdArithmetic.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Update Instructions.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdHelper.cs
* Update AInstEmitSimdMove.cs
* Delete CpuTestSimdMove.cs
|
2018-07-15 00:53:26 -03:00 |
|
|
LDj3SNuDandgdkchan
|
be31f5b46d
|
Improve CountLeadingZeros() algorithm, nits. (#219)
* Update AInstEmitSimdArithmetic.cs
* Update ASoftFallback.cs
* Update ASoftFallback.cs
* Update ASoftFallback.cs
* Update AInstEmitSimdArithmetic.cs
|
2018-07-14 15:07:44 -03:00 |
|
|
LDj3SNuDandgdkchan
|
c228cf320d
|
Add Rbit_V instruction. Add 8 tests (Rbit_V; Rev16_V, Rev32_V, Rev64_V). Improve CountSetBits8() algorithm. (#212)
* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdLogical.cs
* Update AVectorHelper.cs
* Update ASoftFallback.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Improve CountSetBits8() algorithm.
* Improve CountSetBits8() algorithm.
|
2018-07-03 03:31:16 -03:00 |
|
|
LDj3SNuDandgdkchan
|
53934e8872
|
Add Saba_V, Sabal_V, Sabd_V, Sabdl_V, Uaba_V, Uabal_V; Update Uabd_V, Uabdl_V. Add 16 tests. (#204)
* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdHelper.cs
* Update Instructions.cs
* Update CpuTest.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
|
2018-06-30 12:40:41 -03:00 |
|
|
LDj3SNuDandgdkchan
|
c818093528
|
Add Sqxtun_S, Sqxtun_V with 3 tests. (#188)
* Update AInstEmitSimdArithmetic.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
|
2018-06-25 23:36:20 -03:00 |
|
|
LDj3SNuDandgdkchan
|
8f6387128a
|
Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183)
* Add files via upload
* Add files via upload
* Add files via upload
* CPE
* Add EmitSse42Crc32()
* Update CpuTestSimdCmp.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update Instructions.cs
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2018-06-25 22:32:29 -03:00 |
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LDj3SNuDandgdkchan
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3bdd109f45
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Add Cmeq_S, Cmge_S, Cmgt_S, Cmhi_S, Cmhs_S, Cmle_S, Cmlt_S (Reg, Zero) & Cmtst_S compare instructions. Add 22 compare tests (Scalar, Vector). Add Eor_V, Not_V tests. (#171)
* Add files via upload
* Add files via upload
* Delete CpuTestScalar.cs
* Update CpuTestSimdArithmetic.cs
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2018-06-18 14:55:26 -03:00 |
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LDj3SNuDandgdkchan
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7cda630aba
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Add Sqxtn_S, Sqxtn_V, Uqxtn_S, Uqxtn_V instructions and Tests (6). (#110)
* Update ILGeneratorEx.cs
* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Update CpuTest.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdArithmetic.cs
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2018-04-29 20:39:58 -03:00 |
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LDj3SNuDandgdkchan
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2f1250ab04
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Update AOpCodeTable.cs (#108)
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2018-04-25 23:26:41 -03:00 |
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LDj3SNuDandgdkchan
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a5ad1e9a06
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Add Cls_V, Clz_V, Orn_V instructions. Add 18 Tests: And_V, Bic_V, Bif_V, Bit_V, Bsl_V, Cls_V, Clz_V, Orn_V, Orr_V. (#104)
* Update AOpCodeTable.cs
* Update AInstEmitSimdLogical.cs
* Update AInstEmitSimdArithmetic.cs
* Update ASoftFallback.cs
* Update AInstEmitAlu.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimdReg.cs
* Update CpuTestSimd.cs
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2018-04-25 23:20:22 -03:00 |
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LDj3SNuDandgdkchan
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302c1d2861
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Fix Addp_S in AOpCodeTable. Add 5 Tests: ADDP (scalar), ADDP (vector), ADDV. (#96)
* Update AOpCodeTable.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Update Instructions.cs
* Revert "Started to work in improving the sync primitives"
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2018-04-21 16:15:04 -03:00 |
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LDj3SNuDandgdkchan
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2ccd995cb2
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Add ADDHN{2}, RADDHN{2}, SUBHN{2}, RSUBHN{2} (vector) instructions. Add 8 Tests. (#92)
* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update Bits.cs
* Create CpuTestSimd.cs
* Create CpuTestSimdReg.cs
* Update CpuTestSimd.cs
Provide a better supply of input values for the 20 Simd Tests.
* Update CpuTestSimdReg.cs
Provide a better supply of input values for the 20 Simd Tests.
* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
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2018-04-20 12:40:15 -03:00 |
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LDj3SNuDandgdkchan
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e9a96e3522
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Add 151 complete tests for 71 base instructions of types: Alu; AluImm; AluRs; AluRx; Bfm; CcmpImm; CcmpReg; Csel; Mov; Mul. (#80)
* Add files via upload
* Update Ryujinx.Tests.csproj
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2018-04-18 17:22:45 -03:00 |
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LDj3SNuDandgdkchan
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8b75080639
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Add ABS (scalar & vector), ADD (scalar), NEG (scalar) instructions. (#88)
* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update AOpCodeTable.cs
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2018-04-18 10:56:27 -03:00 |
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LDj3SNuDandgdkchan
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262b5b8054
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Add TRN1 & TRN2 (vector) instructions. Add 4 simple tests (4S, 8B). (#77)
* Update AOpCodeTable.cs
* Update AInstEmitSimdMove.cs
* Update CpuTestSimdMove.cs
* Update AInstEmitSimdMove.cs
* Update CpuTestSimdMove.cs
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2018-04-12 11:52:00 -03:00 |
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LDj3SNuDandgdkchan
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e9cfdef098
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Add A1B5G5R5 texture format. (#76)
* Update GalTextureFormat.cs
* Update TextureReader.cs
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2018-04-08 18:08:36 -03:00 |
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LDj3SNuDandgdkchan
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7acd0e0122
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Add FMUL (scalar, by element) instruction; add FRECPE, FRECPS (scalar & vector) instructions. Add 5 simple tests. (#74)
* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdHelper.cs
* Update CpuTestSimdArithmetic.cs
* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
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2018-04-08 16:08:57 -03:00 |
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LDj3SNuDandgdkchan
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873a7cd112
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Add Cls Instruction. (#67)
* Update AInstEmitAlu.cs
* Update ASoftFallback.cs
* Update AOpCodeTable.cs
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2018-03-23 22:06:05 -03:00 |
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LDj3SNuDandgdkchan
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f09a0082bf
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Review of cpu tests and creation of a class for mixed cpu tests. (#35)
* Update CpuTest.cs
* Update CpuTestAlu.cs
* Update CpuTestScalar.cs
* Update CpuTestSimdMove.cs
* Create CpuTestMisc.cs
* Update CpuTest.cs
* Update CpuTestScalar.cs
* Update CpuTest.cs
* Update CpuTestAlu.cs
* Update CpuTestMisc.cs
* Update CpuTestScalar.cs
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2018-02-23 09:29:20 -03:00 |
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