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Author	SHA1	Message	Date
merryandGitHub	ce71f9144e	InstEmitMemory32: Literal loads always have word-aligned PC (#3104)	2022-02-11 17:51:03 -03:00
merryandGitHub	86b37d0ff7	ARMeilleure: A32: Implement SHSUB8 and UHSUB8 (#3089) ... * ARMeilleure: A32: Implement UHSUB8 * ARMeilleure: A32: Implement SHSUB8	2022-02-08 10:46:42 +01:00
merryandGitHub	88d3ffb97c	ARMeilleure: A32: Implement SHADD8 (#3086)	2022-02-06 12:25:45 -03:00
merryandGitHub	222b1ad7da	ARMeilleure: OpCodeTable: Add CMN (RsReg) (#3087)	2022-02-06 02:01:05 +01:00