| .. |
|
CpuContext.cs
|
Refactor CPU interface to allow the implementation of other CPU emulators (#3362)
|
2022-05-31 16:29:35 -03:00 |
|
CpuTest32.cs
|
Refactor CPU interface to allow the implementation of other CPU emulators (#3362)
|
2022-05-31 16:29:35 -03:00 |
|
CpuTest.cs
|
Refactor CPU interface to allow the implementation of other CPU emulators (#3362)
|
2022-05-31 16:29:35 -03:00 |
|
CpuTestAlu32.cs
|
ARMeilleure: A32: Implement SHSUB8 and UHSUB8 (#3089)
|
2022-02-08 10:46:42 +01:00 |
|
CpuTestAlu.cs
|
|
|
|
CpuTestAluBinary32.cs
|
|
|
|
CpuTestAluBinary.cs
|
|
|
|
CpuTestAluImm32.cs
|
A32: Fix ALU immediate instructions (#3179)
|
2022-03-05 15:23:10 -03:00 |
|
CpuTestAluImm.cs
|
|
|
|
CpuTestAluRs32.cs
|
|
|
|
CpuTestAluRs.cs
|
|
|
|
CpuTestAluRx.cs
|
|
|
|
CpuTestBf32.cs
|
|
|
|
CpuTestBfm.cs
|
|
|
|
CpuTestCcmpImm.cs
|
|
|
|
CpuTestCcmpReg.cs
|
|
|
|
CpuTestCsel.cs
|
|
|
|
CpuTestMisc32.cs
|
|
|
|
CpuTestMisc.cs
|
|
|
|
CpuTestMov.cs
|
|
|
|
CpuTestMul32.cs
|
|
|
|
CpuTestMul.cs
|
|
|
|
CpuTestSimd32.cs
|
Implement Arm32 Sha256 and MRS Rd, CPSR instructions (#3544)
|
2022-08-05 19:03:50 +02:00 |
|
CpuTestSimd.cs
|
Implement CPU FCVT Half <-> Double conversion variants (#3439)
|
2022-07-06 13:40:31 +02:00 |
|
CpuTestSimdCrypto32.cs
|
|
|
|
CpuTestSimdCrypto.cs
|
|
|
|
CpuTestSimdCvt32.cs
|
Fix Vnmls_S fast path (F64: losing input d value). Fix Vnmla_S & Vnmls_S slow paths (using fused inst.s). Fix Vfma_V slow path not using StandardFPSCRValue(). (#1775)
|
2020-12-17 20:43:41 +01:00 |
|
CpuTestSimdCvt.cs
|
Implement FCVTNS (Scalar GP) (#2953)
|
2022-01-19 22:21:44 -03:00 |
|
CpuTestSimdExt.cs
|
|
|
|
CpuTestSimdFcond.cs
|
|
|
|
CpuTestSimdFmov.cs
|
|
|
|
CpuTestSimdImm.cs
|
|
|
|
CpuTestSimdIns.cs
|
|
|
|
CpuTestSimdLogical32.cs
|
Implement VORN (register) Arm32 instruction (#2396)
|
2021-06-23 23:21:23 +02:00 |
|
CpuTestSimdMemory32.cs
|
|
|
|
CpuTestSimdMov32.cs
|
|
|
|
CpuTestSimdReg32.cs
|
Implement Arm32 Sha256 and MRS Rd, CPSR instructions (#3544)
|
2022-08-05 19:03:50 +02:00 |
|
CpuTestSimdReg.cs
|
CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817)
|
2021-01-04 23:45:54 +01:00 |
|
CpuTestSimdRegElem32.cs
|
|
|
|
CpuTestSimdRegElem.cs
|
Add Sqdmulh_Ve & Sqrdmulh_Ve Inst.s with Tests. (#2139)
|
2021-03-25 23:33:32 +01:00 |
|
CpuTestSimdRegElemF.cs
|
|
|
|
CpuTestSimdShImm32.cs
|
|
|
|
CpuTestSimdShImm.cs
|
|
|
|
CpuTestSimdTbl.cs
|
|
|
|
CpuTestSystem.cs
|
|
|
|
CpuTestT32Alu.cs
|
T32: Implement Data Processing (Modified Immediate) instructions (#3178)
|
2022-03-06 22:25:01 +01:00 |
|
CpuTestT32Flow.cs
|
T32: Implement B, B.cond, BL, BLX (#3155)
|
2022-03-04 23:05:08 +01:00 |
|
CpuTestT32Mem.cs
|
T32: Implement load/store single (immediate) (#3186)
|
2022-04-21 01:25:43 +02:00 |
|
CpuTestThumb.cs
|
T32: Implement ALU (shifted register) instructions (#3135)
|
2022-02-22 19:11:28 -03:00 |
|
PrecomputedMemoryThumbTestCase.cs
|
T32: Implement load/store single (immediate) (#3186)
|
2022-04-21 01:25:43 +02:00 |
|
PrecomputedThumbTestCase.cs
|
T32: Implement ALU (shifted register) instructions (#3135)
|
2022-02-22 19:11:28 -03:00 |
