mirror of
https://github.com/ryujinx-mirror/ryujinx.git
synced 2024-12-23 14:54:00 +00:00
e21ebbf666
* Add optimizations related to caller/callee saved registers, thread synchronization and disable tier 0 * Refactoring * Add a config entry to enable or disable the reg load/store opt. * Remove unnecessary register state stores for calls when the callee is know * Rename IoType to VarType * Enable tier 0 while fixing some perf issues related to tier 0 * Small tweak -- Compile before adding to the cache, to avoid lags * Add required config entry
51 lines
1.6 KiB
C#
51 lines
1.6 KiB
C#
using ChocolArm64.State;
|
|
using System.Reflection.Emit;
|
|
|
|
namespace ChocolArm64.Translation
|
|
{
|
|
struct ILOpCodeLoadState : IILEmit
|
|
{
|
|
private ILBlock _block;
|
|
|
|
private bool _isSubEntry;
|
|
|
|
public ILOpCodeLoadState(ILBlock block, bool isSubEntry = false)
|
|
{
|
|
_block = block;
|
|
_isSubEntry = isSubEntry;
|
|
}
|
|
|
|
public void Emit(ILMethodBuilder context)
|
|
{
|
|
long intInputs = context.RegUsage.GetIntInputs(_block);
|
|
long vecInputs = context.RegUsage.GetVecInputs(_block);
|
|
|
|
if (Optimizations.AssumeStrictAbiCompliance && context.IsSubComplete)
|
|
{
|
|
intInputs = RegisterUsage.ClearCallerSavedIntRegs(intInputs, context.IsAarch64);
|
|
vecInputs = RegisterUsage.ClearCallerSavedVecRegs(vecInputs, context.IsAarch64);
|
|
}
|
|
|
|
LoadLocals(context, intInputs, RegisterType.Int);
|
|
LoadLocals(context, vecInputs, RegisterType.Vector);
|
|
}
|
|
|
|
private void LoadLocals(ILMethodBuilder context, long inputs, RegisterType baseType)
|
|
{
|
|
for (int bit = 0; bit < 64; bit++)
|
|
{
|
|
long mask = 1L << bit;
|
|
|
|
if ((inputs & mask) != 0)
|
|
{
|
|
Register reg = ILMethodBuilder.GetRegFromBit(bit, baseType);
|
|
|
|
context.Generator.EmitLdarg(TranslatedSub.StateArgIdx);
|
|
context.Generator.Emit(OpCodes.Ldfld, reg.GetField());
|
|
|
|
context.Generator.EmitStloc(context.GetLocalIndex(reg));
|
|
}
|
|
}
|
|
}
|
|
}
|
|
} |