| .. |
|
CryptoHelper.cs
|
|
|
|
InstEmitAlu32.cs
|
Implement PLD and SUB (imm16) on T32, plus UADD8, SADD8, USUB8 and SSUB8 on both A32 and T32 (#3693)
|
2022-09-13 19:51:40 -03:00 |
|
InstEmitAlu.cs
|
|
|
|
InstEmitAluHelper.cs
|
T32: Add Vfp instructions (#3690)
|
2022-09-10 23:03:14 -03:00 |
|
InstEmitBfm.cs
|
|
|
|
InstEmitCcmp.cs
|
|
|
|
InstEmitCsel.cs
|
|
|
|
InstEmitDiv.cs
|
|
|
|
InstEmitException32.cs
|
|
|
|
InstEmitException.cs
|
|
|
|
InstEmitFlow32.cs
|
T32: Add Vfp instructions (#3690)
|
2022-09-10 23:03:14 -03:00 |
|
InstEmitFlow.cs
|
|
|
|
InstEmitFlowHelper.cs
|
|
|
|
InstEmitHash32.cs
|
|
|
|
InstEmitHash.cs
|
|
|
|
InstEmitHashHelper.cs
|
|
|
|
InstEmitHelper.cs
|
|
|
|
InstEmitMemory32.cs
|
Add ADD (zx imm12), NOP, MOV (rs), LDA, TBB, TBH, MOV (zx imm16) and CLZ thumb instructions (#3683)
|
2022-09-09 22:09:11 -03:00 |
|
InstEmitMemory.cs
|
|
|
|
InstEmitMemoryEx32.cs
|
Implement Thumb (32-bit) memory (ordered), multiply, extension and bitfield instructions (#3687)
|
2022-09-10 22:51:00 -03:00 |
|
InstEmitMemoryEx.cs
|
A32/T32/A64: Implement Hint instructions (CSDB, SEV, SEVL, WFE, WFI, YIELD) (#3694)
|
2022-09-14 18:18:15 -03:00 |
|
InstEmitMemoryExHelper.cs
|
|
|
|
InstEmitMemoryHelper.cs
|
Add ADD (zx imm12), NOP, MOV (rs), LDA, TBB, TBH, MOV (zx imm16) and CLZ thumb instructions (#3683)
|
2022-09-09 22:09:11 -03:00 |
|
InstEmitMove.cs
|
|
|
|
InstEmitMul32.cs
|
Implement Thumb (32-bit) memory (ordered), multiply, extension and bitfield instructions (#3687)
|
2022-09-10 22:51:00 -03:00 |
|
InstEmitMul.cs
|
|
|
|
InstEmitSimdArithmetic32.cs
|
|
|
|
InstEmitSimdArithmetic.cs
|
A64: Add fast path for Fcvtas_Gp/S/V, Fcvtau_Gp/S/V and Frinta_S/V in… (#3712)
|
2022-10-19 00:21:33 +00:00 |
|
InstEmitSimdCmp32.cs
|
Fpsr and Fpcr freed. (#3701)
|
2022-09-20 18:55:13 -03:00 |
|
InstEmitSimdCmp.cs
|
|
|
|
InstEmitSimdCrypto32.cs
|
|
|
|
InstEmitSimdCrypto.cs
|
|
|
|
InstEmitSimdCvt32.cs
|
Do not clear the rejit queue when overlaps count is equal to 0. (#3721)
|
2022-10-19 02:08:34 +00:00 |
|
InstEmitSimdCvt.cs
|
Fix CPU FCVTN instruction implementation (slow path) (#4159)
|
2022-12-21 23:05:58 +00:00 |
|
InstEmitSimdHash32.cs
|
|
|
|
InstEmitSimdHash.cs
|
|
|
|
InstEmitSimdHashHelper.cs
|
|
|
|
InstEmitSimdHelper32.cs
|
A32: Implement VCVTT, VCVTB (#3710)
|
2022-10-19 02:36:04 +02:00 |
|
InstEmitSimdHelper.cs
|
A64: Add fast path for Fcvtas_Gp/S/V, Fcvtau_Gp/S/V and Frinta_S/V in… (#3712)
|
2022-10-19 00:21:33 +00:00 |
|
InstEmitSimdLogical32.cs
|
|
|
|
InstEmitSimdLogical.cs
|
Revert "ARMeilleure: Add initial support for AVX512(EVEX encoding) (#3663)" (#4145)
|
2022-12-18 20:21:10 -03:00 |
|
InstEmitSimdMemory32.cs
|
Fix increment on Arm32 NEON VLDn/VSTn instructions with regs > 1 (#3695)
|
2022-09-13 08:24:09 +02:00 |
|
InstEmitSimdMemory.cs
|
|
|
|
InstEmitSimdMove32.cs
|
|
|
|
InstEmitSimdMove.cs
|
|
|
|
InstEmitSimdShift32.cs
|
Fpsr and Fpcr freed. (#3701)
|
2022-09-20 18:55:13 -03:00 |
|
InstEmitSimdShift.cs
|
ARMeilleure: Add gfni acceleration (#3669)
|
2022-10-02 11:17:19 +02:00 |
|
InstEmitSystem32.cs
|
Fpsr and Fpcr freed. (#3701)
|
2022-09-20 18:55:13 -03:00 |
|
InstEmitSystem.cs
|
Fpsr and Fpcr freed. (#3701)
|
2022-09-20 18:55:13 -03:00 |
|
InstName.cs
|
A32/T32/A64: Implement Hint instructions (CSDB, SEV, SEVL, WFE, WFI, YIELD) (#3694)
|
2022-09-14 18:18:15 -03:00 |
|
NativeInterface.cs
|
Fpsr and Fpcr freed. (#3701)
|
2022-09-20 18:55:13 -03:00 |
|
SoftFallback.cs
|
Fpsr and Fpcr freed. (#3701)
|
2022-09-20 18:55:13 -03:00 |
|
SoftFloat.cs
|
Fpsr and Fpcr freed. (#3701)
|
2022-09-20 18:55:13 -03:00 |
