ryujinx/ARMeilleure/Translation
LDj3SNuD 62585755fd
Do not clear the rejit queue when overlaps count is equal to 0. (#3721)
* Do not clear the rejit queue when overlaps count is equal to 0.

* Ptc and PtcProfiler must be invalidated.

* Revert "Ptc and PtcProfiler must be invalidated."

This reverts commit f5b0ad9d7dc3c0b3a0da184de4d04d7234939c81.

* Fix #3710 slow path due to #3701.
2022-10-19 02:08:34 +00:00
..
Cache misc: Migrate usage of RuntimeInformation to OperatingSystem (#2901) 2021-12-04 20:02:30 -03:00
PTC A64: Add fast path for Fcvtas_Gp/S/V, Fcvtau_Gp/S/V and Frinta_S/V in… (#3712) 2022-10-19 00:21:33 +00:00
ArmEmitterContext.cs ARMeilleure: Thumb support (All T16 instructions) (#3105) 2022-02-17 19:39:45 -03:00
Compiler.cs Add an early TailMerge pass (#2721) 2021-10-18 19:51:22 -03:00
CompilerContext.cs
CompilerOptions.cs Refactor PtcInfo (#2625) 2021-09-14 01:23:37 +02:00
ControlFlowGraph.cs Implement some 32-bit Thumb instructions (#3614) 2022-08-25 09:59:34 +00:00
DelegateHelper.cs
DelegateInfo.cs
Delegates.cs Fpsr and Fpcr freed. (#3701) 2022-09-20 18:55:13 -03:00
DispatcherFunction.cs
Dominance.cs
EmitterContext.cs Add host CPU memory barriers for DMB/DSB and ordered load/store (#3015) 2022-01-21 12:47:34 -03:00
GuestFunction.cs
IntervalTree.cs Optimize kernel memory block lookup and consolidate RBTree implementations (#3410) 2022-08-26 18:21:48 +00:00
RegisterToLocal.cs
RegisterUsage.cs Add an early TailMerge pass (#2721) 2021-10-18 19:51:22 -03:00
RejitRequest.cs
SsaConstruction.cs Collapse AsSpan().Slice(..) calls into AsSpan(..) (#3145) 2022-02-22 10:32:10 -03:00
SsaDeconstruction.cs
TranslatedFunction.cs
Translator.cs Do not clear the rejit queue when overlaps count is equal to 0. (#3721) 2022-10-19 02:08:34 +00:00
TranslatorCache.cs Enable CPU JIT cache invalidation (#2965) 2022-02-18 02:53:18 +01:00
TranslatorQueue.cs Clean up rejit queue (#2751) 2022-09-08 20:14:08 -03:00
TranslatorStubs.cs Refactor PtcInfo (#2625) 2021-09-14 01:23:37 +02:00