LDj3SNuD 42e4e02a64 Add Fcvtns_S, Fcvtns_V, Fcvtnu_S, Fcvtnu_V (AOpCodeSimd) FP & Umlal_V, Umlsl_V, Saddl_V, Ssubl_V, Usubl_V instructions; add 8 FP & 16 S/Umlal_V, S/Umlsl_V, S/Uaddl_V, S/Usubl_V Tests. (#390) ... * Update AOpCodeTable.cs * Update AInstEmitSimdCvt.cs * Update Pseudocode.cs * Update Instructions.cs * Update CpuTestSimd.cs * Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs * Update Instructions.cs * Update CpuTestSimdReg.cs * Update CpuTestSimd.cs * Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs * Update Instructions.cs * Update CpuTestSimdReg.cs * Add QCFlagBit. * Add QCFlagBit.		2018-09-01 11:52:51 -03:00
..
ACryptoHelper.cs	Add AESD, AESE, AESIMC, AESMC instructions; add 4 simple Tests (closed box). (#365)	2018-08-20 01:20:26 -03:00
AInst.cs
AInstEmitAlu.cs	Remove broken adds/cmn with condition check optimization (#218)	2018-07-03 21:54:05 -03:00
AInstEmitAluHelper.cs
AInstEmitBfm.cs
AInstEmitCcmp.cs
AInstEmitCsel.cs
AInstEmitException.cs	Implement SvcGetThreadContext3	2018-06-26 01:10:15 -03:00
AInstEmitFlow.cs
AInstEmitHash.cs
AInstEmitMemory.cs
AInstEmitMemoryEx.cs	Fix load/store exclusive/atomic pairwise instructions (#337)	2018-08-10 01:14:27 -03:00
AInstEmitMemoryHelper.cs	More flexible memory manager (#307)	2018-08-15 15:59:51 -03:00
AInstEmitMove.cs
AInstEmitMul.cs
AInstEmitSimdArithmetic.cs	Add Fcvtns_S, Fcvtns_V, Fcvtnu_S, Fcvtnu_V (AOpCodeSimd) FP & Umlal_V, Umlsl_V, Saddl_V, Ssubl_V, Usubl_V instructions; add 8 FP & 16 S/Umlal_V, S/Umlsl_V, S/Uaddl_V, S/Usubl_V Tests. (#390)	2018-09-01 11:52:51 -03:00
AInstEmitSimdCmp.cs	Zero out bits 63:32 of scalar float operations with SSE intrinsics (#273)	2018-08-14 23:54:12 -03:00
AInstEmitSimdCrypto.cs	Add AESD, AESE, AESIMC, AESMC instructions; add 4 simple Tests (closed box). (#365)	2018-08-20 01:20:26 -03:00
AInstEmitSimdCvt.cs	Add Fcvtns_S, Fcvtns_V, Fcvtnu_S, Fcvtnu_V (AOpCodeSimd) FP & Umlal_V, Umlsl_V, Saddl_V, Ssubl_V, Usubl_V instructions; add 8 FP & 16 S/Umlal_V, S/Umlsl_V, S/Uaddl_V, S/Usubl_V Tests. (#390)	2018-09-01 11:52:51 -03:00
AInstEmitSimdHash.cs	Add SHA256H, SHA256H2, SHA256SU0, SHA256SU1 instructions; add 4 Tests (closed box). (#352)	2018-08-16 21:44:44 -03:00
AInstEmitSimdHelper.cs	Zero out bits 63:32 of scalar float operations with SSE intrinsics (#273)	2018-08-14 23:54:12 -03:00
AInstEmitSimdLogical.cs	Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions, nits (#225)	2018-07-14 13:13:02 -03:00
AInstEmitSimdMemory.cs	Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions, nits (#225)	2018-07-14 13:13:02 -03:00
AInstEmitSimdMove.cs	Implement Ssubw_V and Usubw_V instructions. (#287)	2018-07-18 21:06:28 -03:00
AInstEmitSimdShift.cs	Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions, nits (#225)	2018-07-14 13:13:02 -03:00
AInstEmitSystem.cs
AInstEmitter.cs
AInstInterpreter.cs
ASoftFallback.cs	Add AESD, AESE, AESIMC, AESMC instructions; add 4 simple Tests (closed box). (#365)	2018-08-20 01:20:26 -03:00
ASoftFloat.cs	Fix silly copy/paste error on float variant of the FMINNM instruction	2018-08-05 18:56:30 -03:00
AVectorHelper.cs	Zero out bits 63:32 of scalar float operations with SSE intrinsics (#273)	2018-08-14 23:54:12 -03:00