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AInst.cs
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Initial work to support AArch32 with a interpreter, plus nvmm stubs (not used for now)
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2018-05-26 17:50:47 -03:00 |
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AInstEmitAlu.cs
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Remove broken adds/cmn with condition check optimization (#218)
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2018-07-03 21:54:05 -03:00 |
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AInstEmitAluHelper.cs
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Fix corner cases of ADCS and SBFM
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2018-02-26 15:56:34 -03:00 |
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AInstEmitBfm.cs
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Fix corner cases of ADCS and SBFM
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2018-02-26 15:56:34 -03:00 |
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AInstEmitCcmp.cs
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AInstEmitCsel.cs
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AInstEmitException.cs
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Implement SvcGetThreadContext3
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2018-06-26 01:10:15 -03:00 |
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AInstEmitFlow.cs
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Stub a few services, add support for generating call stacks on the CPU
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2018-04-22 01:22:46 -03:00 |
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AInstEmitHash.cs
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Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183)
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2018-06-25 22:32:29 -03:00 |
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AInstEmitMemory.cs
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Fix mistake on astc conversion, make some static methods that shouldn't be public private, remove old commmented out code
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2018-06-02 11:44:52 -03:00 |
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AInstEmitMemoryEx.cs
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Fix some thread sync issues (#172)
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2018-06-21 23:05:42 -03:00 |
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AInstEmitMemoryHelper.cs
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Improved logging (#103)
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2018-04-24 15:57:39 -03:00 |
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AInstEmitMove.cs
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AInstEmitMul.cs
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AInstEmitSimdArithmetic.cs
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ChocolArm64: More accurate implementation of Frecpe & Frecps (#228)
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2018-07-08 16:54:47 -03:00 |
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AInstEmitSimdCmp.cs
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Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. (#183)
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2018-06-25 22:32:29 -03:00 |
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AInstEmitSimdCvt.cs
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AInstEmitSimdCvt: Half-precision to single-precision conversion (#235)
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2018-07-12 15:51:02 -03:00 |
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AInstEmitSimdHelper.cs
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ChocolArm64: More accurate implementation of Frecpe & Frecps (#228)
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2018-07-08 16:54:47 -03:00 |
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AInstEmitSimdLogical.cs
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Add Rbit_V instruction. Add 8 tests (Rbit_V; Rev16_V, Rev32_V, Rev64_V). Improve CountSetBits8() algorithm. (#212)
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2018-07-03 03:31:16 -03:00 |
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AInstEmitSimdMemory.cs
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AInstEmitSimdMove.cs
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Fix ZIP/UZP/TRN instructions when Rd == Rn || Rd == Rm (#239)
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2018-07-09 22:48:28 -03:00 |
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AInstEmitSimdShift.cs
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CPU fix for the cases using a Mask with shift = 0
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2018-03-14 01:59:22 -03:00 |
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AInstEmitSystem.cs
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Add pl:u stub, use higher precision on CNTPCT_EL0 register tick count
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2018-03-13 21:24:32 -03:00 |
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AInstEmitter.cs
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AInstInterpreter.cs
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Initial work to support AArch32 with a interpreter, plus nvmm stubs (not used for now)
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2018-05-26 17:50:47 -03:00 |
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ASoftFallback.cs
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Add Rbit_V instruction. Add 8 tests (Rbit_V; Rev16_V, Rev32_V, Rev64_V). Improve CountSetBits8() algorithm. (#212)
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2018-07-03 03:31:16 -03:00 |
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ASoftFloat.cs
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AInstEmitSimdCvt: Half-precision to single-precision conversion (#235)
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2018-07-12 15:51:02 -03:00 |
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AVectorHelper.cs
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Add Rbit_V instruction. Add 8 tests (Rbit_V; Rev16_V, Rev32_V, Rev64_V). Improve CountSetBits8() algorithm. (#212)
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2018-07-03 03:31:16 -03:00 |
