ryujinx/ChocolArm64/Instruction
LDj3SNuD 262b5b8054 Add TRN1 & TRN2 (vector) instructions. Add 4 simple tests (4S, 8B). (#77)
* Update AOpCodeTable.cs

* Update AInstEmitSimdMove.cs

* Update CpuTestSimdMove.cs

* Update AInstEmitSimdMove.cs

* Update CpuTestSimdMove.cs
2018-04-12 11:52:00 -03:00
..
AInst.cs
AInstEmitAlu.cs Add Cls Instruction. (#67) 2018-03-23 22:06:05 -03:00
AInstEmitAluHelper.cs
AInstEmitBfm.cs
AInstEmitCcmp.cs
AInstEmitCsel.cs
AInstEmitException.cs
AInstEmitFlow.cs
AInstEmitHash.cs Remove unused function from CPU 2018-03-14 00:57:07 -03:00
AInstEmitMemory.cs
AInstEmitMemoryEx.cs
AInstEmitMemoryHelper.cs
AInstEmitMove.cs
AInstEmitMul.cs
AInstEmitSimdArithmetic.cs Add FMUL (scalar, by element) instruction; add FRECPE, FRECPS (scalar & vector) instructions. Add 5 simple tests. (#74) 2018-04-08 16:08:57 -03:00
AInstEmitSimdCmp.cs Fix FRSQRTS and FCM* (scalar) instructions 2018-04-06 10:20:17 -03:00
AInstEmitSimdCvt.cs
AInstEmitSimdHelper.cs Add FMUL (scalar, by element) instruction; add FRECPE, FRECPS (scalar & vector) instructions. Add 5 simple tests. (#74) 2018-04-08 16:08:57 -03:00
AInstEmitSimdLogical.cs Add BIT instruction 2018-03-30 16:46:00 -03:00
AInstEmitSimdMemory.cs
AInstEmitSimdMove.cs Add TRN1 & TRN2 (vector) instructions. Add 4 simple tests (4S, 8B). (#77) 2018-04-12 11:52:00 -03:00
AInstEmitSimdShift.cs CPU fix for the cases using a Mask with shift = 0 2018-03-14 01:59:22 -03:00
AInstEmitSystem.cs Add pl:u stub, use higher precision on CNTPCT_EL0 register tick count 2018-03-13 21:24:32 -03:00
AInstEmitter.cs
ASoftFallback.cs [CPU] Fix CNT instruction 2018-04-10 20:58:32 -03:00
ASoftFloat.cs Implement Frsqrte_S (#72) 2018-04-05 20:36:19 -03:00