LDj3SNuD 00d4f44bbb Add Sse Opt. for S/Uaddl_V, S/Uhadd_V, S/Uhsub_V, S/Umlal_V, S/Umlsl_V, S/Urhadd_V, S/Usubl_V Inst.; and for S/Urshr_V, S/Ursra_V Inst.. (#480) ... * Update AILEmitterCtx.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdShift.cs		2018-10-25 19:10:41 -03:00
..
Decoder	Add Fmls_Se, Fmulx_Se/Ve, Smov_S Inst.; Opt. Clz/Clz_V, Cnt_V, Shl_V, S/Ushr_V, S/Usra_V Inst.; Add 11 Tests. Some fixes. (#449)	2018-10-13 23:35:16 -03:00
Decoder32
Events	Print stack trace on invalid memory accesses (#461)	2018-10-20 22:07:52 +00:00
Exceptions
Instruction	Add Sse Opt. for S/Uaddl_V, S/Uhadd_V, S/Uhsub_V, S/Umlal_V, S/Umlsl_V, S/Urhadd_V, S/Usubl_V Inst.; and for S/Urshr_V, S/Ursra_V Inst.. (#480)	2018-10-25 19:10:41 -03:00
Instruction32
Memory	Print stack trace on invalid memory accesses (#461)	2018-10-20 22:07:52 +00:00
State	Fix Fcvtl_V and Fcvtn_V; fix half to float conv. and add float to half conv. (full FP emu.). Add 4 FP Tests. (#468)	2018-10-23 11:12:45 -03:00
Translation	Add Sse Opt. for S/Uaddl_V, S/Uhadd_V, S/Uhsub_V, S/Umlal_V, S/Umlsl_V, S/Urhadd_V, S/Usubl_V Inst.; and for S/Urshr_V, S/Ursra_V Inst.. (#480)	2018-10-25 19:10:41 -03:00
ABitUtils.cs
AOpCodeTable.cs	Add Fmls_Se, Fmulx_Se/Ve, Smov_S Inst.; Opt. Clz/Clz_V, Cnt_V, Shl_V, S/Ushr_V, S/Usra_V Inst.; Add 11 Tests. Some fixes. (#449)	2018-10-13 23:35:16 -03:00
AOptimizations.cs	Add 9+7 fast/slow FP inst. impls.; add 14 FP Tests. (#437)	2018-10-05 22:45:59 -03:00
AThread.cs
ATranslatedSub.cs
ATranslatedSubType.cs
ATranslator.cs
ATranslatorCache.cs	Tweak cpu cache deletion policy values (#433)	2018-10-07 23:40:37 -03:00
ChocolArm64.csproj