gdkchan 0b52ee6627 Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics (#405) ... * Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics, some CQ improvements * Remove useless space * Address PR feedback * Revert EmitVectorZero32_128 changes		2018-09-26 23:30:21 -03:00
..
ACryptoHelper.cs	Add AESD, AESE, AESIMC, AESMC instructions; add 4 simple Tests (closed box). (#365)	2018-08-20 01:20:26 -03:00
AInst.cs
AInstEmitAlu.cs	Remove broken adds/cmn with condition check optimization (#218)	2018-07-03 21:54:05 -03:00
AInstEmitAluHelper.cs
AInstEmitBfm.cs
AInstEmitCcmp.cs
AInstEmitCsel.cs
AInstEmitException.cs
AInstEmitFlow.cs	Remove cold methods from the CPU cache (#224)	2018-09-19 17:07:56 -03:00
AInstEmitHash.cs
AInstEmitMemory.cs
AInstEmitMemoryEx.cs	Thread scheduler rewrite (#393)	2018-09-18 20:36:43 -03:00
AInstEmitMemoryHelper.cs	More flexible memory manager (#307)	2018-08-15 15:59:51 -03:00
AInstEmitMove.cs
AInstEmitMul.cs
AInstEmitSimdArithmetic.cs	Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics (#405)	2018-09-26 23:30:21 -03:00
AInstEmitSimdCmp.cs	Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics (#405)	2018-09-26 23:30:21 -03:00
AInstEmitSimdCrypto.cs	Add AESD, AESE, AESIMC, AESMC instructions; add 4 simple Tests (closed box). (#365)	2018-08-20 01:20:26 -03:00
AInstEmitSimdCvt.cs	Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics (#405)	2018-09-26 23:30:21 -03:00
AInstEmitSimdHash.cs	Add SHA256H, SHA256H2, SHA256SU0, SHA256SU1 instructions; add 4 Tests (closed box). (#352)	2018-08-16 21:44:44 -03:00
AInstEmitSimdHelper.cs	Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics (#405)	2018-09-26 23:30:21 -03:00
AInstEmitSimdLogical.cs	Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics (#405)	2018-09-26 23:30:21 -03:00
AInstEmitSimdMemory.cs	Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions, nits (#225)	2018-07-14 13:13:02 -03:00
AInstEmitSimdMove.cs	Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics (#405)	2018-09-26 23:30:21 -03:00
AInstEmitSimdShift.cs	Fix/Add 1+12 [Saturating] [Rounded] Shift Right Narrow (imm.) Instructions; add 14 Tests. Add 6 Tests for PR#405. Add 2 Tests for PR#412. (#409)	2018-09-17 01:54:05 -03:00
AInstEmitSystem.cs
AInstEmitter.cs
AInstInterpreter.cs
ASoftFallback.cs	Fix/Add 10 Shift Right and Mls_Ve Instructions; add 14 Tests. (#407)	2018-09-08 14:24:29 -03:00
ASoftFloat.cs	Fix silly copy/paste error on float variant of the FMINNM instruction	2018-08-05 18:56:30 -03:00
AVectorHelper.cs	Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics (#405)	2018-09-26 23:30:21 -03:00