mirror of
https://github.com/aircrack-ng/rtl8812au.git
synced 2024-11-30 00:47:38 +00:00
518 lines
15 KiB
C
518 lines
15 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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/*************************************************************
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* include files
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************************************************************/
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#include "mp_precomp.h"
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#include "phydm_precomp.h"
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#ifdef CONFIG_DYNAMIC_TX_TWR
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#ifdef BB_RAM_SUPPORT
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void
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phydm_2ndtype_dtp_init(void *dm_void)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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u8 pwr_offset_minus3, pwr_offset_minus7;
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/*@ 2's com, for offset 3dB and 7dB, which 1 step will be 0.25dB*/
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pwr_offset_minus3 = BIT(7) | 0x74;
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pwr_offset_minus7 = BIT(7) | 0x64;
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odm_set_bb_reg(dm, 0x1e70, 0x00ff0000, pwr_offset_minus3);
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odm_set_bb_reg(dm, 0x1e70, 0xff000000, pwr_offset_minus7);
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};
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void
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phdm_2ndtype_rd_ram_pwr(void *dm_void, u8 macid)
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{
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};
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void
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phdm_2ndtype_wt_ram_pwr(void *dm_void, u8 macid, boolean pwr_offset0_en,
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boolean pwr_offset1_en, s8 pwr_offset0, s8 pwr_offset1)
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{
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u32 reg_io_0x1e84 = 0;
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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struct phydm_bb_ram_per_sta *dm_ram_per_sta = NULL;
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dm_ram_per_sta = &dm->p_bb_ram_ctrl.pram_sta_ctrl[macid];
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dm_ram_per_sta->tx_pwr_offset0_en = pwr_offset0_en;
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dm_ram_per_sta->tx_pwr_offset1_en = pwr_offset1_en;
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dm_ram_per_sta->tx_pwr_offset0 = pwr_offset0;
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dm_ram_per_sta->tx_pwr_offset1 = pwr_offset1;
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reg_io_0x1e84 = (dm_ram_per_sta->hw_igi_en<<7) + dm_ram_per_sta->hw_igi;
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reg_io_0x1e84 |= (pwr_offset0_en<<15) + ((pwr_offset0&0x7f)<<8);
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reg_io_0x1e84 |= (pwr_offset1_en<<23) + ((pwr_offset1&0x7f)<<16);
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reg_io_0x1e84 |= (macid&0x3f)<<24;
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reg_io_0x1e84 |= BIT(30);
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odm_set_bb_reg(dm, 0x1e84, 0xffffffff, reg_io_0x1e84);
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};
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u8 phydm_pwr_lv_mapping_2ndtype(u8 tx_pwr_lv)
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{
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if (tx_pwr_lv == tx_high_pwr_level_level3)
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/*PHYDM_2ND_OFFSET_MINUS_11DB;*/
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return PHYDM_2ND_OFFSET_MINUS_7DB;
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else if (tx_pwr_lv == tx_high_pwr_level_level2)
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return PHYDM_2ND_OFFSET_MINUS_7DB;
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else if (tx_pwr_lv == tx_high_pwr_level_level1)
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return PHYDM_2ND_OFFSET_MINUS_3DB;
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else
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return PHYDM_2ND_OFFSET_ZERO;
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}
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void phydm_dtp_fill_cmninfo_2ndtype(void *dm_void, u8 macid, u8 dtp_lvl)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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struct dtp_info *dtp = NULL;
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dtp = &dm->phydm_sta_info[macid]->dtp_stat;
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if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
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return;
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dtp->dyn_tx_power = phydm_pwr_lv_mapping_2ndtype(dtp_lvl);
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PHYDM_DBG(dm, DBG_DYN_TXPWR,
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"Fill cmninfo TxPwr: macid=(%d), PwrLv (%d)\n", macid,
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dtp->dyn_tx_power);
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/* dyn_tx_power is 2 bit at 8822C/14B/98F/12F*/
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}
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#endif
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boolean
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phydm_check_rates(void *dm_void, u8 rate_idx)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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u32 check_rate_bitmap0 = 0x08080808; /* @check CCK11M, OFDM54M, MCS7, MCS15*/
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u32 check_rate_bitmap1 = 0x80200808; /* @check MCS23, MCS31, VHT1SS M9, VHT2SS M9*/
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u32 check_rate_bitmap2 = 0x00080200; /* @check VHT3SS M9, VHT4SS M9*/
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u32 bitmap_result;
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#if (RTL8822B_SUPPORT == 1)
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if (dm->support_ic_type & ODM_RTL8822B) {
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check_rate_bitmap2 &= 0;
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check_rate_bitmap1 &= 0xfffff000;
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check_rate_bitmap0 &= 0x0fffffff;
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}
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#endif
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#if (RTL8197F_SUPPORT == 1)
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if (dm->support_ic_type & ODM_RTL8197F) {
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check_rate_bitmap2 &= 0;
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check_rate_bitmap1 &= 0;
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check_rate_bitmap0 &= 0x0fffffff;
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}
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#endif
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#if (RTL8192E_SUPPORT == 1)
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if (dm->support_ic_type & ODM_RTL8192E) {
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check_rate_bitmap2 &= 0;
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check_rate_bitmap1 &= 0;
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check_rate_bitmap0 &= 0x0fffffff;
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}
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#endif
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/*@jj add 20170822*/
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#if (RTL8192F_SUPPORT == 1)
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if (dm->support_ic_type & ODM_RTL8192F) {
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check_rate_bitmap2 &= 0;
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check_rate_bitmap1 &= 0;
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check_rate_bitmap0 &= 0x0fffffff;
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}
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#endif
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#if (RTL8721D_SUPPORT == 1)
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if (dm->support_ic_type & ODM_RTL8721D) {
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check_rate_bitmap2 &= 0;
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check_rate_bitmap1 &= 0;
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check_rate_bitmap0 &= 0x000fffff;
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}
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#endif
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#if (RTL8821C_SUPPORT == 1)
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if (dm->support_ic_type & ODM_RTL8821C) {
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check_rate_bitmap2 &= 0;
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check_rate_bitmap1 &= 0x003ff000;
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check_rate_bitmap0 &= 0x000fffff;
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}
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#endif
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if (rate_idx >= 64)
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bitmap_result = BIT(rate_idx - 64) & check_rate_bitmap2;
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else if (rate_idx >= 32)
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bitmap_result = BIT(rate_idx - 32) & check_rate_bitmap1;
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else if (rate_idx <= 31)
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bitmap_result = BIT(rate_idx) & check_rate_bitmap0;
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if (bitmap_result != 0)
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return true;
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else
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return false;
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}
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enum rf_path
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phydm_check_paths(void *dm_void)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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enum rf_path max_path = RF_PATH_A;
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if (dm->num_rf_path == 1)
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max_path = RF_PATH_A;
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if (dm->num_rf_path == 2)
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max_path = RF_PATH_B;
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if (dm->num_rf_path == 3)
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max_path = RF_PATH_C;
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if (dm->num_rf_path == 4)
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max_path = RF_PATH_D;
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return max_path;
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}
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#ifndef PHYDM_COMMON_API_SUPPORT
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u8 phydm_dtp_get_txagc(void *dm_void, enum rf_path path, u8 hw_rate)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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u8 ret = 0xff;
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#if (RTL8192E_SUPPORT == 1)
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ret = config_phydm_read_txagc_n(dm, path, hw_rate);
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#endif
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return ret;
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}
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#endif
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u8 phydm_search_min_power_index(void *dm_void)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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enum rf_path path;
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enum rf_path max_path;
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u8 min_gain_index = 0x3f;
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u8 gain_index;
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u8 rate_idx;
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PHYDM_DBG(dm, DBG_DYN_TXPWR, "%s\n", __func__);
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max_path = phydm_check_paths(dm);
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for (path = 0; path <= max_path; path++)
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for (rate_idx = 0; rate_idx < 84; rate_idx++)
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if (phydm_check_rates(dm, rate_idx)) {
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#ifdef PHYDM_COMMON_API_SUPPORT
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/*This is for API support IC : 97F,8822B,92F,8821C*/
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gain_index = phydm_api_get_txagc(dm, path, rate_idx);
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#else
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/*This is for API non-support IC : 92E */
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gain_index = phydm_dtp_get_txagc(dm, path, rate_idx);
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#endif
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if (gain_index == 0xff) {
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min_gain_index = 0x20;
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PHYDM_DBG(dm, DBG_DYN_TXPWR,
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"Error Gain idx!! Rewite to: ((%d))\n", min_gain_index);
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break;
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}
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PHYDM_DBG(dm, DBG_DYN_TXPWR,
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"Support Rate: ((%d)) -> Gain idx: ((%d))\n",
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rate_idx, gain_index);
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if (gain_index < min_gain_index)
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min_gain_index = gain_index;
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}
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return min_gain_index;
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}
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void phydm_dynamic_tx_power_init(void *dm_void)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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u8 i;
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dm->last_dtp_lvl = tx_high_pwr_level_normal;
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dm->dynamic_tx_high_power_lvl = tx_high_pwr_level_normal;
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for (i = 0; i < 3; i++) {
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dm->enhance_pwr_th[i] = 0xff;
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}
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dm->set_pwr_th[0] = TX_POWER_NEAR_FIELD_THRESH_LVL1;
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dm->set_pwr_th[1] = TX_POWER_NEAR_FIELD_THRESH_LVL2;
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dm->set_pwr_th[2] = 0xff;
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dm->min_power_index = phydm_search_min_power_index(dm);
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PHYDM_DBG(dm, DBG_DYN_TXPWR, "DTP init: Min Gain idx: ((%d))\n",
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dm->min_power_index);
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}
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void phydm_noisy_enhance_hp_th(void *dm_void, u8 noisy_state)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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if (noisy_state == 0) {
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dm->enhance_pwr_th[0] = dm->set_pwr_th[0];
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dm->enhance_pwr_th[1] = dm->set_pwr_th[1];
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dm->enhance_pwr_th[2] = dm->set_pwr_th[2];
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} else {
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dm->enhance_pwr_th[0] = dm->set_pwr_th[0] + 8;
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dm->enhance_pwr_th[1] = dm->set_pwr_th[1] + 5;
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dm->enhance_pwr_th[2] = dm->set_pwr_th[2];
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}
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PHYDM_DBG(dm, DBG_DYN_TXPWR,
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"DTP hp_th: Lv1_th =%d ,Lv2_th = %d ,Lv3_th = %d\n",
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dm->enhance_pwr_th[0], dm->enhance_pwr_th[1],
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dm->enhance_pwr_th[2]);
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}
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u8 phydm_pwr_lvl_check(void *dm_void, u8 input_rssi)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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u8 th0,th1,th2;
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th2 = dm->enhance_pwr_th[2];
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th1 = dm->enhance_pwr_th[1];
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th0 = dm->enhance_pwr_th[0];
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if (input_rssi >= th2)
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return tx_high_pwr_level_level3;
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else if (input_rssi < (th2 - 3) && input_rssi >= th1)
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return tx_high_pwr_level_level2;
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else if (input_rssi < (th1 - 3) && input_rssi >= th0)
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return tx_high_pwr_level_level1;
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else if (input_rssi < (th0 - 3))
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return tx_high_pwr_level_normal;
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else
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return tx_high_pwr_level_unchange;
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}
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u8 phydm_pwr_lv_mapping(u8 tx_pwr_lv)
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{
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if (tx_pwr_lv == tx_high_pwr_level_level3)
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return PHYDM_OFFSET_MINUS_11DB;
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else if (tx_pwr_lv == tx_high_pwr_level_level2)
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return PHYDM_OFFSET_MINUS_7DB;
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else if (tx_pwr_lv == tx_high_pwr_level_level1)
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return PHYDM_OFFSET_MINUS_3DB;
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else
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return PHYDM_OFFSET_ZERO;
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}
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void phydm_dynamic_response_power(void *dm_void)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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u8 rpwr;
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if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
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return;
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if (dm->dynamic_tx_high_power_lvl == tx_high_pwr_level_unchange) {
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dm->dynamic_tx_high_power_lvl = dm->last_dtp_lvl;
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PHYDM_DBG(dm, DBG_DYN_TXPWR, "RespPwr not change\n");
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return;
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}
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PHYDM_DBG(dm, DBG_DYN_TXPWR,
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"RespPwr update_DTP_lv: ((%d)) -> ((%d))\n", dm->last_dtp_lvl,
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dm->dynamic_tx_high_power_lvl);
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dm->last_dtp_lvl = dm->dynamic_tx_high_power_lvl;
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rpwr = phydm_pwr_lv_mapping(dm->dynamic_tx_high_power_lvl);
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odm_set_mac_reg(dm, ODM_REG_RESP_TX_11AC, BIT(20) | BIT(19) | BIT(18), rpwr);
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PHYDM_DBG(dm, DBG_DYN_TXPWR, "RespPwr Set TxPwr: Lv (%d)\n",
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dm->dynamic_tx_high_power_lvl);
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}
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void phydm_dtp_fill_cmninfo(void *dm_void, u8 macid, u8 dtp_lvl)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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struct dtp_info *dtp = NULL;
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dtp = &dm->phydm_sta_info[macid]->dtp_stat;
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if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
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return;
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dtp->dyn_tx_power = phydm_pwr_lv_mapping(dtp_lvl);
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PHYDM_DBG(dm, DBG_DYN_TXPWR,
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"Fill cmninfo TxPwr: macid=(%d), PwrLv (%d)\n", macid,
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dtp->dyn_tx_power);
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}
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void phydm_dtp_per_sta(void *dm_void, u8 macid)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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struct cmn_sta_info *sta = dm->phydm_sta_info[macid];
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struct dtp_info *dtp = NULL;
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struct rssi_info *rssi = NULL;
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if (is_sta_active(sta)) {
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dtp = &sta->dtp_stat;
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rssi = &sta->rssi_stat;
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dtp->sta_tx_high_power_lvl = phydm_pwr_lvl_check(dm, rssi->rssi);
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PHYDM_DBG(dm, DBG_DYN_TXPWR,
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"STA=%d , RSSI: %d , GetPwrLv: %d\n", macid,
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rssi->rssi, dtp->sta_tx_high_power_lvl);
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if (dtp->sta_tx_high_power_lvl == tx_high_pwr_level_unchange
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|| dtp->sta_tx_high_power_lvl == dtp->sta_last_dtp_lvl) {
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dtp->sta_tx_high_power_lvl = dtp->sta_last_dtp_lvl;
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PHYDM_DBG(dm, DBG_DYN_TXPWR,
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"DTP_lv not change: ((%d))\n",
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dtp->sta_tx_high_power_lvl);
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return;
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}
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PHYDM_DBG(dm, DBG_DYN_TXPWR,
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"DTP_lv update: ((%d)) -> ((%d))\n", dm->last_dtp_lvl,
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dm->dynamic_tx_high_power_lvl);
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dtp->sta_last_dtp_lvl = dtp->sta_tx_high_power_lvl;
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#ifdef BB_RAM_SUPPORT
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phydm_dtp_fill_cmninfo_2ndtype(dm, macid, dtp->sta_tx_high_power_lvl);
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#else
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phydm_dtp_fill_cmninfo(dm, macid, dtp->sta_tx_high_power_lvl);
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#endif
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}
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}
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void odm_set_dyntxpwr(void *dm_void, u8 *desc, u8 macid)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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struct dtp_info *dtp = NULL;
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dtp = &dm->phydm_sta_info[macid]->dtp_stat;
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if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
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return;
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if (dm->fill_desc_dyntxpwr)
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dm->fill_desc_dyntxpwr(dm, desc, dtp->dyn_tx_power);
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else
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PHYDM_DBG(dm, DBG_DYN_TXPWR,
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"%s: fill_desc_dyntxpwr is null!\n", __func__);
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if (dtp->last_tx_power != dtp->dyn_tx_power) {
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PHYDM_DBG(dm, DBG_DYN_TXPWR,
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"%s: last_offset=%d, txpwr_offset=%d\n", __func__,
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dtp->last_tx_power, dtp->dyn_tx_power);
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dtp->last_tx_power = dtp->dyn_tx_power;
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}
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}
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void phydm_dtp_debug(void *dm_void, char input[][16], u32 *_used, char *output,
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u32 *_out_len)
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{
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u32 used = *_used;
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u32 out_len = *_out_len;
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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char help[] = "-h";
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u32 var1[3] = {0};
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u8 set_pwr_th1, set_pwr_th2, set_pwr_th3;
|
|
u8 i;
|
|
|
|
if ((strcmp(input[1], help) == 0)) {
|
|
PDM_SNPF(out_len, used, output + used, out_len - used,
|
|
"Set DTP threhosld: {1} {TH[0]} {TH[1]} {TH[2]}\n");
|
|
} else {
|
|
for (i = 0; i < 3; i++) {
|
|
if (input[i + 1])
|
|
PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]);
|
|
}
|
|
if (var1[0] == 1) {
|
|
for (i = 0; i < 3; i++)
|
|
if (var1[i] == 0 || var1[i] > 100)
|
|
dm->set_pwr_th[i] = 0xff;
|
|
else
|
|
dm->set_pwr_th[i] = (u8)var1[1 + i];
|
|
|
|
PDM_SNPF(out_len, used, output + used, out_len - used,
|
|
"DTP_TH[0:2] = {%d, %d, %d}\n",
|
|
dm->set_pwr_th[0], dm->set_pwr_th[1],
|
|
dm->set_pwr_th[2]);
|
|
}
|
|
}
|
|
*_used = used;
|
|
*_out_len = out_len;
|
|
}
|
|
|
|
|
|
void phydm_dynamic_tx_power(void *dm_void)
|
|
{
|
|
|
|
struct dm_struct *dm = (struct dm_struct *)dm_void;
|
|
struct cmn_sta_info *sta = NULL;
|
|
u8 i;
|
|
u8 cnt = 0;
|
|
u8 rssi_min = dm->rssi_min;
|
|
u8 rssi_tmp = 0;
|
|
|
|
if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
|
|
return;
|
|
|
|
PHYDM_DBG(dm, DBG_DYN_TXPWR,
|
|
"[%s] RSSI_min = %d, Noisy_dec = %d\n", __func__, rssi_min,
|
|
dm->noisy_decision);
|
|
phydm_noisy_enhance_hp_th(dm, dm->noisy_decision);
|
|
#ifndef BB_RAM_SUPPORT
|
|
/* Response Power */
|
|
dm->dynamic_tx_high_power_lvl = phydm_pwr_lvl_check(dm, rssi_min);
|
|
phydm_dynamic_response_power(dm);
|
|
#endif /* #ifndef BB_RAM_SUPPORT */
|
|
/* Per STA Tx power */
|
|
for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
|
|
phydm_dtp_per_sta(dm, i);
|
|
cnt++;
|
|
if (cnt >= dm->number_linked_client)
|
|
break;
|
|
}
|
|
}
|
|
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
|
|
|
void phydm_dynamic_tx_power_init_win(void *dm_void)
|
|
{
|
|
struct dm_struct *dm = (struct dm_struct *)dm_void;
|
|
void *adapter = dm->adapter;
|
|
PMGNT_INFO mgnt_info = &((PADAPTER)adapter)->MgntInfo;
|
|
HAL_DATA_TYPE *hal_data = GET_HAL_DATA((PADAPTER)adapter);
|
|
|
|
mgnt_info->bDynamicTxPowerEnable = false;
|
|
|
|
#if DEV_BUS_TYPE == RT_USB_INTERFACE
|
|
if (RT_GetInterfaceSelection((PADAPTER)adapter) ==
|
|
INTF_SEL1_USB_High_Power) {
|
|
mgnt_info->bDynamicTxPowerEnable = true;
|
|
}
|
|
#endif
|
|
|
|
hal_data->LastDTPLvl = tx_high_pwr_level_normal;
|
|
hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal;
|
|
|
|
PHYDM_DBG(dm, DBG_DYN_TXPWR, "[%s] DTP=%d\n", __func__,
|
|
mgnt_info->bDynamicTxPowerEnable);
|
|
}
|
|
|
|
void phydm_dynamic_tx_power_win(void *dm_void)
|
|
{
|
|
struct dm_struct *dm = (struct dm_struct *)dm_void;
|
|
|
|
if (!(dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
|
|
return;
|
|
|
|
#if (RTL8814A_SUPPORT == 1)
|
|
if (dm->support_ic_type == ODM_RTL8814A)
|
|
odm_dynamic_tx_power_8814a(dm);
|
|
#endif
|
|
|
|
#if (RTL8821A_SUPPORT == 1)
|
|
if (dm->support_ic_type & ODM_RTL8821) {
|
|
void *adapter = dm->adapter;
|
|
PMGNT_INFO mgnt_info = GetDefaultMgntInfo((PADAPTER)adapter);
|
|
|
|
if (mgnt_info->RegRspPwr == 1) {
|
|
if (dm->rssi_min > 60) {
|
|
/*Resp TXAGC offset = -3dB*/
|
|
odm_set_mac_reg(dm, 0x6d8, 0x1C0000, 1);
|
|
} else if (dm->rssi_min < 55) {
|
|
/*Resp TXAGC offset = 0dB*/
|
|
odm_set_mac_reg(dm, 0x6d8, 0x1C0000, 0);
|
|
}
|
|
}
|
|
}
|
|
#endif
|
|
}
|
|
#endif /*@#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
|
|
#endif /* @#ifdef CONFIG_DYNAMIC_TX_TWR */
|