mirror of
https://github.com/aircrack-ng/rtl8812au.git
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200 lines
5.2 KiB
C
200 lines
5.2 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __PHYDMSOML_H__
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#define __PHYDMSOML_H__
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/*@#define ADAPTIVE_SOML_VERSION "1.0" Byte counter version*/
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#define ADAPTIVE_SOML_VERSION "2.0" /*@add avg. phy rate decision 20180126*/
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#define PHYDM_ADAPTIVE_SOML_IC (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F)
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/*@jj add 20170822*/
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#define INIT_SOML_TIMMER 0
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#define CANCEL_SOML_TIMMER 1
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#define RELEASE_SOML_TIMMER 2
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#define SOML_RSSI_TH_HIGH 25
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#define SOML_RSSI_TH_LOW 20
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#define HT_RATE_IDX 16
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#define VHT_RATE_IDX 20
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#define HT_ORDER_TYPE 3
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#define VHT_ORDER_TYPE 4
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#define CRC_FAIL 1
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#define CRC_OK 0
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#if 0
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#define CFO_QPSK_TH 20
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#define CFO_QAM16_TH 20
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#define CFO_QAM64_TH 20
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#define CFO_QAM256_TH 20
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#define BPSK_QPSK_DIST 20
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#define QAM16_DIST 30
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#define QAM64_DIST 30
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#define QAM256_DIST 20
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#endif
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#define HT_TYPE 1
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#define VHT_TYPE 2
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#define SOML_ON 1
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#define SOML_OFF 0
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#ifdef CONFIG_ADAPTIVE_SOML
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struct adaptive_soml {
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u32 rvrt_val; /*all rvrt_val for pause API must set to u32*/
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boolean is_soml_method_enable;
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boolean get_stats;
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u8 soml_on_off;
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u8 soml_state_cnt;
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u8 soml_delay_time;
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u8 soml_intvl;
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u8 soml_train_num;
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u8 soml_counter;
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u8 soml_period;
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u8 soml_select;
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u8 soml_last_state;
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u8 cfo_qpsk_th;
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u8 cfo_qam16_th;
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u8 cfo_qam64_th;
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u8 cfo_qam256_th;
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u8 bpsk_qpsk_dist_th;
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u8 qam16_dist_th;
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u8 qam64_dist_th;
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u8 qam256_dist_th;
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u8 cfo_cnt;
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s32 cfo_diff_a;
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s32 cfo_diff_b;
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s32 cfo_diff_sum_a;
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s32 cfo_diff_sum_b;
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s32 cfo_diff_avg_a;
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s32 cfo_diff_avg_b;
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u16 ht_cnt[HT_RATE_IDX];
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u16 pre_ht_cnt[HT_RATE_IDX];
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u16 ht_cnt_on[HT_RATE_IDX];
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u16 ht_cnt_off[HT_RATE_IDX];
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u16 ht_crc_ok_cnt_on[HT_RATE_IDX];
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u16 ht_crc_fail_cnt_on[HT_RATE_IDX];
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u16 ht_crc_ok_cnt_off[HT_RATE_IDX];
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u16 ht_crc_fail_cnt_off[HT_RATE_IDX];
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u16 vht_crc_ok_cnt_on[VHT_RATE_IDX];
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u16 vht_crc_fail_cnt_on[VHT_RATE_IDX];
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u16 vht_crc_ok_cnt_off[VHT_RATE_IDX];
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u16 vht_crc_fail_cnt_off[VHT_RATE_IDX];
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u16 vht_cnt[VHT_RATE_IDX];
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u16 pre_vht_cnt[VHT_RATE_IDX];
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u16 vht_cnt_on[VHT_RATE_IDX];
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u16 vht_cnt_off[VHT_RATE_IDX];
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u16 num_ht_qam[HT_ORDER_TYPE];
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u16 ht_byte[HT_RATE_IDX];
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u16 pre_ht_byte[HT_RATE_IDX];
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u16 ht_byte_on[HT_RATE_IDX];
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u16 ht_byte_off[HT_RATE_IDX];
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u16 num_vht_qam[VHT_ORDER_TYPE];
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u16 vht_byte[VHT_RATE_IDX];
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u16 pre_vht_byte[VHT_RATE_IDX];
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u16 vht_byte_on[VHT_RATE_IDX];
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u16 vht_byte_off[VHT_RATE_IDX];
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#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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#if USE_WORKITEM
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RT_WORK_ITEM phydm_adaptive_soml_workitem;
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#endif
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#endif
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struct phydm_timer_list phydm_adaptive_soml_timer;
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};
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enum qam_order {
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BPSK_QPSK = 0,
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QAM16 = 1,
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QAM64 = 2,
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QAM256 = 3
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};
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void phydm_dynamicsoftmletting(void *dm_void);
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void phydm_soml_on_off(void *dm_void, u8 swch);
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#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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void phydm_adaptive_soml_callback(struct phydm_timer_list *timer);
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void phydm_adaptive_soml_workitem_callback(void *context);
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#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
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void phydm_adaptive_soml_callback(void *dm_void);
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void phydm_adaptive_soml_workitem_callback(void *context);
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#else
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void phydm_adaptive_soml_callback(void *dm_void);
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#endif
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void phydm_rx_rate_for_soml(void *dm_void, void *pkt_info_void);
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void phydm_rx_qam_for_soml(void *dm_void, void *pkt_info_void);
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void phydm_soml_reset_rx_rate(void *dm_void);
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void phydm_soml_reset_qam(void *dm_void);
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void phydm_soml_cfo_process(void *dm_void, s32 *diff_a, s32 *diff_b);
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void phydm_soml_debug(void *dm_void, char input[][16], u32 *_used,
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char *output, u32 *_out_len);
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void phydm_soml_statistics(void *dm_void, u8 on_off_state);
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void phydm_adsl(void *dm_void);
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void phydm_adaptive_soml_reset(void *dm_void);
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void phydm_set_adsl_val(void *dm_void, u32 *val_buf, u8 val_len);
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void phydm_soml_crc_acq(void *dm_void, u8 rate_id, boolean crc32, u32 length);
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void phydm_soml_bytes_acq(void *dm_void, u8 rate_id, u32 length);
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void phydm_adaptive_soml_timers(void *dm_void, u8 state);
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void phydm_adaptive_soml_init(void *dm_void);
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void phydm_adaptive_soml(void *dm_void);
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void phydm_enable_adaptive_soml(void *dm_void);
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void phydm_stop_adaptive_soml(void *dm_void);
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void phydm_adaptive_soml_para_set(void *dm_void, u8 train_num, u8 intvl,
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u8 period, u8 delay_time);
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#endif
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void phydm_init_soft_ml_setting(void *dm_void);
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#endif /*@#ifndef __PHYDMSOML_H__*/
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