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Fix some compiler errors

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This commit is contained in:
kimocoder 2020-03-08 19:53:37 +01:00
parent 19398a4630
commit 5484970659
2 changed files with 28 additions and 34 deletions
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18
hal/phydm/rtl8814a/halhwimg8814a_bb.c
View File

@ -114,7 +114,7 @@ CheckNegative(
* AGC_TAB.TXT
******************************************************************************/
u32 Array_MP_8814A_AGC_TAB[] = {
u32 Array_MP_8814A_AGC_TAB[] = {
0x80000001, 0x00000055, 0x40000000, 0x00000000,
0x81C, 0xFE000003,
0x81C, 0xFF000003,
@ -1562,7 +1562,7 @@ ODM_GetVersion_MP_8814A_AGC_TAB(void)
* PHY_REG.TXT
******************************************************************************/
u32 Array_MP_8814A_PHY_REG[] = {
u32 Array_MP_8814A_PHY_REG[] = {
0x800, 0x9020D010,
0x804, 0x08011280,
0x808, 0x0E0282FF,
@ -3699,7 +3699,7 @@ ODM_GetVersion_MP_8814A_PHY_REG(void)
* PHY_REG_MP.TXT
******************************************************************************/
u32 Array_MP_8814A_PHY_REG_MP[] = {
u32 Array_MP_8814A_PHY_REG_MP[] = {
0x8FC, 0x00000000,
0x838, 0x86667641,
@ -3769,7 +3769,7 @@ ODM_GetVersion_MP_8814A_PHY_REG_MP(void)
* PHY_REG_PG.TXT
******************************************************************************/
u32 Array_MP_8814A_PHY_REG_PG[] = {
u32 Array_MP_8814A_PHY_REG_PG[] = {
0, 0, 0, 0x00000c20, 0xffffffff, 0x34363840,
0, 0, 0, 0x00000c24, 0xffffffff, 0x42424444,
0, 0, 0, 0x00000c28, 0xffffffff, 0x30323638,
@ -3947,8 +3947,8 @@ odm_read_and_config_mp_8814a_phy_reg_pg(
/******************************************************************************
* PHY_REG_PG_Type2.TXT
******************************************************************************/
/*
******************************************************************************\
u32 Array_MP_8814A_PHY_REG_PG_Type2[] = {
0, 0, 0, 0x00000c20, 0xffffffff, 0x36363636,
0, 0, 0, 0x00000c24, 0xffffffff, 0x36363636,
@ -4124,12 +4124,10 @@ _odm_read_and_config_mp_8814a_phy_reg_pg_type2(
}
/******************************************************************************
******************************************************************************
* PHY_REG_PG_Type3.TXT
******************************************************************************/
******************************************************************************
/*
u32 Array_MP_8814A_PHY_REG_PG_Type3[] = {
0, 0, 0, 0x00000c20, 0xffffffff, 0x48484848,
0, 0, 0, 0x00000c24, 0xffffffff, 0x46464646,

44
hal/phydm/rtl8814a/halhwimg8814a_rf.c
View File

@ -53,20 +53,20 @@ u4Byte driver3 = 0;
(pDM_Odm->type_alna & 0xFF00) << 8 |
(pDM_Odm->type_apa & 0xFF00) << 16;
PHYDM_DBG(pDM_Odm, ODM_COMP_INIT,
PHYDM_DBG(pDM_Odm, ODM_COMP_INIT,
"===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4);
PHYDM_DBG(pDM_Odm, ODM_COMP_INIT,
PHYDM_DBG(pDM_Odm, ODM_COMP_INIT,
"===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4);
PHYDM_DBG(pDM_Odm, ODM_COMP_INIT,
PHYDM_DBG(pDM_Odm, ODM_COMP_INIT,
" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->support_platform, pDM_Odm->support_interface);
PHYDM_DBG(pDM_Odm, ODM_COMP_INIT,
PHYDM_DBG(pDM_Odm, ODM_COMP_INIT,
" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->board_type, pDM_Odm->package_type);
/*============== Value Defined Check ===============*/
/*QFN Type [15:12] and Cut Version [27:24] need to do value check*/
if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000)))
return FALSE;
if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000)))
@ -75,8 +75,8 @@ u4Byte driver3 = 0;
/*=============== Bit Defined Check ================*/
/* We don't care [31:28] */
cond1 &= 0x00FF0FFF;
driver1 &= 0x00FF0FFF;
cond1 &= 0x00FF0FFF;
driver1 &= 0x00FF0FFF;
if ((cond1 & driver1) == cond1) {
u4Byte bitMask = 0;
@ -114,7 +114,7 @@ CheckNegative(
* RadioA.TXT
******************************************************************************/
u4Byte Array_MP_8814A_RadioA[] = {
u4Byte Array_MP_8814A_RadioA[] = {
0x018, 0x00013124,
0x040, 0x00000C00,
0x058, 0x00000F98,
@ -1249,7 +1249,7 @@ ODM_GetVersion_MP_8814A_RadioA(void)
* RadioB.TXT
******************************************************************************/
u4Byte Array_MP_8814A_RadioB[] = {
u4Byte Array_MP_8814A_RadioB[] = {
0x018, 0x00013124,
0x040, 0x00000C00,
0x058, 0x00000F98,
@ -2292,7 +2292,7 @@ ODM_GetVersion_MP_8814A_RadioB(void)
* RadioC.TXT
******************************************************************************/
u4Byte Array_MP_8814A_RadioC[] = {
u4Byte Array_MP_8814A_RadioC[] = {
0x018, 0x00013124,
0x040, 0x00000C00,
0x058, 0x00000F98,
@ -3338,7 +3338,7 @@ ODM_GetVersion_MP_8814A_RadioC(void)
* RadioD.TXT
******************************************************************************/
u4Byte Array_MP_8814A_RadioD[] = {
u4Byte Array_MP_8814A_RadioD[] = {
0x018, 0x00013124,
0x040, 0x00000C00,
0x058, 0x00000F98,
@ -4332,7 +4332,7 @@ odm_read_and_config_mp_8814a_radiod(
BOOLEAN bMatched = TRUE, bSkipped = FALSE;
u4Byte ArrayLen = sizeof(Array_MP_8814A_RadioD)/sizeof(u4Byte);
pu4Byte Array = Array_MP_8814A_RadioD;
u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
PHYDM_DBG(pDM_Odm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_8814A_RadioD\n");
@ -4782,7 +4782,7 @@ odm_read_and_config_mp_8814a_txpowertrack_type5(
* TXPWR_LMT.TXT
******************************************************************************/
const char *Array_MP_8814A_TXPWR_LMT[] = {
const char *Array_MP_8814A_TXPWR_LMT[] = {
"FCC", "2.4G", "20M", "CCK", "1T", "01", "36",
"ETSI", "2.4G", "20M", "CCK", "1T", "01", "32",
"MKK", "2.4G", "20M", "CCK", "1T", "01", "32",
@ -5784,7 +5784,7 @@ odm_read_and_config_mp_8814a_txpwr_lmt(
pu1Byte rfPath = Array[i+4];
pu1Byte chnl = Array[i+5];
pu1Byte val = Array[i+6];
odm_ConfigBB_TXPWR_LMT_8814A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",",
@ -6801,7 +6801,7 @@ _odm_read_and_config_mp_8814a_txpwr_lmt_type2(
pu1Byte rfPath = Array[i+4];
pu1Byte chnl = Array[i+5];
pu1Byte val = Array[i+6];
odm_ConfigBB_TXPWR_LMT_8814A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",",
@ -6811,11 +6811,10 @@ _odm_read_and_config_mp_8814a_txpwr_lmt_type2(
}
/******************************************************************************
******************************************************************************
* TXPWR_LMT_Type3.TXT
******************************************************************************/
******************************************************************************
/*
const char *Array_MP_8814A_TXPWR_LMT_Type3[] = {
"FCC", "2.4G", "20M", "CCK", "1T", "01", "46",
"ETSI", "2.4G", "20M", "CCK", "1T", "01", "40",
@ -7791,7 +7790,6 @@ const char *Array_MP_8814A_TXPWR_LMT_Type3[] = {
"MKK", "5G", "80M", "VHT", "4T", "155", "63"
};
/*
void
_odm_read_and_config_mp_8814a_txpwr_lmt_type3(
struct dm_struct * pDM_Odm
@ -7818,11 +7816,10 @@ _odm_read_and_config_mp_8814a_txpwr_lmt_type3(
}
/******************************************************************************
******************************************************************************
* TXPWR_LMT_Type5.TXT
******************************************************************************/
******************************************************************************
/*
const char *Array_MP_8814A_TXPWR_LMT_Type5[] = {
"FCC", "2.4G", "20M", "CCK", "1T", "01", "46",
"ETSI", "2.4G", "20M", "CCK", "1T", "01", "40",
@ -8796,10 +8793,9 @@ const char *Array_MP_8814A_TXPWR_LMT_Type5[] = {
"FCC", "5G", "80M", "VHT", "4T", "155", "46",
"ETSI", "5G", "80M", "VHT", "4T", "155", "40",
"MKK", "5G", "80M", "VHT", "4T", "155", "63"
//};
};
/*
void
_odm_read_and_config_mp_8814a_txpwr_lmt_type5(
struct dm_struct * pDM_Odm