2016-03-27 17:56:02 +00:00
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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2017-04-07 11:39:45 +00:00
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*
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2016-03-27 17:56:02 +00:00
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*
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******************************************************************************/
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2017-04-07 11:39:45 +00:00
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#ifndef __RTW_RF_H_
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2016-03-27 17:56:02 +00:00
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#define __RTW_RF_H_
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#define OFDM_PHY 1
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#define MIXED_PHY 2
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#define CCK_PHY 3
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#define NumRates (13)
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2017-04-07 11:39:45 +00:00
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/* slot time for 11g */
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2016-03-27 17:56:02 +00:00
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#define SHORT_SLOT_TIME 9
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#define NON_SHORT_SLOT_TIME 20
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#define RTL8711_RF_MAX_SENS 6
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#define RTL8711_RF_DEF_SENS 4
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2017-04-07 11:39:45 +00:00
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/*
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* We now define the following channels as the max channels in each channel plan.
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* 2G, total 14 chnls
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* {1,2,3,4,5,6,7,8,9,10,11,12,13,14}
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* 5G, total 24 chnls
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* {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165} */
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2016-03-27 17:56:02 +00:00
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#define MAX_CHANNEL_NUM_2G 14
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#define MAX_CHANNEL_NUM_5G 24
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2017-04-07 11:39:45 +00:00
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#define MAX_CHANNEL_NUM 38/* 14+24 */
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2016-03-27 17:56:02 +00:00
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2017-04-07 11:39:45 +00:00
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#define CENTER_CH_2G_40M_NUM 9
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2016-03-27 17:56:02 +00:00
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#define CENTER_CH_2G_NUM 14
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#define CENTER_CH_5G_20M_NUM 28 /* 20M center channels */
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#define CENTER_CH_5G_40M_NUM 14 /* 40M center channels */
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#define CENTER_CH_5G_80M_NUM 7 /* 80M center channels */
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2017-04-07 11:39:45 +00:00
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#define CENTER_CH_5G_160M_NUM 3 /* 160M center channels */
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2016-03-27 17:56:02 +00:00
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#define CENTER_CH_5G_ALL_NUM (CENTER_CH_5G_20M_NUM + CENTER_CH_5G_40M_NUM + CENTER_CH_5G_80M_NUM)
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2017-04-07 11:39:45 +00:00
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extern u8 center_ch_2g[CENTER_CH_2G_NUM];
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extern u8 center_ch_2g_40m[CENTER_CH_2G_40M_NUM];
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u8 center_chs_2g_num(u8 bw);
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u8 center_chs_2g(u8 bw, u8 id);
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2016-03-27 17:56:02 +00:00
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extern u8 center_ch_5g_20m[CENTER_CH_5G_20M_NUM];
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extern u8 center_ch_5g_40m[CENTER_CH_5G_40M_NUM];
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2017-04-07 11:39:45 +00:00
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extern u8 center_ch_5g_20m_40m[CENTER_CH_5G_20M_NUM + CENTER_CH_5G_40M_NUM];
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2016-03-27 17:56:02 +00:00
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extern u8 center_ch_5g_80m[CENTER_CH_5G_80M_NUM];
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extern u8 center_ch_5g_all[CENTER_CH_5G_ALL_NUM];
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u8 center_chs_5g_num(u8 bw);
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u8 center_chs_5g(u8 bw, u8 id);
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2017-04-07 11:39:45 +00:00
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u8 rtw_get_scch_by_cch_offset(u8 cch, u8 bw, u8 offset);
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u8 rtw_get_op_chs_by_cch_bw(u8 cch, u8 bw, u8 **op_chs, u8 *op_ch_num);
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u8 rtw_get_ch_group(u8 ch, u8 *group, u8 *cck_group);
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/* #define NUM_REGULATORYS 21 */
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2016-03-27 17:56:02 +00:00
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#define NUM_REGULATORYS 1
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2017-04-07 11:39:45 +00:00
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/* Country codes */
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2016-03-27 17:56:02 +00:00
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#define USA 0x555320
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2017-04-07 11:39:45 +00:00
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#define EUROPE 0x1 /* temp, should be provided later */
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#define JAPAN 0x2 /* temp, should be provided later */
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2016-03-27 17:56:02 +00:00
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struct regulatory_class {
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2017-04-07 11:39:45 +00:00
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u32 starting_freq; /* MHz, */
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2016-03-27 17:56:02 +00:00
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u8 channel_set[MAX_CHANNEL_NUM];
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2017-04-07 11:39:45 +00:00
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u8 channel_cck_power[MAX_CHANNEL_NUM];/* dbm */
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u8 channel_ofdm_power[MAX_CHANNEL_NUM];/* dbm */
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u8 txpower_limit; /* dbm */
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u8 channel_spacing; /* MHz */
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2016-03-27 17:56:02 +00:00
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u8 modem;
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};
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2017-04-07 11:39:45 +00:00
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typedef enum _CAPABILITY {
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2016-03-27 17:56:02 +00:00
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cESS = 0x0001,
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cIBSS = 0x0002,
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cPollable = 0x0004,
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cPollReq = 0x0008,
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cPrivacy = 0x0010,
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cShortPreamble = 0x0020,
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cPBCC = 0x0040,
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cChannelAgility = 0x0080,
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cSpectrumMgnt = 0x0100,
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2017-04-07 11:39:45 +00:00
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cQos = 0x0200, /* For HCCA, use with CF-Pollable and CF-PollReq */
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2016-03-27 17:56:02 +00:00
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cShortSlotTime = 0x0400,
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cAPSD = 0x0800,
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2017-04-07 11:39:45 +00:00
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cRM = 0x1000, /* RRM (Radio Request Measurement) */
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2016-03-27 17:56:02 +00:00
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cDSSS_OFDM = 0x2000,
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cDelayedBA = 0x4000,
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cImmediateBA = 0x8000,
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2017-04-07 11:39:45 +00:00
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} CAPABILITY, *PCAPABILITY;
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2016-03-27 17:56:02 +00:00
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2017-04-07 11:39:45 +00:00
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enum _REG_PREAMBLE_MODE {
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2016-03-27 17:56:02 +00:00
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PREAMBLE_LONG = 1,
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PREAMBLE_AUTO = 2,
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PREAMBLE_SHORT = 3,
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};
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2017-04-07 11:39:45 +00:00
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enum _RTL8712_RF_MIMO_CONFIG_ {
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RTL8712_RFCONFIG_1T = 0x10,
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RTL8712_RFCONFIG_2T = 0x20,
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RTL8712_RFCONFIG_1R = 0x01,
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RTL8712_RFCONFIG_2R = 0x02,
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RTL8712_RFCONFIG_1T1R = 0x11,
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RTL8712_RFCONFIG_1T2R = 0x12,
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RTL8712_RFCONFIG_TURBO = 0x92,
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RTL8712_RFCONFIG_2T2R = 0x22
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2016-03-27 17:56:02 +00:00
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};
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typedef enum _RF_PATH {
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RF_PATH_A = 0,
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RF_PATH_B = 1,
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RF_PATH_C = 2,
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RF_PATH_D = 3,
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} RF_PATH, *PRF_PATH;
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#define rf_path_char(path) (((path) >= RF_PATH_MAX) ? 'X' : 'A' + (path))
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2017-04-07 11:39:45 +00:00
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/* Bandwidth Offset */
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2016-03-27 17:56:02 +00:00
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#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
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#define HAL_PRIME_CHNL_OFFSET_LOWER 1
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#define HAL_PRIME_CHNL_OFFSET_UPPER 2
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typedef enum _BAND_TYPE {
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BAND_ON_2_4G = 0,
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BAND_ON_5G = 1,
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BAND_ON_BOTH = 2,
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BAND_MAX = 3,
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} BAND_TYPE, *PBAND_TYPE;
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2017-04-07 11:39:45 +00:00
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extern const char *const _band_str[];
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2016-03-27 17:56:02 +00:00
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#define band_str(band) (((band) >= BAND_MAX) ? _band_str[BAND_MAX] : _band_str[(band)])
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extern const u8 _band_to_band_cap[];
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#define band_to_band_cap(band) (((band) >= BAND_MAX) ? _band_to_band_cap[BAND_MAX] : _band_to_band_cap[(band)])
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2017-04-07 11:39:45 +00:00
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/* Represent Channel Width in HT Capabilities
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* */
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typedef enum _CHANNEL_WIDTH {
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2016-03-27 17:56:02 +00:00
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CHANNEL_WIDTH_20 = 0,
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CHANNEL_WIDTH_40 = 1,
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CHANNEL_WIDTH_80 = 2,
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CHANNEL_WIDTH_160 = 3,
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CHANNEL_WIDTH_80_80 = 4,
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CHANNEL_WIDTH_MAX = 5,
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2017-04-07 11:39:45 +00:00
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} CHANNEL_WIDTH, *PCHANNEL_WIDTH;
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2016-03-27 17:56:02 +00:00
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2017-04-07 11:39:45 +00:00
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extern const char *const _ch_width_str[];
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2016-03-27 17:56:02 +00:00
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#define ch_width_str(bw) (((bw) >= CHANNEL_WIDTH_MAX) ? _ch_width_str[CHANNEL_WIDTH_MAX] : _ch_width_str[(bw)])
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extern const u8 _ch_width_to_bw_cap[];
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#define ch_width_to_bw_cap(bw) (((bw) >= CHANNEL_WIDTH_MAX) ? _ch_width_to_bw_cap[CHANNEL_WIDTH_MAX] : _ch_width_to_bw_cap[(bw)])
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2017-04-07 11:39:45 +00:00
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/*
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* Represent Extention Channel Offset in HT Capabilities
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* This is available only in 40Mhz mode.
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* */
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typedef enum _EXTCHNL_OFFSET {
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2016-03-27 17:56:02 +00:00
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EXTCHNL_OFFSET_NO_EXT = 0,
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EXTCHNL_OFFSET_UPPER = 1,
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EXTCHNL_OFFSET_NO_DEF = 2,
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EXTCHNL_OFFSET_LOWER = 3,
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2017-04-07 11:39:45 +00:00
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} EXTCHNL_OFFSET, *PEXTCHNL_OFFSET;
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2016-03-27 17:56:02 +00:00
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2017-04-07 11:39:45 +00:00
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typedef enum _VHT_DATA_SC {
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2016-03-27 17:56:02 +00:00
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VHT_DATA_SC_DONOT_CARE = 0,
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VHT_DATA_SC_20_UPPER_OF_80MHZ = 1,
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VHT_DATA_SC_20_LOWER_OF_80MHZ = 2,
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VHT_DATA_SC_20_UPPERST_OF_80MHZ = 3,
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VHT_DATA_SC_20_LOWEST_OF_80MHZ = 4,
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VHT_DATA_SC_20_RECV1 = 5,
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VHT_DATA_SC_20_RECV2 = 6,
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VHT_DATA_SC_20_RECV3 = 7,
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VHT_DATA_SC_20_RECV4 = 8,
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VHT_DATA_SC_40_UPPER_OF_80MHZ = 9,
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VHT_DATA_SC_40_LOWER_OF_80MHZ = 10,
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2017-04-07 11:39:45 +00:00
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} VHT_DATA_SC, *PVHT_DATA_SC_E;
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2016-03-27 17:56:02 +00:00
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2017-04-07 11:39:45 +00:00
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typedef enum _PROTECTION_MODE {
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2016-03-27 17:56:02 +00:00
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PROTECTION_MODE_AUTO = 0,
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PROTECTION_MODE_FORCE_ENABLE = 1,
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PROTECTION_MODE_FORCE_DISABLE = 2,
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2017-04-07 11:39:45 +00:00
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} PROTECTION_MODE, *PPROTECTION_MODE;
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2016-03-27 17:56:02 +00:00
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2017-10-24 14:33:57 +00:00
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enum rt_rf_types {
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2016-03-27 17:56:02 +00:00
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RF_1T2R = 0,
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RF_2T4R = 1,
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RF_2T2R = 2,
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RF_1T1R = 3,
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RF_2T2R_GREEN = 4,
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RF_2T3R = 5,
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2016-03-27 17:56:02 +00:00
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RF_3T3R = 6,
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RF_3T4R = 7,
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RF_4T4R = 8,
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RF_MAX_TYPE = 0xF, /* u1Byte */
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2017-10-24 14:33:57 +00:00
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};
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2016-03-27 17:56:02 +00:00
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int rtw_ch2freq(int chan);
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int rtw_freq2ch(int freq);
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bool rtw_chbw_to_freq_range(u8 ch, u8 bw, u8 offset, u32 *hi, u32 *lo);
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2017-04-07 11:39:45 +00:00
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#define RTW_MODULE_RTL8821AE_HMC_M2 BIT0 /* RTL8821AE(HMC + M.2) */
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#define RTW_MODULE_RTL8821AU BIT1 /* RTL8821AU */
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#define RTW_MODULE_RTL8812AENF_NGFF BIT2 /* RTL8812AENF(8812AE+8761)_NGFF */
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#define RTW_MODULE_RTL8812AEBT_HMC BIT3 /* RTL8812AEBT(8812AE+8761)_HMC */
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#define RTW_MODULE_RTL8188EE_HMC_M2 BIT4 /* RTL8188EE(HMC + M.2) */
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#define RTW_MODULE_RTL8723BE_HMC_M2 BIT5 /* RTL8723BE(HMC + M.2) */
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#define RTW_MODULE_RTL8723BS_NGFF1216 BIT6 /* RTL8723BS(NGFF1216) */
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#define RTW_MODULE_RTL8192EEBT_HMC_M2 BIT7 /* RTL8192EEBT(8192EE+8761AU)_(HMC + M.2) */
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#define IS_ALPHA2_NO_SPECIFIED(_alpha2) ((*((u16 *)(_alpha2))) == 0xFFFF)
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struct country_chplan {
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char alpha2[2];
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u8 chplan;
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#ifdef CONFIG_80211AC_VHT
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u8 en_11ac;
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#endif
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#if RTW_DEF_MODULE_REGULATORY_CERT
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u8 def_module_flags; /* RTW_MODULE_RTLXXX */
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#endif
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};
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#ifdef CONFIG_80211AC_VHT
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#define COUNTRY_CHPLAN_EN_11AC(_ent) ((_ent)->en_11ac)
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#else
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#define COUNTRY_CHPLAN_EN_11AC(_ent) 0
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#endif
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#if RTW_DEF_MODULE_REGULATORY_CERT
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#define COUNTRY_CHPLAN_DEF_MODULE_FALGS(_ent) ((_ent)->def_module_flags)
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#else
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#define COUNTRY_CHPLAN_DEF_MODULE_FALGS(_ent) 0
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#endif
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const struct country_chplan *rtw_get_chplan_from_country(const char *country_code);
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2016-03-27 17:56:02 +00:00
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#define BB_GAIN_2G 0
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#ifdef CONFIG_IEEE80211_BAND_5GHZ
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#define BB_GAIN_5GLB1 1
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#define BB_GAIN_5GLB2 2
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#define BB_GAIN_5GMB1 3
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#define BB_GAIN_5GMB2 4
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#define BB_GAIN_5GHB 5
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#endif
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#ifdef CONFIG_IEEE80211_BAND_5GHZ
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#define BB_GAIN_NUM 6
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#else
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#define BB_GAIN_NUM 1
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#endif
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int rtw_ch_to_bb_gain_sel(int ch);
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void rtw_rf_set_tx_gain_offset(_adapter *adapter, u8 path, s8 offset);
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void rtw_rf_apply_tx_gain_offset(_adapter *adapter, u8 ch);
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bool rtw_is_dfs_range(u32 hi, u32 lo);
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bool rtw_is_dfs_ch(u8 ch, u8 bw, u8 offset);
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2017-04-07 11:39:45 +00:00
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bool rtw_is_long_cac_range(u32 hi, u32 lo, u8 dfs_region);
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bool rtw_is_long_cac_ch(u8 ch, u8 bw, u8 offset, u8 dfs_region);
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2016-03-27 17:56:02 +00:00
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2017-04-07 11:39:45 +00:00
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#endif /* _RTL8711_RF_H_ */
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