1
0
mirror of https://github.com/aircrack-ng/rtl8812au.git synced 2024-11-14 18:05:36 +00:00
rtl8812au/hal/phydm/rtl8821a/phydm_regconfig8821a.c

207 lines
4.7 KiB
C
Raw Normal View History

2018-07-03 14:50:43 +00:00
/******************************************************************************
*
2018-08-24 20:52:34 +00:00
* Copyright(c) 2007 - 2017 Realtek Corporation.
2018-07-03 14:50:43 +00:00
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
2018-08-24 20:52:34 +00:00
*****************************************************************************/
2018-07-03 14:50:43 +00:00
#include "mp_precomp.h"
#include "../phydm_precomp.h"
2018-08-24 20:52:34 +00:00
#if (RTL8821A_SUPPORT == 1)
2018-07-03 14:50:43 +00:00
2018-08-24 20:52:34 +00:00
void
odm_config_rf_reg_8821a(
struct dm_struct *dm,
2018-07-03 14:50:43 +00:00
u32 addr,
u32 data,
enum rf_path RF_PATH,
u32 reg_addr
)
{
if (addr == 0xfe || addr == 0xffe) {
#ifdef CONFIG_LONG_DELAY_ISSUE
ODM_sleep_ms(50);
#else
ODM_delay_ms(50);
#endif
2018-08-24 20:52:34 +00:00
} else if (addr == 0xfd)
2018-07-03 14:50:43 +00:00
ODM_delay_ms(5);
else if (addr == 0xfc)
ODM_delay_ms(1);
else if (addr == 0xfb)
ODM_delay_us(50);
else if (addr == 0xfa)
ODM_delay_us(5);
else if (addr == 0xf9)
ODM_delay_us(1);
2018-08-24 20:52:34 +00:00
else {
odm_set_rf_reg(dm, RF_PATH, reg_addr, RFREGOFFSETMASK, data);
/* Add 1us delay between BB/RF register setting. */
2018-07-03 14:50:43 +00:00
ODM_delay_us(1);
2018-08-24 20:52:34 +00:00
}
2018-07-03 14:50:43 +00:00
}
void
odm_config_rf_radio_a_8821a(
2018-08-24 20:52:34 +00:00
struct dm_struct *dm,
2018-07-03 14:50:43 +00:00
u32 addr,
u32 data
)
{
u32 content = 0x1000; /* RF_Content: radioa_txt */
u32 maskfor_phy_set = (u32)(content & 0xE000);
2018-08-24 20:52:34 +00:00
odm_config_rf_reg_8821a(dm, addr, data, RF_PATH_A, addr | maskfor_phy_set);
2018-07-03 14:50:43 +00:00
2018-08-24 20:52:34 +00:00
PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_config_rf_with_header_file: [RadioA] %08X %08X\n", addr, data);
2018-07-03 14:50:43 +00:00
}
2018-08-24 20:52:34 +00:00
/* 8821 no RF B */
#if 0
2018-07-03 14:50:43 +00:00
void
odm_config_rf_radio_b_8821a(
2018-08-24 20:52:34 +00:00
struct dm_struct *dm,
2018-07-03 14:50:43 +00:00
u32 addr,
u32 data
)
{
2018-08-24 20:52:34 +00:00
u32 content = 0x1001; /* RF_Content: radiob_txt */
2018-07-03 14:50:43 +00:00
u32 maskfor_phy_set = (u32)(content & 0xE000);
2018-08-24 20:52:34 +00:00
odm_config_rf_reg_8812a(dm, addr, data, RF_PATH_B, addr | maskfor_phy_set);
2018-07-03 14:50:43 +00:00
2018-08-24 20:52:34 +00:00
PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_config_rf_with_header_file: [RadioB] %08X %08X\n", addr, data);
2018-07-03 14:50:43 +00:00
}
2018-08-24 20:52:34 +00:00
#endif
2018-07-03 14:50:43 +00:00
void
odm_config_mac_8821a(
2018-08-24 20:52:34 +00:00
struct dm_struct *dm,
2018-07-03 14:50:43 +00:00
u32 addr,
u8 data
)
{
2018-08-24 20:52:34 +00:00
odm_write_1byte(dm, addr, data);
PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_config_mac_with_header_file: [MAC_REG] %08X %08X\n", addr, data);
2018-07-03 14:50:43 +00:00
}
void
odm_config_bb_agc_8821a(
2018-08-24 20:52:34 +00:00
struct dm_struct *dm,
2018-07-03 14:50:43 +00:00
u32 addr,
u32 bitmask,
u32 data
)
{
2018-08-24 20:52:34 +00:00
odm_set_bb_reg(dm, addr, bitmask, data);
2018-07-03 14:50:43 +00:00
/* Add 1us delay between BB/RF register setting. */
ODM_delay_us(1);
2018-08-24 20:52:34 +00:00
PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_config_bb_with_header_file: [AGC_TAB] %08X %08X\n", addr, data);
2018-07-03 14:50:43 +00:00
}
void
odm_config_bb_phy_reg_pg_8821a(
2018-08-24 20:52:34 +00:00
struct dm_struct *dm,
2018-07-03 14:50:43 +00:00
u32 band,
u32 rf_path,
u32 tx_num,
u32 addr,
u32 bitmask,
u32 data
)
{
2018-08-24 20:52:34 +00:00
if (addr == 0xfe)
2018-07-03 14:50:43 +00:00
#ifdef CONFIG_LONG_DELAY_ISSUE
ODM_sleep_ms(50);
#else
ODM_delay_ms(50);
#endif
else if (addr == 0xfd)
ODM_delay_ms(5);
else if (addr == 0xfc)
ODM_delay_ms(1);
else if (addr == 0xfb)
ODM_delay_us(50);
else if (addr == 0xfa)
ODM_delay_us(5);
else if (addr == 0xf9)
ODM_delay_us(1);
2018-08-24 20:52:34 +00:00
PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_config_bb_with_header_file: [PHY_REG] %08X %08X %08X\n", addr, bitmask, data);
2018-07-03 14:50:43 +00:00
2018-08-24 20:52:34 +00:00
#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
phy_store_tx_power_by_rate(dm->adapter, band, rf_path, tx_num, addr, bitmask, data);
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
PHY_StoreTxPowerByRate((PADAPTER)dm->adapter, band, rf_path, tx_num, addr, bitmask, data);
2018-07-03 14:50:43 +00:00
#endif
}
void
odm_config_bb_phy_8821a(
2018-08-24 20:52:34 +00:00
struct dm_struct *dm,
2018-07-03 14:50:43 +00:00
u32 addr,
u32 bitmask,
u32 data
)
{
if (addr == 0xfe)
#ifdef CONFIG_LONG_DELAY_ISSUE
ODM_sleep_ms(50);
#else
ODM_delay_ms(50);
#endif
else if (addr == 0xfd)
ODM_delay_ms(5);
else if (addr == 0xfc)
ODM_delay_ms(1);
else if (addr == 0xfb)
ODM_delay_us(50);
else if (addr == 0xfa)
ODM_delay_us(5);
else if (addr == 0xf9)
ODM_delay_us(1);
else if (addr == 0xa24)
2018-08-24 20:52:34 +00:00
dm->rf_calibrate_info.rega24 = data;
odm_set_bb_reg(dm, addr, bitmask, data);
/* Add 1us delay between BB/RF register setting. */
2018-07-03 14:50:43 +00:00
ODM_delay_us(1);
2018-08-24 20:52:34 +00:00
PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_config_bb_with_header_file: [PHY_REG] %08X %08X\n", addr, data);
2018-07-03 14:50:43 +00:00
}
void
odm_config_bb_txpwr_lmt_8821a(
2018-08-24 20:52:34 +00:00
struct dm_struct *dm,
2018-07-03 14:50:43 +00:00
u8 *regulation,
u8 *band,
u8 *bandwidth,
u8 *rate_section,
u8 *rf_path,
u8 *channel,
u8 *power_limit
)
{
2018-08-24 20:52:34 +00:00
#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
phy_set_tx_power_limit(dm, regulation, band,
bandwidth, rate_section, rf_path, channel, power_limit);
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
PHY_SetTxPowerLimit(dm, regulation, band,
bandwidth, rate_section, rf_path, channel, power_limit);
2018-07-03 14:50:43 +00:00
#endif
}
#endif /* #if (RTL8821A_SUPPORT == 1)*/