mirror of
https://github.com/chinawrj/rtl8812au
synced 2024-11-14 18:05:52 +00:00
457 lines
14 KiB
C
457 lines
14 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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/* ************************************************************
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* include files
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* ************************************************************ */
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#include "mp_precomp.h"
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#include "phydm_precomp.h"
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void
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phydm_dynamic_tx_power_init(
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void *p_dm_void
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)
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{
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struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
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#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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struct _ADAPTER *adapter = p_dm->adapter;
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PMGNT_INFO p_mgnt_info = &adapter->MgntInfo;
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HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
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/*if (!IS_HARDWARE_TYPE_8814A(adapter)) {*/
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/* PHYDM_DBG(p_dm,DBG_DYN_TXPWR, */
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/* ("phydm_dynamic_tx_power_init DynamicTxPowerEnable=%d\n", p_mgnt_info->is_dynamic_tx_power_enable));*/
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/* return;*/
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/*} else*/
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{
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p_mgnt_info->bDynamicTxPowerEnable = true;
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PHYDM_DBG(p_dm, DBG_DYN_TXPWR,
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("phydm_dynamic_tx_power_init DynamicTxPowerEnable=%d\n", p_mgnt_info->bDynamicTxPowerEnable));
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}
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#if DEV_BUS_TYPE == RT_USB_INTERFACE
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if (RT_GetInterfaceSelection(adapter) == INTF_SEL1_USB_High_Power) {
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odm_dynamic_tx_power_save_power_index(p_dm);
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p_mgnt_info->bDynamicTxPowerEnable = true;
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} else
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#else
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/* so 92c pci do not need dynamic tx power? vivi check it later */
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p_mgnt_info->bDynamicTxPowerEnable = false;
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#endif
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p_hal_data->LastDTPLvl = tx_high_pwr_level_normal;
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p_hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal;
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#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
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p_dm->last_dtp_lvl = tx_high_pwr_level_normal;
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p_dm->dynamic_tx_high_power_lvl = tx_high_pwr_level_normal;
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p_dm->tx_agc_ofdm_18_6 = odm_get_bb_reg(p_dm, 0xC24, MASKDWORD); /*TXAGC {18M 12M 9M 6M}*/
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#endif
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}
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void
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odm_dynamic_tx_power_save_power_index(
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void *p_dm_void
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)
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{
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#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
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u8 index;
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u32 power_index_reg[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
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#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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struct _ADAPTER *adapter = p_dm->adapter;
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HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
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for (index = 0; index < 6; index++)
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p_hal_data->PowerIndex_backup[index] = PlatformEFIORead1Byte(adapter, power_index_reg[index]);
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#endif
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#endif
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}
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void
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odm_dynamic_tx_power_restore_power_index(
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void *p_dm_void
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)
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{
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#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
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u8 index;
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struct _ADAPTER *adapter = p_dm->adapter;
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HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
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u32 power_index_reg[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
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for (index = 0; index < 6; index++)
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PlatformEFIOWrite1Byte(adapter, power_index_reg[index], p_hal_data->PowerIndex_backup[index]);
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#endif
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}
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void
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odm_dynamic_tx_power_write_power_index(
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void *p_dm_void,
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u8 value)
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{
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struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
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u8 index;
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u32 power_index_reg[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
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for (index = 0; index < 6; index++)
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/* platform_efio_write_1byte(adapter, power_index_reg[index], value); */
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odm_write_1byte(p_dm, power_index_reg[index], value);
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}
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void
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odm_dynamic_tx_power_nic_ce(
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void *p_dm_void
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)
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{
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#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
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#if (RTL8821A_SUPPORT == 1)
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struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
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u8 val;
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u8 rssi_tmp = p_dm->rssi_min;
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if (!(p_dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
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return;
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if (rssi_tmp >= TX_POWER_NEAR_FIELD_THRESH_LVL2) {
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p_dm->dynamic_tx_high_power_lvl = tx_high_pwr_level_level2;
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/**/
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} else if (rssi_tmp >= TX_POWER_NEAR_FIELD_THRESH_LVL1) {
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p_dm->dynamic_tx_high_power_lvl = tx_high_pwr_level_level1;
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/**/
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} else if (rssi_tmp < (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) {
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p_dm->dynamic_tx_high_power_lvl = tx_high_pwr_level_normal;
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/**/
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}
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if (p_dm->last_dtp_lvl != p_dm->dynamic_tx_high_power_lvl) {
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PHYDM_DBG(p_dm, DBG_DYN_TXPWR, ("update_DTP_lv: ((%d)) -> ((%d))\n", p_dm->last_dtp_lvl, p_dm->dynamic_tx_high_power_lvl));
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p_dm->last_dtp_lvl = p_dm->dynamic_tx_high_power_lvl;
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if (p_dm->support_ic_type & (ODM_RTL8821)) {
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if (p_dm->dynamic_tx_high_power_lvl == tx_high_pwr_level_level2) {
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odm_set_mac_reg(p_dm, 0x6D8, BIT(20) | BIT19 | BIT18, 1); /* Resp TXAGC offset = -3dB*/
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val = p_dm->tx_agc_ofdm_18_6 & 0xff;
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if (val >= 0x20)
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val -= 0x16;
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odm_set_bb_reg(p_dm, 0xC24, 0xff, val);
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PHYDM_DBG(p_dm, DBG_DYN_TXPWR, ("Set TX power: level 2\n"));
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} else if (p_dm->dynamic_tx_high_power_lvl == tx_high_pwr_level_level1) {
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odm_set_mac_reg(p_dm, 0x6D8, BIT(20) | BIT19 | BIT18, 1); /* Resp TXAGC offset = -3dB*/
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val = p_dm->tx_agc_ofdm_18_6 & 0xff;
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if (val >= 0x20)
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val -= 0x10;
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odm_set_bb_reg(p_dm, 0xC24, 0xff, val);
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PHYDM_DBG(p_dm, DBG_DYN_TXPWR, ("Set TX power: level 1\n"));
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} else if (p_dm->dynamic_tx_high_power_lvl == tx_high_pwr_level_normal) {
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odm_set_mac_reg(p_dm, 0x6D8, BIT(20) | BIT19 | BIT18, 0); /* Resp TXAGC offset = 0dB*/
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odm_set_bb_reg(p_dm, 0xC24, MASKDWORD, p_dm->tx_agc_ofdm_18_6);
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PHYDM_DBG(p_dm, DBG_DYN_TXPWR, ("Set TX power: normal\n"));
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}
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}
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}
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#endif
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#endif
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}
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void
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odm_dynamic_tx_power(
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void *p_dm_void
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)
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{
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/* */
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/* For AP/ADSL use struct rtl8192cd_priv* */
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/* For CE/NIC use struct _ADAPTER* */
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/* */
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/* struct _ADAPTER* p_adapter = p_dm->adapter;
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* struct rtl8192cd_priv* priv = p_dm->priv; */
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struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
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if (!(p_dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
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return;
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/* */
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/* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
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/* at the same time. In the stage2/3, we need to prive universal interface and merge all */
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/* HW dynamic mechanism. */
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/* */
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switch (p_dm->support_platform) {
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case ODM_WIN:
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odm_dynamic_tx_power_nic(p_dm);
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break;
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case ODM_CE:
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odm_dynamic_tx_power_nic_ce(p_dm);
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break;
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default:
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break;
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}
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}
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void
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odm_dynamic_tx_power_nic(
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void *p_dm_void
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)
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{
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struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
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if (!(p_dm->support_ability & ODM_BB_DYNAMIC_TXPWR))
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return;
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#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
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if (p_dm->support_ic_type == ODM_RTL8814A)
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odm_dynamic_tx_power_8814a(p_dm);
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else if (p_dm->support_ic_type & ODM_RTL8821) {
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struct _ADAPTER *adapter = p_dm->adapter;
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PMGNT_INFO p_mgnt_info = GetDefaultMgntInfo(adapter);
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if (p_mgnt_info->RegRspPwr == 1) {
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if (p_dm->rssi_min > 60)
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odm_set_mac_reg(p_dm, ODM_REG_RESP_TX_11AC, BIT(20) | BIT19 | BIT18, 1); /*Resp TXAGC offset = -3dB*/
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else if (p_dm->rssi_min < 55)
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odm_set_mac_reg(p_dm, ODM_REG_RESP_TX_11AC, BIT(20) | BIT19 | BIT18, 0); /*Resp TXAGC offset = 0dB*/
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}
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}
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#endif
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}
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void
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odm_dynamic_tx_power_8821(
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void *p_dm_void,
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u8 *p_desc,
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u8 mac_id
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)
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{
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#if (RTL8821A_SUPPORT == 1)
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#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
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struct cmn_sta_info *p_entry;
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u8 reg0xc56_byte;
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u8 txpwr_offset = 0;
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p_entry = p_dm->p_phydm_sta_info[mac_id];
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reg0xc56_byte = odm_read_1byte(p_dm, 0xc56);
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PHYDM_DBG(p_dm, DBG_DYN_TXPWR, ("reg0xc56_byte=%d\n", reg0xc56_byte));
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if (p_entry[mac_id].rssi_stat.rssi > 85) {
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/* Avoid TXAGC error after TX power offset is applied.
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For example: Reg0xc56=0x6, if txpwr_offset=3( reduce 11dB )
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Total power = 6-11= -5( overflow!! ), PA may be burned !
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so txpwr_offset should be adjusted by Reg0xc56*/
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if (reg0xc56_byte < 7)
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txpwr_offset = 1;
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else if (reg0xc56_byte < 11)
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txpwr_offset = 2;
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else
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txpwr_offset = 3;
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SET_TX_DESC_TX_POWER_OFFSET_8812(p_desc, txpwr_offset);
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PHYDM_DBG(p_dm, DBG_DYN_TXPWR, ("odm_dynamic_tx_power_8821: RSSI=%d, txpwr_offset=%d\n", p_entry[mac_id].rssi_stat.rssi, txpwr_offset));
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} else {
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SET_TX_DESC_TX_POWER_OFFSET_8812(p_desc, txpwr_offset);
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PHYDM_DBG(p_dm, DBG_DYN_TXPWR, ("odm_dynamic_tx_power_8821: RSSI=%d, txpwr_offset=%d\n", p_entry[mac_id].rssi_stat.rssi, txpwr_offset));
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}
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#endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/
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#endif /*#if (RTL8821A_SUPPORT==1)*/
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}
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#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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void
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odm_dynamic_tx_power_8814a(
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void *p_dm_void
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)
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{
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struct PHY_DM_STRUCT *p_dm = (struct PHY_DM_STRUCT *)p_dm_void;
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struct _ADAPTER *adapter = p_dm->adapter;
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PMGNT_INFO p_mgnt_info = &adapter->MgntInfo;
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HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
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s32 undecorated_smoothed_pwdb;
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PHYDM_DBG(p_dm, DBG_DYN_TXPWR,
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("TxLevel=%d p_mgnt_info->iot_action=%x p_mgnt_info->is_dynamic_tx_power_enable=%d\n",
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p_hal_data->DynamicTxHighPowerLvl, p_mgnt_info->IOTAction, p_mgnt_info->bDynamicTxPowerEnable));
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/*STA not connected and AP not connected*/
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if ((!p_mgnt_info->bMediaConnect) && (p_hal_data->EntryMinUndecoratedSmoothedPWDB == 0)) {
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PHYDM_DBG(p_dm, DBG_DYN_TXPWR, ("Not connected to any reset power lvl\n"));
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p_hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal;
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return;
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}
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if ((p_mgnt_info->bDynamicTxPowerEnable != true) || p_mgnt_info->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER)
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p_hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal;
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else {
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if (p_mgnt_info->bMediaConnect) { /*Default port*/
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if (ACTING_AS_AP(adapter) || ACTING_AS_IBSS(adapter)) {
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undecorated_smoothed_pwdb = p_hal_data->EntryMinUndecoratedSmoothedPWDB;
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PHYDM_DBG(p_dm, DBG_DYN_TXPWR, ("AP Client PWDB = 0x%x\n", undecorated_smoothed_pwdb));
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} else {
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undecorated_smoothed_pwdb = p_hal_data->UndecoratedSmoothedPWDB;
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PHYDM_DBG(p_dm, DBG_DYN_TXPWR, ("STA Default Port PWDB = 0x%x\n", undecorated_smoothed_pwdb));
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}
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} else {/*associated entry pwdb*/
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undecorated_smoothed_pwdb = p_hal_data->EntryMinUndecoratedSmoothedPWDB;
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PHYDM_DBG(p_dm, DBG_DYN_TXPWR, ("AP Ext Port PWDB = 0x%x\n", undecorated_smoothed_pwdb));
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}
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/*Should we separate as 2.4G/5G band?*/
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if (undecorated_smoothed_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL2) {
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p_hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_level2;
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PHYDM_DBG(p_dm, DBG_DYN_TXPWR, ("tx_high_pwr_level_level1 (TxPwr=0x0)\n"));
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} else if ((undecorated_smoothed_pwdb < (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3)) &&
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(undecorated_smoothed_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL1)) {
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p_hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_level1;
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PHYDM_DBG(p_dm, DBG_DYN_TXPWR, ("tx_high_pwr_level_level1 (TxPwr=0x10)\n"));
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} else if (undecorated_smoothed_pwdb < (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) {
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p_hal_data->DynamicTxHighPowerLvl = tx_high_pwr_level_normal;
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PHYDM_DBG(p_dm, DBG_DYN_TXPWR, ("tx_high_pwr_level_normal\n"));
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}
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}
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if (p_hal_data->DynamicTxHighPowerLvl != p_hal_data->LastDTPLvl) {
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PHYDM_DBG(p_dm, DBG_DYN_TXPWR, ("odm_dynamic_tx_power_8814a() channel = %d\n", p_hal_data->CurrentChannel));
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odm_set_tx_power_level8814(adapter, p_hal_data->CurrentChannel, p_hal_data->DynamicTxHighPowerLvl);
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}
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PHYDM_DBG(p_dm, DBG_DYN_TXPWR,
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("odm_dynamic_tx_power_8814a() channel = %d TXpower lvl=%d/%d\n",
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p_hal_data->CurrentChannel, p_hal_data->LastDTPLvl, p_hal_data->DynamicTxHighPowerLvl));
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p_hal_data->LastDTPLvl = p_hal_data->DynamicTxHighPowerLvl;
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}
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/**/
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/*For normal driver we always use the FW method to configure TX power index to reduce I/O transaction.*/
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/**/
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/**/
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void
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odm_set_tx_power_level8814(
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struct _ADAPTER *adapter,
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u8 channel,
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u8 pwr_lvl
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)
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{
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#if (DEV_BUS_TYPE == RT_USB_INTERFACE)
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u32 i, j, k = 0;
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u32 value[264] = {0};
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u32 path = 0, power_index, txagc_table_wd = 0x00801000;
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HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
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u8 jaguar2_rates[][4] = { {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M},
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{MGN_6M, MGN_9M, MGN_12M, MGN_18M},
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{MGN_24M, MGN_36M, MGN_48M, MGN_54M},
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{MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3},
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{MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7},
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{MGN_MCS8, MGN_MCS9, MGN_MCS10, MGN_MCS11},
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{MGN_MCS12, MGN_MCS13, MGN_MCS14, MGN_MCS15},
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{MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19},
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{MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23},
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{MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3},
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{MGN_VHT1SS_MCS4, MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7},
|
|
{MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9, MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1},
|
|
{MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4, MGN_VHT2SS_MCS5},
|
|
{MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9},
|
|
{MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3},
|
|
{MGN_VHT3SS_MCS4, MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7},
|
|
{MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9, 0, 0}
|
|
};
|
|
|
|
for (path = RF_PATH_A; path <= RF_PATH_D; ++path) {
|
|
|
|
u8 usb_host = UsbModeQueryHubUsbType(adapter);
|
|
u8 usb_rfset = UsbModeQueryRfSet(adapter);
|
|
u8 usb_rf_type = RT_GetRFType(adapter);
|
|
|
|
for (i = 0; i <= 16; i++) {
|
|
for (j = 0; j <= 3; j++) {
|
|
if (jaguar2_rates[i][j] == 0)
|
|
continue;
|
|
|
|
txagc_table_wd = 0x00801000;
|
|
power_index = (u32) PHY_GetTxPowerIndex(adapter, (u8)path, jaguar2_rates[i][j], p_hal_data->CurrentChannelBW, channel);
|
|
|
|
/*for Query bus type to recude tx power.*/
|
|
if (usb_host != USB_MODE_U3 && usb_rfset == 1 && IS_HARDWARE_TYPE_8814AU(adapter) && usb_rf_type == RF_3T3R) {
|
|
if (channel <= 14) {
|
|
if (power_index >= 16)
|
|
power_index -= 16;
|
|
else
|
|
power_index = 0;
|
|
} else
|
|
power_index = 0;
|
|
}
|
|
|
|
if (pwr_lvl == tx_high_pwr_level_level1) {
|
|
if (power_index >= 0x10)
|
|
power_index -= 0x10;
|
|
else
|
|
power_index = 0;
|
|
} else if (pwr_lvl == tx_high_pwr_level_level2)
|
|
power_index = 0;
|
|
|
|
txagc_table_wd |= (path << 8) | MRateToHwRate(jaguar2_rates[i][j]) | (power_index << 24);
|
|
|
|
PHY_SetTxPowerIndexShadow(adapter, (u8)power_index, (u8)path, jaguar2_rates[i][j]);
|
|
|
|
value[k++] = txagc_table_wd;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (adapter->MgntInfo.bScanInProgress == false && adapter->MgntInfo.RegFWOffload == 2)
|
|
HalDownloadTxPowerLevel8814(adapter, value);
|
|
#endif
|
|
}
|
|
#endif
|