mirror of
https://github.com/chinawrj/rtl8812au
synced 2024-09-20 05:00:47 +00:00
363 lines
7.7 KiB
C
363 lines
7.7 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __PHYDMDIG_H__
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#define __PHYDMDIG_H__
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/*#define DIG_VERSION "1.4"*/ /* 2017.04.18 YuChen. refine DIG code structure*/
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/*#define DIG_VERSION "2.0"*/ /* 2017.05.09 Dino. Move CCKPD to new files*/
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/*#define DIG_VERSION "2.1"*/ /* 2017.06.01 YuChen. Refine DFS condition*/
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#define DIG_VERSION "2.2" /* 2017.06.13 YuChen. Remove MP dig*/
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#define DIG_HW 0
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/*--------------------Define ---------------------------------------*/
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/*=== [DIG Boundary] ========================================*/
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/*DIG coverage mode*/
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#define DIG_MAX_COVERAGR 0x26
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#define DIG_MIN_COVERAGE 0x1c
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#define DIG_MAX_OF_MIN_COVERAGE 0x22
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/*DIG performance mode*/
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#if (DIG_HW == 1)
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#define DIG_MAX_BALANCE_MODE 0x32
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#else
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#define DIG_MAX_BALANCE_MODE 0x3e
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#endif
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#define DIG_MAX_OF_MIN_BALANCE_MODE 0x2a
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#define DIG_MAX_PERFORMANCE_MODE 0x5a
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#define DIG_MAX_OF_MIN_PERFORMANCE_MODE 0x40 /*from 3E -> 2A, refine by YuChen 2017/04/18*/
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#define DIG_MIN_PERFORMANCE 0x20
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/*DIG DFS function*/
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#define DIG_MAX_DFS 0x28
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#define DIG_MIN_DFS 0x20
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/*DIG LPS function*/
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#define DIG_MAX_LPS 0x3e
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#define DIG_MIN_LPS 0x20
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/*=== [DIG FA Threshold] ======================================*/
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/*Normal*/
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#define DM_DIG_FA_TH0 500
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#define DM_DIG_FA_TH1 750
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/*LPS*/
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#define DM_DIG_FA_TH0_LPS 4 /* -> 4 lps */
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#define DM_DIG_FA_TH1_LPS 15 /* -> 15 lps */
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#define DM_DIG_FA_TH2_LPS 30 /* -> 30 lps */
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#define RSSI_OFFSET_DIG_LPS 5
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/*LNA saturation check*/
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#define OFDM_AGC_TAB_0 0
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#define OFDM_AGC_TAB_2 2
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#define DIFF_RSSI_TO_IGI 10
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#define ONE_SEC_MS 1000
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/*--------------------Enum-----------------------------------*/
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enum dig_goupcheck_level {
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DIG_GOUPCHECK_LEVEL_0,
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DIG_GOUPCHECK_LEVEL_1,
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DIG_GOUPCHECK_LEVEL_2
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};
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enum phydm_dig_mode {
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PHYDM_DIG_PERFORAMNCE_MODE = 0,
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PHYDM_DIG_COVERAGE_MODE = 1,
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};
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enum lna_sat_timer_state {
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INIT_LNA_SAT_CHK_TIMMER,
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CANCEL_LNA_SAT_CHK_TIMMER,
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RELEASE_LNA_SAT_CHK_TIMMER
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};
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/*--------------------Define Struct-----------------------------------*/
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struct phydm_dig_struct {
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boolean is_ignore_dig; /*for old pause function*/
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boolean is_dbg_fa_th;
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u8 dig_mode_decision;
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u8 cur_ig_value;
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u8 rvrt_val;
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u8 igi_backup;
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u8 rx_gain_range_max; /*dig_dynamic_max*/
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u8 rx_gain_range_min; /*dig_dynamic_min*/
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u8 dm_dig_max; /*Absolutly upper bound*/
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u8 dm_dig_min; /*Absolutly lower bound*/
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u8 dig_max_of_min; /*Absolutly max of min*/
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boolean is_media_connect;
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u32 ant_div_rssi_max;
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u8 *is_p2p_in_process;
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u8 pause_lv_bitmap; /*bit-map of pause level*/
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u8 pause_dig_value[PHYDM_PAUSE_MAX_NUM];
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enum dig_goupcheck_level dig_go_up_check_level;
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u8 aaa_default;
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u16 fa_th[3];
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#if (RTL8822B_SUPPORT == 1 || RTL8197F_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
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u8 rf_gain_idx;
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u8 agc_table_idx;
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u8 big_jump_lmt[16];
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u8 enable_adjust_big_jump:1;
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u8 big_jump_step1:3;
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u8 big_jump_step2:2;
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u8 big_jump_step3:2;
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#endif
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u8 dig_upcheck_initial_value;
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u8 dig_level0_ratio_reciprocal;
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u8 dig_level1_ratio_reciprocal;
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#ifdef PHYDM_TDMA_DIG_SUPPORT
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u8 cur_ig_value_tdma;
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u8 low_ig_value;
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u8 tdma_dig_state; /*To distinguish which state is now.(L-sate or H-state)*/
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u8 tdma_dig_cnt; /*for phydm_tdma_dig_timer_check use*/
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u8 pre_tdma_dig_cnt;
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u8 sec_factor;
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u32 cur_timestamp;
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u32 pre_timestamp;
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u32 fa_start_timestamp;
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u32 fa_end_timestamp;
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u32 fa_acc_1sec_timestamp;
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#endif
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};
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struct phydm_fa_struct {
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u32 cnt_parity_fail;
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u32 cnt_rate_illegal;
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u32 cnt_crc8_fail;
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u32 cnt_crc8_fail_vht;
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u32 cnt_mcs_fail;
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u32 cnt_mcs_fail_vht;
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u32 cnt_ofdm_fail;
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u32 cnt_ofdm_fail_pre; /* For RTL8881A */
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u32 cnt_cck_fail;
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u32 cnt_all;
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u32 cnt_all_pre;
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u32 cnt_fast_fsync;
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u32 cnt_sb_search_fail;
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u32 cnt_ofdm_cca;
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u32 cnt_cck_cca;
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u32 cnt_cca_all;
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u32 cnt_bw_usc;
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u32 cnt_bw_lsc;
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u32 cnt_cck_crc32_error;
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u32 cnt_cck_crc32_ok;
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u32 cnt_ofdm_crc32_error;
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u32 cnt_ofdm_crc32_ok;
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u32 cnt_ht_crc32_error;
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u32 cnt_ht_crc32_ok;
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u32 cnt_ht_crc32_error_agg;
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u32 cnt_ht_crc32_ok_agg;
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u32 cnt_vht_crc32_error;
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u32 cnt_vht_crc32_ok;
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u32 cnt_crc32_error_all;
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u32 cnt_crc32_ok_all;
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u32 time_fa_all;
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boolean cck_block_enable;
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boolean ofdm_block_enable;
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u32 dbg_port0;
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boolean edcca_flag;
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};
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#ifdef PHYDM_TDMA_DIG_SUPPORT
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struct phydm_fa_acc_struct {
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u32 cnt_parity_fail;
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u32 cnt_rate_illegal;
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u32 cnt_crc8_fail;
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u32 cnt_mcs_fail;
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u32 cnt_ofdm_fail;
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u32 cnt_ofdm_fail_pre; /*For RTL8881A*/
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u32 cnt_cck_fail;
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u32 cnt_all;
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u32 cnt_all_pre;
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u32 cnt_fast_fsync;
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u32 cnt_sb_search_fail;
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u32 cnt_ofdm_cca;
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u32 cnt_cck_cca;
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u32 cnt_cca_all;
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u32 cnt_cck_crc32_error;
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u32 cnt_cck_crc32_ok;
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u32 cnt_ofdm_crc32_error;
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u32 cnt_ofdm_crc32_ok;
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u32 cnt_ht_crc32_error;
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u32 cnt_ht_crc32_ok;
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u32 cnt_vht_crc32_error;
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u32 cnt_vht_crc32_ok;
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u32 cnt_crc32_error_all;
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u32 cnt_crc32_ok_all;
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u32 cnt_all_1sec;
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u32 cnt_cca_all_1sec;
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u32 cnt_cck_fail_1sec;
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};
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#endif /*#ifdef PHYDM_TDMA_DIG_SUPPORT*/
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struct phydm_lna_sat_info_struct {
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u32 sat_cnt_acc_patha;
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u32 sat_cnt_acc_pathb;
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u32 check_time;
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boolean pre_sat_status;
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boolean cur_sat_status;
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struct phydm_timer_list phydm_lna_sat_chk_timer;
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u32 cur_timer_check_cnt;
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u32 pre_timer_check_cnt;
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};
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/*--------------------Function declaration-----------------------------*/
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void
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odm_write_dig(
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void *dm_void,
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u8 current_igi
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);
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void
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phydm_set_dig_val(
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void *dm_void,
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u32 *val_buf,
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u8 val_len
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);
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void
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odm_pause_dig(
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void *dm_void,
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enum phydm_pause_type pause_type,
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enum phydm_pause_level pause_level,
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u8 igi_value
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);
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void
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phydm_dig_init(
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void *dm_void
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);
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void
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phydm_dig(
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void *dm_void
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);
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void
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phydm_dig_lps_32k(
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void *dm_void
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);
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void
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phydm_dig_by_rssi_lps(
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void *dm_void
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);
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void
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odm_false_alarm_counter_statistics(
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void *dm_void
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);
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#ifdef PHYDM_TDMA_DIG_SUPPORT
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void
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phydm_set_tdma_dig_timer(
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void *dm_void
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);
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void
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phydm_tdma_dig_timer_check(
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void *dm_void
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);
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void
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phydm_tdma_dig(
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void *dm_void
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);
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void
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phydm_tdma_false_alarm_counter_check(
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void *dm_void
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);
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void
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phydm_tdma_dig_add_interrupt_mask_handler(
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void *dm_void
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);
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void
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phydm_false_alarm_counter_reset(
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void *dm_void
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);
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void
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phydm_false_alarm_counter_acc(
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void *dm_void,
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boolean rssi_dump_en
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);
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void
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phydm_false_alarm_counter_acc_reset(
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void *dm_void
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);
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#endif /*#ifdef PHYDM_TDMA_DIG_SUPPORT*/
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void
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phydm_set_ofdm_agc_tab(
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void *dm_void,
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u8 tab_sel
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);
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#ifdef PHYDM_LNA_SAT_CHK_SUPPORT
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u8
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phydm_get_ofdm_agc_tab(
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void *dm_void
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);
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void
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phydm_lna_sat_chk(
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void *dm_void
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);
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void
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phydm_lna_sat_chk_timers(
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void *dm_void,
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u8 state
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);
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void
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phydm_lna_sat_chk_watchdog(
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void *dm_void
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);
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#endif /*#if (PHYDM_LNA_SAT_CHK_SUPPORT == 1)*/
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void
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phydm_dig_debug(
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void *dm_void,
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char input[][16],
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u32 *_used,
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char *output,
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u32 *_out_len,
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u32 input_num
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);
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#endif
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