mirror of
https://github.com/chinawrj/rtl8812au
synced 2024-11-27 15:44:18 +00:00
Fix some compiler errors
This commit is contained in:
kimocoder
parent
19398a4630
commit
5484970659
@ -114,7 +114,7 @@ CheckNegative(
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* AGC_TAB.TXT
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******************************************************************************/
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u32 Array_MP_8814A_AGC_TAB[] = {
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u32 Array_MP_8814A_AGC_TAB[] = {
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0x80000001, 0x00000055, 0x40000000, 0x00000000,
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0x81C, 0xFE000003,
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0x81C, 0xFF000003,
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@ -1562,7 +1562,7 @@ ODM_GetVersion_MP_8814A_AGC_TAB(void)
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* PHY_REG.TXT
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******************************************************************************/
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u32 Array_MP_8814A_PHY_REG[] = {
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u32 Array_MP_8814A_PHY_REG[] = {
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0x800, 0x9020D010,
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0x804, 0x08011280,
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0x808, 0x0E0282FF,
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@ -3699,7 +3699,7 @@ ODM_GetVersion_MP_8814A_PHY_REG(void)
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* PHY_REG_MP.TXT
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******************************************************************************/
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u32 Array_MP_8814A_PHY_REG_MP[] = {
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u32 Array_MP_8814A_PHY_REG_MP[] = {
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0x8FC, 0x00000000,
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0x838, 0x86667641,
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@ -3769,7 +3769,7 @@ ODM_GetVersion_MP_8814A_PHY_REG_MP(void)
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* PHY_REG_PG.TXT
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******************************************************************************/
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u32 Array_MP_8814A_PHY_REG_PG[] = {
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u32 Array_MP_8814A_PHY_REG_PG[] = {
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0, 0, 0, 0x00000c20, 0xffffffff, 0x34363840,
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0, 0, 0, 0x00000c24, 0xffffffff, 0x42424444,
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0, 0, 0, 0x00000c28, 0xffffffff, 0x30323638,
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@ -3947,8 +3947,8 @@ odm_read_and_config_mp_8814a_phy_reg_pg(
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/******************************************************************************
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* PHY_REG_PG_Type2.TXT
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******************************************************************************/
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/*
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******************************************************************************\
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u32 Array_MP_8814A_PHY_REG_PG_Type2[] = {
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0, 0, 0, 0x00000c20, 0xffffffff, 0x36363636,
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0, 0, 0, 0x00000c24, 0xffffffff, 0x36363636,
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@ -4124,12 +4124,10 @@ _odm_read_and_config_mp_8814a_phy_reg_pg_type2(
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}
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/******************************************************************************
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******************************************************************************
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* PHY_REG_PG_Type3.TXT
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******************************************************************************/
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******************************************************************************
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/*
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u32 Array_MP_8814A_PHY_REG_PG_Type3[] = {
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0, 0, 0, 0x00000c20, 0xffffffff, 0x48484848,
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0, 0, 0, 0x00000c24, 0xffffffff, 0x46464646,
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@ -53,20 +53,20 @@ u4Byte driver3 = 0;
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(pDM_Odm->type_alna & 0xFF00) << 8 |
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(pDM_Odm->type_apa & 0xFF00) << 16;
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PHYDM_DBG(pDM_Odm, ODM_COMP_INIT,
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PHYDM_DBG(pDM_Odm, ODM_COMP_INIT,
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"===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4);
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PHYDM_DBG(pDM_Odm, ODM_COMP_INIT,
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PHYDM_DBG(pDM_Odm, ODM_COMP_INIT,
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"===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4);
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PHYDM_DBG(pDM_Odm, ODM_COMP_INIT,
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PHYDM_DBG(pDM_Odm, ODM_COMP_INIT,
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" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->support_platform, pDM_Odm->support_interface);
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PHYDM_DBG(pDM_Odm, ODM_COMP_INIT,
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PHYDM_DBG(pDM_Odm, ODM_COMP_INIT,
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" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->board_type, pDM_Odm->package_type);
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/*============== Value Defined Check ===============*/
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/*QFN Type [15:12] and Cut Version [27:24] need to do value check*/
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if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000)))
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return FALSE;
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if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000)))
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@ -75,8 +75,8 @@ u4Byte driver3 = 0;
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/*=============== Bit Defined Check ================*/
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/* We don't care [31:28] */
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cond1 &= 0x00FF0FFF;
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driver1 &= 0x00FF0FFF;
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cond1 &= 0x00FF0FFF;
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driver1 &= 0x00FF0FFF;
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if ((cond1 & driver1) == cond1) {
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u4Byte bitMask = 0;
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@ -114,7 +114,7 @@ CheckNegative(
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* RadioA.TXT
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******************************************************************************/
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u4Byte Array_MP_8814A_RadioA[] = {
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u4Byte Array_MP_8814A_RadioA[] = {
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0x018, 0x00013124,
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0x040, 0x00000C00,
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0x058, 0x00000F98,
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@ -1249,7 +1249,7 @@ ODM_GetVersion_MP_8814A_RadioA(void)
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* RadioB.TXT
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******************************************************************************/
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u4Byte Array_MP_8814A_RadioB[] = {
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u4Byte Array_MP_8814A_RadioB[] = {
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0x018, 0x00013124,
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0x040, 0x00000C00,
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0x058, 0x00000F98,
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@ -2292,7 +2292,7 @@ ODM_GetVersion_MP_8814A_RadioB(void)
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* RadioC.TXT
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******************************************************************************/
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u4Byte Array_MP_8814A_RadioC[] = {
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u4Byte Array_MP_8814A_RadioC[] = {
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0x018, 0x00013124,
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0x040, 0x00000C00,
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0x058, 0x00000F98,
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@ -3338,7 +3338,7 @@ ODM_GetVersion_MP_8814A_RadioC(void)
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* RadioD.TXT
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******************************************************************************/
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u4Byte Array_MP_8814A_RadioD[] = {
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u4Byte Array_MP_8814A_RadioD[] = {
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0x018, 0x00013124,
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0x040, 0x00000C00,
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0x058, 0x00000F98,
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@ -4332,7 +4332,7 @@ odm_read_and_config_mp_8814a_radiod(
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BOOLEAN bMatched = TRUE, bSkipped = FALSE;
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u4Byte ArrayLen = sizeof(Array_MP_8814A_RadioD)/sizeof(u4Byte);
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pu4Byte Array = Array_MP_8814A_RadioD;
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u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
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PHYDM_DBG(pDM_Odm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_8814A_RadioD\n");
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@ -4782,7 +4782,7 @@ odm_read_and_config_mp_8814a_txpowertrack_type5(
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* TXPWR_LMT.TXT
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******************************************************************************/
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const char *Array_MP_8814A_TXPWR_LMT[] = {
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const char *Array_MP_8814A_TXPWR_LMT[] = {
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"FCC", "2.4G", "20M", "CCK", "1T", "01", "36",
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"ETSI", "2.4G", "20M", "CCK", "1T", "01", "32",
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"MKK", "2.4G", "20M", "CCK", "1T", "01", "32",
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@ -5784,7 +5784,7 @@ odm_read_and_config_mp_8814a_txpwr_lmt(
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pu1Byte rfPath = Array[i+4];
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pu1Byte chnl = Array[i+5];
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pu1Byte val = Array[i+6];
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odm_ConfigBB_TXPWR_LMT_8814A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val);
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#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",",
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@ -6801,7 +6801,7 @@ _odm_read_and_config_mp_8814a_txpwr_lmt_type2(
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pu1Byte rfPath = Array[i+4];
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pu1Byte chnl = Array[i+5];
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pu1Byte val = Array[i+6];
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odm_ConfigBB_TXPWR_LMT_8814A(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val);
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#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",",
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@ -6811,11 +6811,10 @@ _odm_read_and_config_mp_8814a_txpwr_lmt_type2(
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}
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/******************************************************************************
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******************************************************************************
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* TXPWR_LMT_Type3.TXT
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******************************************************************************/
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******************************************************************************
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/*
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const char *Array_MP_8814A_TXPWR_LMT_Type3[] = {
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"FCC", "2.4G", "20M", "CCK", "1T", "01", "46",
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"ETSI", "2.4G", "20M", "CCK", "1T", "01", "40",
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@ -7791,7 +7790,6 @@ const char *Array_MP_8814A_TXPWR_LMT_Type3[] = {
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"MKK", "5G", "80M", "VHT", "4T", "155", "63"
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};
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/*
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void
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_odm_read_and_config_mp_8814a_txpwr_lmt_type3(
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struct dm_struct * pDM_Odm
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@ -7818,11 +7816,10 @@ _odm_read_and_config_mp_8814a_txpwr_lmt_type3(
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}
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/******************************************************************************
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******************************************************************************
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* TXPWR_LMT_Type5.TXT
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******************************************************************************/
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******************************************************************************
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/*
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const char *Array_MP_8814A_TXPWR_LMT_Type5[] = {
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"FCC", "2.4G", "20M", "CCK", "1T", "01", "46",
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"ETSI", "2.4G", "20M", "CCK", "1T", "01", "40",
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@ -8796,10 +8793,9 @@ const char *Array_MP_8814A_TXPWR_LMT_Type5[] = {
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"FCC", "5G", "80M", "VHT", "4T", "155", "46",
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"ETSI", "5G", "80M", "VHT", "4T", "155", "40",
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"MKK", "5G", "80M", "VHT", "4T", "155", "63"
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//};
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};
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/*
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void
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_odm_read_and_config_mp_8814a_txpwr_lmt_type5(
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struct dm_struct * pDM_Odm
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