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https://github.com/chinawrj/rtl8812au
synced 2024-11-14 09:55:50 +00:00
Code cleanup
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parent
005d1b8117
commit
40fcd1e3b8
@ -33,7 +33,7 @@ void rtl8814_sreset_xmit_status_check(_adapter *padapter)
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unsigned int diff_time;
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unsigned int diff_time;
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u32 txdma_status;
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u32 txdma_status;
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if( (txdma_status=rtw_read32(padapter, REG_TXDMA_STATUS)) !=0x00){
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if ( (txdma_status=rtw_read32(padapter, REG_TXDMA_STATUS)) !=0x00) {
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RTW_INFO("%s REG_TXDMA_STATUS:0x%08x\n", __FUNCTION__, txdma_status);
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RTW_INFO("%s REG_TXDMA_STATUS:0x%08x\n", __FUNCTION__, txdma_status);
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rtw_hal_sreset_reset(padapter);
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rtw_hal_sreset_reset(padapter);
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}
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}
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@ -51,7 +51,7 @@ void rtl8814_sreset_xmit_status_check(_adapter *padapter)
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if (psrtpriv->last_tx_complete_time == 0) {
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if (psrtpriv->last_tx_complete_time == 0) {
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psrtpriv->last_tx_complete_time = current_time;
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psrtpriv->last_tx_complete_time = current_time;
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}
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}
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else{
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else {
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diff_time = rtw_get_passing_time_ms(psrtpriv->last_tx_complete_time);
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diff_time = rtw_get_passing_time_ms(psrtpriv->last_tx_complete_time);
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if (diff_time > 4000) {
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if (diff_time > 4000) {
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u32 ability = 0;
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u32 ability = 0;
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@ -84,7 +84,7 @@ void rtl8814_sreset_linked_status_check(_adapter *padapter)
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u32 rx_dma_status = 0;
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u32 rx_dma_status = 0;
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rx_dma_status = rtw_read32(padapter,REG_RXDMA_STATUS);
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rx_dma_status = rtw_read32(padapter,REG_RXDMA_STATUS);
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if(rx_dma_status!= 0x00){
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if (rx_dma_status!= 0x00) {
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RTW_INFO("%s REG_RXDMA_STATUS:0x%08x\n",__FUNCTION__,rx_dma_status);
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RTW_INFO("%s REG_RXDMA_STATUS:0x%08x\n",__FUNCTION__,rx_dma_status);
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}
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}
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#if 0
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#if 0
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@ -111,4 +111,3 @@ void rtl8814_sreset_linked_status_check(_adapter *padapter)
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}
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}
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}
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}
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#endif
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#endif
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