mirror of
https://github.com/chinawrj/rtl8812au
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457 lines
9.0 KiB
C
457 lines
9.0 KiB
C
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#ifndef __PHYDMRAINFO_H__
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#define __PHYDMRAINFO_H__
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/*#define RAINFO_VERSION "2.0"*/ /*2014.11.04*/
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/*#define RAINFO_VERSION "3.0"*/ /*2015.01.13 Dino*/
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/*#define RAINFO_VERSION "3.1"*/ /*2015.01.14 Dino*/
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/*#define RAINFO_VERSION "3.3"*/ /*2015.07.29 YuChen*/
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/*#define RAINFO_VERSION "3.4"*/ /*2015.12.15 Stanley*/
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/*#define RAINFO_VERSION "4.0"*/ /*2016.03.24 Dino, Add more RA mask state and Phydm-lize partial ra mask function */
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/*#define RAINFO_VERSION "4.1"*/ /*2016.04.20 Dino, Add new function to adjust PCR RA threshold */
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/*#define RAINFO_VERSION "4.2"*/ /*2016.05.17 Dino, Add H2C debug cmd */
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/*#define RAINFO_VERSION "4.3"*/ /*2016.07.11 Dino, Fix RA hang in CCK 1M problem */
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#define RAINFO_VERSION "5.0" /*2017.04.20 Dino, the 3rd PHYDM reform*/
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#define FORCED_UPDATE_RAMASK_PERIOD 5
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#define H2C_MAX_LENGTH 7
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#define RA_FLOOR_UP_GAP 3
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#define RA_FLOOR_TABLE_SIZE 7
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#define ACTIVE_TP_THRESHOLD 1
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#define RA_RETRY_DESCEND_NUM 2
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#define RA_RETRY_LIMIT_LOW 4
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#define RA_RETRY_LIMIT_HIGH 32
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#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
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#define RA_FIRST_MACID 1
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#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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#define RA_FIRST_MACID 0
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#define WIN_DEFAULT_PORT_MACID 0
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#define WIN_BT_PORT_MACID 2
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#else /*if (DM_ODM_SUPPORT_TYPE == ODM_CE)*/
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#define RA_FIRST_MACID 0
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#endif
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#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
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#define AP_InitRateAdaptiveState odm_rate_adaptive_state_ap_init
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#endif
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#define DM_RATR_STA_INIT 0
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#define DM_RATR_STA_HIGH 1
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#define DM_RATR_STA_MIDDLE 2
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#define DM_RATR_STA_LOW 3
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#define DM_RATR_STA_ULTRA_LOW 4
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enum phydm_ra_dbg_para_e {
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RADBG_PCR_TH_OFFSET = 0,
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RADBG_RTY_PENALTY = 1,
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RADBG_N_HIGH = 2,
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RADBG_N_LOW = 3,
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RADBG_TRATE_UP_TABLE = 4,
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RADBG_TRATE_DOWN_TABLE = 5,
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RADBG_TRYING_NECESSARY = 6,
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RADBG_TDROPING_NECESSARY = 7,
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RADBG_RATE_UP_RTY_RATIO = 8,
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RADBG_RATE_DOWN_RTY_RATIO = 9, /* u8 */
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RADBG_DEBUG_MONITOR1 = 0xc,
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RADBG_DEBUG_MONITOR2 = 0xd,
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RADBG_DEBUG_MONITOR3 = 0xe,
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RADBG_DEBUG_MONITOR4 = 0xf,
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RADBG_DEBUG_MONITOR5 = 0x10,
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NUM_RA_PARA
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};
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enum phydm_wireless_mode_e {
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PHYDM_WIRELESS_MODE_UNKNOWN = 0x00,
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PHYDM_WIRELESS_MODE_A = 0x01,
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PHYDM_WIRELESS_MODE_B = 0x02,
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PHYDM_WIRELESS_MODE_G = 0x04,
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PHYDM_WIRELESS_MODE_AUTO = 0x08,
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PHYDM_WIRELESS_MODE_N_24G = 0x10,
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PHYDM_WIRELESS_MODE_N_5G = 0x20,
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PHYDM_WIRELESS_MODE_AC_5G = 0x40,
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PHYDM_WIRELESS_MODE_AC_24G = 0x80,
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PHYDM_WIRELESS_MODE_AC_ONLY = 0x100,
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PHYDM_WIRELESS_MODE_MAX = 0x800,
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PHYDM_WIRELESS_MODE_ALL = 0xFFFF
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};
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enum phydm_rateid_idx_e {
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PHYDM_BGN_40M_2SS = 0,
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PHYDM_BGN_40M_1SS = 1,
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PHYDM_BGN_20M_2SS = 2,
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PHYDM_BGN_20M_1SS = 3,
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PHYDM_GN_N2SS = 4,
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PHYDM_GN_N1SS = 5,
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PHYDM_BG = 6,
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PHYDM_G = 7,
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PHYDM_B_20M = 8,
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PHYDM_ARFR0_AC_2SS = 9,
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PHYDM_ARFR1_AC_1SS = 10,
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PHYDM_ARFR2_AC_2G_1SS = 11,
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PHYDM_ARFR3_AC_2G_2SS = 12,
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PHYDM_ARFR4_AC_3SS = 13,
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PHYDM_ARFR5_N_3SS = 14
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};
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#if (RATE_ADAPTIVE_SUPPORT == 1)/* 88E RA */
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struct _odm_ra_info_ {
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u8 rate_id;
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u32 rate_mask;
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u32 ra_use_rate;
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u8 rate_sgi;
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u8 rssi_sta_ra;
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u8 pre_rssi_sta_ra;
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u8 sgi_enable;
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u8 decision_rate;
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u8 pre_rate;
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u8 highest_rate;
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u8 lowest_rate;
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u32 nsc_up;
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u32 nsc_down;
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u16 RTY[5];
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u32 TOTAL;
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u16 DROP;
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u8 active;
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u16 rpt_time;
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u8 ra_waiting_counter;
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u8 ra_pending_counter;
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u8 ra_drop_after_down;
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#if 1 /* POWER_TRAINING_ACTIVE == 1 */ /* For compile pass only~! */
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u8 pt_active; /* on or off */
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u8 pt_try_state; /* 0 trying state, 1 for decision state */
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u8 pt_stage; /* 0~6 */
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u8 pt_stop_count; /* Stop PT counter */
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u8 pt_pre_rate; /* if rate change do PT */
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u8 pt_pre_rssi; /* if RSSI change 5% do PT */
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u8 pt_mode_ss; /* decide whitch rate should do PT */
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u8 ra_stage; /* StageRA, decide how many times RA will be done between PT */
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u8 pt_smooth_factor;
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#endif
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#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
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u8 rate_down_counter;
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u8 rate_up_counter;
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u8 rate_direction;
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u8 bounding_type;
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u8 bounding_counter;
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u8 bounding_learning_time;
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u8 rate_down_start_time;
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#endif
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};
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#endif
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struct _rate_adaptive_table_ {
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u8 firstconnect;
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#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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boolean PT_collision_pre;
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#endif
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#if (defined(CONFIG_RA_DBG_CMD))
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boolean is_ra_dbg_init;
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u8 RTY_P[ODM_NUM_RATE_IDX];
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u8 RTY_P_default[ODM_NUM_RATE_IDX];
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boolean RTY_P_modify_note[ODM_NUM_RATE_IDX];
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u8 RATE_UP_RTY_RATIO[ODM_NUM_RATE_IDX];
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u8 RATE_UP_RTY_RATIO_default[ODM_NUM_RATE_IDX];
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boolean RATE_UP_RTY_RATIO_modify_note[ODM_NUM_RATE_IDX];
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u8 RATE_DOWN_RTY_RATIO[ODM_NUM_RATE_IDX];
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u8 RATE_DOWN_RTY_RATIO_default[ODM_NUM_RATE_IDX];
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boolean RATE_DOWN_RTY_RATIO_modify_note[ODM_NUM_RATE_IDX];
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boolean ra_para_feedback_req;
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u8 para_idx;
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u8 rate_idx;
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u8 value;
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u16 value_16;
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u8 rate_length;
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#endif
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/*u8 link_tx_rate[ODM_ASSOCIATE_ENTRY_NUM];*/
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u8 ra_ratio[ODM_ASSOCIATE_ENTRY_NUM];
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u8 mu1_rate[30];
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u8 highest_client_tx_order;
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u16 highest_client_tx_rate_order;
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u8 power_tracking_flag;
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u8 RA_threshold_offset;
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u8 RA_offset_direction;
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u8 up_ramask_cnt; /*force update_ra_mask counter*/
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u8 up_ramask_cnt_tmp; /*Just for debug, should be removed latter*/
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#if (defined(CONFIG_RA_DYNAMIC_RTY_LIMIT))
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u8 per_rate_retrylimit_20M[ODM_NUM_RATE_IDX];
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u8 per_rate_retrylimit_40M[ODM_NUM_RATE_IDX];
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u8 retry_descend_num;
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u8 retrylimit_low;
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u8 retrylimit_high;
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#endif
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u8 ldpc_thres; /* if RSSI > ldpc_thres => switch from LPDC to BCC */
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void (*record_ra_info)(void *p_dm_void, u8 macid, struct cmn_sta_info *p_sta, u64 ra_mask);
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};
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void
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phydm_h2C_debug(
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void *p_dm_void,
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u32 *const dm_value,
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u32 *_used,
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char *output,
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u32 *_out_len
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);
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#if (defined(CONFIG_RA_DBG_CMD))
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void
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odm_RA_debug(
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void *p_dm_void,
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u32 *const dm_value
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);
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void
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odm_ra_para_adjust_init(
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void *p_dm_void
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);
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#endif
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void
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phydm_ra_debug(
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void *p_dm_void,
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char input[][16],
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u32 *_used,
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char *output,
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u32 *_out_len
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);
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void
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odm_c2h_ra_para_report_handler(
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void *p_dm_void,
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u8 *cmd_buf,
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u8 cmd_len
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);
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void
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odm_ra_para_adjust(
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void *p_dm_void
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);
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void
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phydm_ra_dynamic_retry_count(
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void *p_dm_void
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);
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void
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phydm_ra_dynamic_retry_limit(
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void *p_dm_void
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);
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void
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phydm_print_rate(
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void *p_dm_void,
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u8 rate,
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u32 dbg_component
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);
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void
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phydm_c2h_ra_report_handler(
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void *p_dm_void,
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u8 *cmd_buf,
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u8 cmd_len
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);
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u8
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phydm_rate_order_compute(
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void *p_dm_void,
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u8 rate_idx
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);
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void
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phydm_ra_info_watchdog(
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void *p_dm_void
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);
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void
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phydm_ra_info_init(
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void *p_dm_void
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);
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void
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phydm_modify_RA_PCR_threshold(
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void *p_dm_void,
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u8 RA_offset_direction,
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u8 RA_threshold_offset
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);
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u8
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phydm_vht_en_mapping(
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void *p_dm_void,
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u32 wireless_mode
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);
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u8
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phydm_rate_id_mapping(
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void *p_dm_void,
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u32 wireless_mode,
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u8 rf_type,
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u8 bw
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);
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void
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phydm_update_hal_ra_mask(
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void *p_dm_void,
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u32 wireless_mode,
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u8 rf_type,
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u8 BW,
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u8 mimo_ps_enable,
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u8 disable_cck_rate,
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u32 *ratr_bitmap_msb_in,
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u32 *ratr_bitmap_in,
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u8 tx_rate_level
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);
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void
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phydm_refresh_rate_adaptive_mask(
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void *p_dm_void
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);
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u8
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phydm_rssi_lv_dec(
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void *p_dm_void,
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u32 rssi,
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u8 ratr_state
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);
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void
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odm_ra_post_action_on_assoc(
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void *p_dm
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);
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u8
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odm_find_rts_rate(
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void *p_dm_void,
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u8 tx_rate,
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boolean is_erp_protect
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);
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void
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phydm_show_sta_info(
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void *p_dm_void,
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char input[][16],
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u32 *_used,
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char *output,
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u32 *_out_len,
|
||
|
|
u32 input_num
|
||
|
|
);
|
||
|
|
|
||
|
|
#ifdef PHYDM_3RD_REFORM_RA_MASK
|
||
|
|
|
||
|
|
void
|
||
|
|
phydm_ra_registed(
|
||
|
|
void *p_dm_void,
|
||
|
|
u8 macid,
|
||
|
|
u8 rssi_from_assoc
|
||
|
|
);
|
||
|
|
|
||
|
|
void
|
||
|
|
phydm_ra_offline(
|
||
|
|
void *p_dm_void,
|
||
|
|
u8 macid
|
||
|
|
);
|
||
|
|
|
||
|
|
|
||
|
|
void
|
||
|
|
phydm_ra_mask_watchdog(
|
||
|
|
void *p_dm_void
|
||
|
|
);
|
||
|
|
|
||
|
|
#endif
|
||
|
|
|
||
|
|
|
||
|
|
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
|
||
|
|
|
||
|
|
void
|
||
|
|
odm_refresh_basic_rate_mask(
|
||
|
|
void *p_dm_void
|
||
|
|
);
|
||
|
|
|
||
|
|
void
|
||
|
|
odm_update_init_rate_work_item_callback(
|
||
|
|
void *p_context
|
||
|
|
);
|
||
|
|
|
||
|
|
void
|
||
|
|
odm_refresh_ldpc_rts_mp(
|
||
|
|
struct _ADAPTER *p_adapter,
|
||
|
|
struct PHY_DM_STRUCT *p_dm,
|
||
|
|
u8 m_mac_id,
|
||
|
|
u8 iot_peer,
|
||
|
|
s32 undecorated_smoothed_pwdb
|
||
|
|
);
|
||
|
|
|
||
|
|
void
|
||
|
|
odm_rate_adaptive_state_ap_init(
|
||
|
|
void *PADAPTER_VOID,
|
||
|
|
struct cmn_sta_info *p_entry
|
||
|
|
);
|
||
|
|
|
||
|
|
#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
|
||
|
|
|
||
|
|
void
|
||
|
|
phydm_gen_ramask_h2c_AP(
|
||
|
|
void *p_dm_void,
|
||
|
|
struct rtl8192cd_priv *priv,
|
||
|
|
struct sta_info *p_entry,
|
||
|
|
u8 rssi_level
|
||
|
|
);
|
||
|
|
|
||
|
|
#endif/*#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))*/
|
||
|
|
|
||
|
|
|
||
|
|
#if (defined(CONFIG_RA_DYNAMIC_RATE_ID))
|
||
|
|
void
|
||
|
|
phydm_ra_dynamic_rate_id_on_assoc(
|
||
|
|
void *p_dm_void,
|
||
|
|
u8 wireless_mode,
|
||
|
|
u8 init_rate_id
|
||
|
|
);
|
||
|
|
|
||
|
|
void
|
||
|
|
phydm_ra_dynamic_rate_id_init(
|
||
|
|
void *p_dm_void
|
||
|
|
);
|
||
|
|
|
||
|
|
void
|
||
|
|
phydm_update_rate_id(
|
||
|
|
void *p_dm_void,
|
||
|
|
u8 rate,
|
||
|
|
u8 platform_macid
|
||
|
|
);
|
||
|
|
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif /*#ifndef __ODMRAINFO_H__*/
|