mirror of
https://github.com/chinawrj/rtl8812au
synced 2024-11-14 18:05:52 +00:00
130 lines
3.2 KiB
C
130 lines
3.2 KiB
C
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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/* ************************************************************
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* include files
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* ************************************************************ */
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#include "mp_precomp.h"
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#include "../phydm_precomp.h"
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#if (RTL8821A_SUPPORT == 1)
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s8 phydm_cck_rssi_8821a(struct dm_struct *dm, u16 lna_idx, u8 vga_idx)
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{
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s8 rx_pwr_all = 0;
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switch (lna_idx) {
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case 7:
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if (vga_idx <= 27)
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rx_pwr_all = -94 + 2 * (27 - vga_idx);
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else
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rx_pwr_all = -94;
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break;
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case 6:
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rx_pwr_all = -42 + 2 * (2 - vga_idx);
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break;
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case 5:
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rx_pwr_all = -36 + 2 * (7 - vga_idx);
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break;
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case 4:
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rx_pwr_all = -30 + 2 * (7 - vga_idx);
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break;
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case 3:
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rx_pwr_all = -18 + 2 * (7 - vga_idx);
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break;
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case 2:
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rx_pwr_all = 2 * (5 - vga_idx);
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break;
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case 1:
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rx_pwr_all = 14 - 2 * vga_idx;
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break;
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case 0:
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rx_pwr_all = 20 - 2 * vga_idx;
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break;
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default:
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break;
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}
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return rx_pwr_all;
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}
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void
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phydm_set_ext_band_switch_8821A(
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void *dm_void,
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u32 band
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)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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/*Output Pin Settings*/
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odm_set_mac_reg(dm, 0x4C, BIT(23), 0); /*select DPDT_P and DPDT_N as output pin*/
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odm_set_mac_reg(dm, 0x4C, BIT(24), 1); /*by WLAN control*/
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odm_set_bb_reg(dm, 0xCB4, 0xF, 7); /*DPDT_P = 1b'0*/
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odm_set_bb_reg(dm, 0xCB4, 0xF0, 7); /*DPDT_N = 1b'0*/
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if (band == ODM_BAND_2_4G) {
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odm_set_bb_reg(dm, 0xCB4, (BIT(29) | BIT(28)), 1);
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PHYDM_DBG(dm, DBG_ANT_DIV, "***8821A set band switch = 2b'01\n");
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} else {
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odm_set_bb_reg(dm, 0xCB4, BIT(29) | BIT(28), 2);
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PHYDM_DBG(dm, DBG_ANT_DIV, "***8821A set band switch = 2b'10\n");
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}
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}
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void
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odm_dynamic_try_state_agg_8821a(
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struct dm_struct *dm
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)
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{
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if ((dm->support_ic_type & ODM_RTL8821) && (dm->support_interface == ODM_ITRF_USB)) {
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if (dm->rssi_min > 25)
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odm_write_1byte(dm, 0x4CF, 0x02);
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else if (dm->rssi_min < 20)
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odm_write_1byte(dm, 0x4CF, 0x00);
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}
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}
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void
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odm_dynamic_packet_detection_th_8821a(
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struct dm_struct *dm
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)
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{
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if (dm->support_ic_type & ODM_RTL8821) {
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if (dm->rssi_min <= 25) {
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/*odm_set_bb_reg(dm, REG_PWED_TH_JAGUAR, MASKDWORD, 0x2aaaf1a8);*/
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odm_set_bb_reg(dm, REG_PWED_TH_JAGUAR, 0x1ff0, 0x11a);
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odm_set_bb_reg(dm, REG_BW_INDICATION_JAGUAR, BIT(26), 1);
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} else if (dm->rssi_min >= 30) {
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/*odm_set_bb_reg(dm, REG_PWED_TH_JAGUAR, MASKDWORD, 0x2aaaeec8);*/
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odm_set_bb_reg(dm, REG_PWED_TH_JAGUAR, 0x1ff0, 0xec);
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odm_set_bb_reg(dm, REG_BW_INDICATION_JAGUAR, BIT(26), 0);
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}
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}
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}
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void
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odm_hw_setting_8821a(
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struct dm_struct *dm
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)
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{
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odm_dynamic_try_state_agg_8821a(dm);
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odm_dynamic_packet_detection_th_8821a(dm);
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}
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#endif /* #if (RTL8821A_SUPPORT == 1) */
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