mirror of
https://github.com/chinawrj/rtl8812au
synced 2024-11-08 20:35:07 +00:00
91 lines
3.4 KiB
C
91 lines
3.4 KiB
C
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/******************************************************************************
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*
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* Copyright(c) 2013 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#ifndef __RTL8821A_SPEC_H__
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#define __RTL8821A_SPEC_H__
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#include <drv_conf.h>
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/* This file should based on "hal_com_reg.h" */
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#include <hal_com_reg.h>
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/* Because 8812a and 8821a is the same serial,
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* most of 8821a register definitions are the same as 8812a. */
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#include <rtl8812a_spec.h>
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/* ************************************************************
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* 8821A Regsiter offset definition
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* ************************************************************ */
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/* ************************************************************
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* MAC register
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* ************************************************************ */
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/* -----------------------------------------------------
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* 0x0000h ~ 0x00FFh System Configuration
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* ----------------------------------------------------- */
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/* -----------------------------------------------------
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* 0x0100h ~ 0x01FFh MACTOP General Configuration
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* ----------------------------------------------------- */
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#define REG_WOWLAN_WAKE_REASON REG_MCUTST_WOWLAN
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/* -----------------------------------------------------
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* 0x0200h ~ 0x027Fh TXDMA Configuration
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* ----------------------------------------------------- */
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/* -----------------------------------------------------
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* 0x0280h ~ 0x02FFh RXDMA Configuration
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* ----------------------------------------------------- */
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/* -----------------------------------------------------
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* 0x0300h ~ 0x03FFh PCIe
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* ----------------------------------------------------- */
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/* -----------------------------------------------------
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* 0x0400h ~ 0x047Fh Protocol Configuration
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* ----------------------------------------------------- */
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/* -----------------------------------------------------
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* 0x0500h ~ 0x05FFh EDCA Configuration
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* ----------------------------------------------------- */
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/* -----------------------------------------------------
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* 0x0600h ~ 0x07FFh WMAC Configuration
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* ----------------------------------------------------- */
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/* ************************************************************
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* SDIO Bus Specification
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* ************************************************************ */
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/* -----------------------------------------------------
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* SDIO CMD Address Mapping
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* ----------------------------------------------------- */
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/* -----------------------------------------------------
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* I/O bus domain (Host)
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* ----------------------------------------------------- */
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/* -----------------------------------------------------
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* SDIO register
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* ----------------------------------------------------- */
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#define SDIO_REG_FREE_TXPG2 0x024
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#define SDIO_REG_HCPWM1_8821A 0x025
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/* ************************************************************
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* Regsiter Bit and Content definition
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* ************************************************************ */
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#endif /* __RTL8821A_SPEC_H__ */
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