2018-06-22 16:48:32 +00:00
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/******************************************************************************
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*
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2019-05-24 19:43:57 +00:00
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* Copyright(c) 2015 - 2018 Realtek Corporation.
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2018-06-22 16:48:32 +00:00
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#ifndef _HAL_HALMAC_H_
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#define _HAL_HALMAC_H_
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#include <drv_types.h> /* adapter_to_dvobj(), struct intf_hdl and etc. */
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#include <hal_data.h> /* struct hal_spec_t */
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2018-08-24 20:52:34 +00:00
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#include "halmac/halmac_api.h" /* struct halmac_adapter* and etc. */
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2018-06-22 16:48:32 +00:00
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/* HALMAC Definition for Driver */
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#define RTW_HALMAC_H2C_MAX_SIZE 8
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#define RTW_HALMAC_BA_SSN_RPT_SIZE 4
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#define dvobj_set_halmac(d, mac) ((d)->halmac = (mac))
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2018-08-24 20:52:34 +00:00
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#define dvobj_to_halmac(d) ((struct halmac_adapter *)((d)->halmac))
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2018-06-22 16:48:32 +00:00
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#define adapter_to_halmac(p) dvobj_to_halmac(adapter_to_dvobj(p))
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/* for H2C cmd */
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#define MAX_H2C_BOX_NUMS 4
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#define MESSAGE_BOX_SIZE 4
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#define EX_MESSAGE_BOX_SIZE 4
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typedef enum _RTW_HALMAC_MODE {
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RTW_HALMAC_MODE_NORMAL,
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RTW_HALMAC_MODE_WIFI_TEST,
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} RTW_HALMAC_MODE;
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union rtw_phy_para_data {
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struct _mac {
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2018-08-24 20:52:34 +00:00
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u32 value; /* value to be set in bit mask(msk) */
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u32 msk; /* bit mask */
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u16 offset; /* address */
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u8 msk_en; /* 0/1 for msk invalid/valid */
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2018-06-22 16:48:32 +00:00
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u8 size; /* Unit is bytes, and value should be 1/2/4 */
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} mac;
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struct _bb {
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u32 value;
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u32 msk;
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u16 offset;
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u8 msk_en;
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u8 size;
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} bb;
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struct _rf {
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u32 value;
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u32 msk;
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u8 offset;
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u8 msk_en;
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/*
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* 0: path A
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* 1: path B
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* 2: path C
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* 3: path D
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*/
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u8 path;
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} rf;
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struct _delay {
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/*
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* 0: microsecond (us)
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* 1: millisecond (ms)
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*/
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u8 unit;
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u16 value;
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} delay;
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};
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struct rtw_phy_parameter {
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/*
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* 0: MAC register
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* 1: BB register
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* 2: RF register
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* 3: Delay
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* 0xFF: Latest(End) command
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*/
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u8 cmd;
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union rtw_phy_para_data data;
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};
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struct rtw_halmac_bcn_ctrl {
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u8 rx_bssid_fit:1; /* 0:HW handle beacon, 1:ignore */
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u8 txbcn_rpt:1; /* Enable TXBCN report in ad hoc and AP mode */
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u8 tsf_update:1; /* Update TSF when beacon or probe response */
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u8 enable_bcn:1; /* Enable beacon related functions */
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u8 rxbcn_rpt:1; /* Enable RXBCNOK report */
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2024-07-02 06:09:52 +00:00
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u8 p2p_ctwin:1; /* Enable P2P CTN WINDOWS function */
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2018-06-22 16:48:32 +00:00
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u8 p2p_bcn_area:1; /* Enable P2P BCN area on function */
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};
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2018-08-24 20:52:34 +00:00
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extern struct halmac_platform_api rtw_halmac_platform_api;
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2018-06-22 16:48:32 +00:00
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/* HALMAC API for Driver(HAL) */
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u8 rtw_halmac_read8(struct intf_hdl *, u32 addr);
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u16 rtw_halmac_read16(struct intf_hdl *, u32 addr);
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u32 rtw_halmac_read32(struct intf_hdl *, u32 addr);
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void rtw_halmac_read_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem);
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#ifdef CONFIG_SDIO_INDIRECT_ACCESS
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u8 rtw_halmac_iread8(struct intf_hdl *pintfhdl, u32 addr);
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u16 rtw_halmac_iread16(struct intf_hdl *pintfhdl, u32 addr);
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u32 rtw_halmac_iread32(struct intf_hdl *pintfhdl, u32 addr);
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#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
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int rtw_halmac_write8(struct intf_hdl *, u32 addr, u8 value);
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int rtw_halmac_write16(struct intf_hdl *, u32 addr, u16 value);
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int rtw_halmac_write32(struct intf_hdl *, u32 addr, u32 value);
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/* Software Information */
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void rtw_halmac_get_version(char *str, u32 len);
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/* Software Initialization */
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2018-08-24 20:52:34 +00:00
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int rtw_halmac_init_adapter(struct dvobj_priv *d, struct halmac_platform_api *pf_api);
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2018-06-22 16:48:32 +00:00
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int rtw_halmac_deinit_adapter(struct dvobj_priv *);
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/* Get operations */
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2018-08-24 20:52:34 +00:00
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int rtw_halmac_get_hw_value(struct dvobj_priv *d, enum halmac_hw_id hw_id, void *pvalue);
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2018-06-22 16:48:32 +00:00
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int rtw_halmac_get_tx_fifo_size(struct dvobj_priv *d, u32 *size);
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int rtw_halmac_get_rx_fifo_size(struct dvobj_priv *d, u32 *size);
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int rtw_halmac_get_rsvd_drv_pg_bndy(struct dvobj_priv *d, u16 *bndy);
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int rtw_halmac_get_page_size(struct dvobj_priv *d, u32 *size);
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int rtw_halmac_get_tx_agg_align_size(struct dvobj_priv *d, u16 *size);
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int rtw_halmac_get_rx_agg_align_size(struct dvobj_priv *d, u8 *size);
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int rtw_halmac_get_rx_drv_info_sz(struct dvobj_priv *, u8 *sz);
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int rtw_halmac_get_tx_desc_size(struct dvobj_priv *d, u32 *size);
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int rtw_halmac_get_rx_desc_size(struct dvobj_priv *d, u32 *size);
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int rtw_halmac_get_ori_h2c_size(struct dvobj_priv *d, u32 *size);
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int rtw_halmac_get_oqt_size(struct dvobj_priv *d, u8 *size);
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int rtw_halmac_get_ac_queue_number(struct dvobj_priv *d, u8 *num);
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int rtw_halmac_get_mac_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr);
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int rtw_halmac_get_network_type(struct dvobj_priv *d, enum _hw_port hwport, u8 *type);
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int rtw_halmac_get_bcn_ctrl(struct dvobj_priv *d, enum _hw_port hwport, struct rtw_halmac_bcn_ctrl *bcn_ctrl);
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/*int rtw_halmac_get_wow_reason(struct dvobj_priv *, u8 *reason);*/
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/* Set operations */
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2018-08-24 20:52:34 +00:00
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int rtw_halmac_config_rx_info(struct dvobj_priv *d, enum halmac_drv_info info);
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2018-06-22 16:48:32 +00:00
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int rtw_halmac_set_max_dl_fw_size(struct dvobj_priv *d, u32 size);
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int rtw_halmac_set_mac_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr);
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int rtw_halmac_set_bssid(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr);
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int rtw_halmac_set_tx_address(struct dvobj_priv *d, enum _hw_port hwport, u8 *addr);
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int rtw_halmac_set_network_type(struct dvobj_priv *d, enum _hw_port hwport, u8 type);
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int rtw_halmac_reset_tsf(struct dvobj_priv *d, enum _hw_port hwport);
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int rtw_halmac_set_bcn_interval(struct dvobj_priv *d, enum _hw_port hwport, u32 space);
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int rtw_halmac_set_bcn_ctrl(struct dvobj_priv *d, enum _hw_port hwport, struct rtw_halmac_bcn_ctrl *bcn_ctrl);
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int rtw_halmac_set_aid(struct dvobj_priv *d, enum _hw_port hwport, u16 aid);
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int rtw_halmac_set_bandwidth(struct dvobj_priv *d, u8 channel, u8 pri_ch_idx, u8 bw);
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int rtw_halmac_set_edca(struct dvobj_priv *d, u8 queue, u8 aifs, u8 cw, u16 txop);
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2019-05-24 19:43:57 +00:00
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int rtw_halmac_set_rts_full_bw(struct dvobj_priv *d, u8 enable);
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2018-06-22 16:48:32 +00:00
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/* Functions */
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int rtw_halmac_poweron(struct dvobj_priv *);
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int rtw_halmac_poweroff(struct dvobj_priv *);
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int rtw_halmac_init_hal(struct dvobj_priv *);
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int rtw_halmac_init_hal_fw(struct dvobj_priv *, u8 *fw, u32 fwsize);
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int rtw_halmac_init_hal_fw_file(struct dvobj_priv *, u8 *fwpath);
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int rtw_halmac_deinit_hal(struct dvobj_priv *);
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int rtw_halmac_self_verify(struct dvobj_priv *);
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int rtw_halmac_txfifo_wait_empty(struct dvobj_priv *d, u32 timeout);
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int rtw_halmac_dlfw(struct dvobj_priv *, u8 *fw, u32 fwsize);
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int rtw_halmac_dlfw_from_file(struct dvobj_priv *, u8 *fwpath);
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int rtw_halmac_dlfw_mem(struct dvobj_priv *d, u8 *fw, u32 fwsize, enum fw_mem mem);
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int rtw_halmac_dlfw_mem_from_file(struct dvobj_priv *d, u8 *fwpath, enum fw_mem mem);
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int rtw_halmac_phy_power_switch(struct dvobj_priv *, u8 enable);
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int rtw_halmac_send_h2c(struct dvobj_priv *, u8 *h2c);
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int rtw_halmac_c2h_handle(struct dvobj_priv *, u8 *c2h, u32 size);
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/* eFuse */
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int rtw_halmac_get_available_efuse_size(struct dvobj_priv *d, u32 *size);
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int rtw_halmac_get_physical_efuse_size(struct dvobj_priv *, u32 *size);
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int rtw_halmac_read_physical_efuse_map(struct dvobj_priv *, u8 *map, u32 size);
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int rtw_halmac_read_physical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data);
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int rtw_halmac_write_physical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data);
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int rtw_halmac_get_logical_efuse_size(struct dvobj_priv *, u32 *size);
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int rtw_halmac_read_logical_efuse_map(struct dvobj_priv *, u8 *map, u32 size, u8 *maskmap, u32 masksize);
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int rtw_halmac_write_logical_efuse_map(struct dvobj_priv *, u8 *map, u32 size, u8 *maskmap, u32 masksize);
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int rtw_halmac_read_logical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data);
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int rtw_halmac_write_logical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data);
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int rtw_halmac_write_bt_physical_efuse(struct dvobj_priv *, u32 offset, u32 cnt, u8 *data);
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int rtw_halmac_read_bt_physical_efuse_map(struct dvobj_priv *, u8 *map, u32 size);
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int rtw_halmac_dump_fifo(struct dvobj_priv *d, u8 fifo_sel, u32 addr, u32 size, u8 *buffer);
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int rtw_halmac_rx_agg_switch(struct dvobj_priv *, u8 enable);
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/* Specific function APIs*/
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int rtw_halmac_download_rsvd_page(struct dvobj_priv *dvobj, u8 pg_offset, u8 *pbuf, u32 size);
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int rtw_halmac_fill_hal_spec(struct dvobj_priv *, struct hal_spec_t *);
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int rtw_halmac_p2pps(struct dvobj_priv *dvobj, PHAL_P2P_PS_PARA pp2p_ps_para);
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int rtw_halmac_iqk(struct dvobj_priv *d, u8 clear, u8 segment);
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int rtw_halmac_cfg_phy_para(struct dvobj_priv *d, struct rtw_phy_parameter *para);
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2018-08-24 20:52:34 +00:00
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int rtw_halmac_led_cfg(struct dvobj_priv *d, u8 enable, u8 mode);
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void rtw_halmac_led_switch(struct dvobj_priv *d, u8 on);
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2019-05-24 19:43:57 +00:00
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int rtw_halmac_bt_wake_cfg(struct dvobj_priv *d, u8 enable);
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#ifdef CONFIG_PNO_SUPPORT
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int rtw_halmac_pno_scanoffload(struct dvobj_priv *d, u32 enable);
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#endif
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2018-06-22 16:48:32 +00:00
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#ifdef CONFIG_SDIO_HCI
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int rtw_halmac_query_tx_page_num(struct dvobj_priv *);
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int rtw_halmac_get_tx_queue_page_num(struct dvobj_priv *, u8 queue, u32 *page);
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u32 rtw_halmac_sdio_get_tx_addr(struct dvobj_priv *, u8 *desc, u32 size);
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int rtw_halmac_sdio_tx_allowed(struct dvobj_priv *, u8 *buf, u32 size);
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u32 rtw_halmac_sdio_get_rx_addr(struct dvobj_priv *, u8 *seq);
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#endif /* CONFIG_SDIO_HCI */
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#ifdef CONFIG_USB_HCI
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u8 rtw_halmac_usb_get_bulkout_id(struct dvobj_priv *, u8 *buf, u32 size);
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int rtw_halmac_usb_get_txagg_desc_num(struct dvobj_priv *d, u8 *num);
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u8 rtw_halmac_switch_usb_mode(struct dvobj_priv *d, enum RTW_USB_SPEED usb_mode);
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#endif /* CONFIG_USB_HCI */
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#ifdef CONFIG_SUPPORT_TRX_SHARED
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void dump_trx_share_mode(void *sel, _adapter *adapter);
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#endif
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2018-08-24 20:52:34 +00:00
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#ifdef CONFIG_BEAMFORMING
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#ifdef RTW_BEAMFORMING_VERSION_2
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int rtw_halmac_bf_add_mu_bfer(struct dvobj_priv *d, u16 paid, u16 csi_para,
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u16 my_aid, enum halmac_csi_seg_len sel, u8 *addr);
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int rtw_halmac_bf_del_mu_bfer(struct dvobj_priv *d);
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int rtw_halmac_bf_cfg_sounding(struct dvobj_priv *d, enum halmac_snd_role role,
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enum halmac_data_rate rate);
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int rtw_halmac_bf_del_sounding(struct dvobj_priv *d, enum halmac_snd_role role);
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int rtw_halmac_bf_cfg_csi_rate(struct dvobj_priv *d, u8 rssi, u8 current_rate,
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u8 fixrate_en, u8 *new_rate);
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int rtw_halmac_bf_cfg_mu_mimo(struct dvobj_priv *d, enum halmac_snd_role role,
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u8 *sounding_sts, u16 grouping_bitmap, u8 mu_tx_en,
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u32 *given_gid_tab, u32 *given_user_pos);
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#define rtw_halmac_bf_cfg_mu_bfee(d, gid_tab, user_pos) \
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rtw_halmac_bf_cfg_mu_mimo(d, HAL_BFEE, NULL, 0, 0, gid_tab, user_pos)
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#endif /* RTW_BEAMFORMING_VERSION_2 */
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#endif /* CONFIG_BEAMFORMING */
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2018-06-22 16:48:32 +00:00
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#endif /* _HAL_HALMAC_H_ */
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