mirror of
https://github.com/gnab/rtl8812au
synced 2024-11-27 07:34:24 +00:00
580 lines
18 KiB
C
580 lines
18 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*
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******************************************************************************/
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#define _RTL8812A_RF6052_C_
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//#include <drv_types.h>
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#include <rtl8812a_hal.h>
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/*-----------------------------------------------------------------------------
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* Function: PHY_RF6052SetBandwidth()
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*
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* Overview: This function is called by SetBWModeCallback8190Pci() only
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*
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* Input: PADAPTER Adapter
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* WIRELESS_BANDWIDTH_E Bandwidth //20M or 40M
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*
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* Output: NONE
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*
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* Return: NONE
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*
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* Note: For RF type 0222D
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*---------------------------------------------------------------------------*/
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VOID
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PHY_RF6052SetBandwidth8812(
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IN PADAPTER Adapter,
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IN CHANNEL_WIDTH Bandwidth) //20M or 40M
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{
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HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
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switch(Bandwidth)
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{
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case CHANNEL_WIDTH_20:
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//DBG_871X("PHY_RF6052SetBandwidth8812(), set 20MHz, pHalData->RfRegChnlVal[0] = 0x%x \n", pHalData->RfRegChnlVal[0]);
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PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW_Jaguar, BIT11|BIT10, 3);
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PHY_SetRFReg(Adapter, RF_PATH_B, RF_CHNLBW_Jaguar, BIT11|BIT10, 3);
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break;
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case CHANNEL_WIDTH_40:
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//DBG_871X("PHY_RF6052SetBandwidth8812(), set 40MHz, pHalData->RfRegChnlVal[0] = 0x%x \n", pHalData->RfRegChnlVal[0]);
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PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW_Jaguar, BIT11|BIT10, 1);
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PHY_SetRFReg(Adapter, RF_PATH_B, RF_CHNLBW_Jaguar, BIT11|BIT10, 1);
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break;
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case CHANNEL_WIDTH_80:
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//DBG_871X("PHY_RF6052SetBandwidth8812(), set 80MHz, pHalData->RfRegChnlVal[0] = 0x%x \n", pHalData->RfRegChnlVal[0]);
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PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW_Jaguar, BIT11|BIT10, 0);
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PHY_SetRFReg(Adapter, RF_PATH_B, RF_CHNLBW_Jaguar, BIT11|BIT10, 0);
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break;
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default:
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DBG_871X("PHY_RF6052SetBandwidth8812(): unknown Bandwidth: %#X\n",Bandwidth );
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break;
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}
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}
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//
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// powerbase0 for OFDM rates
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// powerbase1 for HT MCS rates
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//
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void getPowerBase8812(
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IN PADAPTER Adapter,
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IN u8* pPowerLevelOFDM,
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IN u8* pPowerLevelBW20,
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IN u8* pPowerLevelBW40,
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IN u8 Channel,
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IN OUT u32* OfdmBase,
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IN OUT u32* MCSBase
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)
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{
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HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
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u32 powerBase0, powerBase1;
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u8 i, powerlevel[2];
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for(i=0; i<2; i++)
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{
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powerBase0 = pPowerLevelOFDM[i];
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powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0;
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*(OfdmBase+i) = powerBase0;
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//DBG_871X(" [OFDM power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(OfdmBase+i));
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}
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for(i=0; i<pHalData->NumTotalRFPath; i++)
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{
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//Check HT20 to HT40 diff
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if(pHalData->CurrentChannelBW == CHANNEL_WIDTH_20)
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{
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powerlevel[i] = pPowerLevelBW20[i];
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}
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else
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{
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powerlevel[i] = pPowerLevelBW40[i];
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}
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powerBase1 = powerlevel[i];
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powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1;
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*(MCSBase+i) = powerBase1;
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//DBG_871X(" [MCS power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(MCSBase+i));
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}
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}
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void getTxPowerWriteValByRegulatory8812(
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IN PADAPTER Adapter,
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IN u8 Channel,
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IN u8 index,
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IN u32* powerBase0,
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IN u32* powerBase1,
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OUT u32* pOutWriteVal
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)
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{
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HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
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struct dm_priv *pdmpriv = &pHalData->dmpriv;
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u8 i, chnlGroup=0, pwr_diff_limit[4], customer_pwr_limit;
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s8 pwr_diff=0;
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u32 writeVal, customer_limit, rf;
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u8 Regulatory = pHalData->EEPROMRegulatory;
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//
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// Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate
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//
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#if 0 // (INTEL_PROXIMITY_SUPPORT == 1)
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if(pMgntInfo->IntelProximityModeInfo.PowerOutput > 0)
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Regulatory = 2;
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#endif
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for(rf=0; rf<2; rf++)
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{
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switch(Regulatory)
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{
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case 0: // Realtek better performance
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// increase power diff defined by Realtek for large power
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chnlGroup = 0;
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//RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
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// chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]));
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writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
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((index<2)?powerBase0[rf]:powerBase1[rf]);
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//RTPRINT(FPHY, PHY_TXPWR, ("RTK better performance, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
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break;
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case 1: // Realtek regulatory
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// increase power diff defined by Realtek for regulatory
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{
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if(pHalData->pwrGroupCnt == 1)
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chnlGroup = 0;
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//if(pHalData->pwrGroupCnt >= pHalData->PGMaxGroup)
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{
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if (Channel < 3) // Chanel 1-2
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chnlGroup = 0;
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else if (Channel < 6) // Channel 3-5
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chnlGroup = 1;
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else if(Channel <9) // Channel 6-8
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chnlGroup = 2;
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else if(Channel <12) // Channel 9-11
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chnlGroup = 3;
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else if(Channel <14) // Channel 12-13
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chnlGroup = 4;
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else if(Channel ==14) // Channel 14
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chnlGroup = 5;
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/*
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if(Channel <= 3)
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chnlGroup = 0;
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else if(Channel >= 4 && Channel <= 9)
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chnlGroup = 1;
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else if(Channel > 9)
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chnlGroup = 2;
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if(pHalData->CurrentChannelBW == CHANNEL_WIDTH_20)
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chnlGroup++;
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else
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chnlGroup+=4;
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*/
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}
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//RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
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//chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]));
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writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
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((index<2)?powerBase0[rf]:powerBase1[rf]);
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//RTPRINT(FPHY, PHY_TXPWR, ("Realtek regulatory, 20MHz, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
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}
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break;
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case 2: // Better regulatory
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// don't increase any power diff
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writeVal = ((index<2)?powerBase0[rf]:powerBase1[rf]);
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//RTPRINT(FPHY, PHY_TXPWR, ("Better regulatory, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
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break;
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case 3: // Customer defined power diff.
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// increase power diff defined by customer.
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chnlGroup = 0;
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//RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
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// chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]));
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/*
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if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_40)
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{
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RTPRINT(FPHY, PHY_TXPWR, ("customer's limit, 40MHz rf(%c) = 0x%x\n",
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((rf==0)?'A':'B'), pHalData->PwrGroupHT40[rf][Channel-1]));
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}
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else
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{
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RTPRINT(FPHY, PHY_TXPWR, ("customer's limit, 20MHz rf(%c) = 0x%x\n",
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((rf==0)?'A':'B'), pHalData->PwrGroupHT20[rf][Channel-1]));
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}*/
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if(index < 2)
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pwr_diff = pHalData->TxPwrLegacyHtDiff[rf][Channel-1];
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else if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_20)
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pwr_diff = pHalData->TxPwrHt20Diff[rf][Channel-1];
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//RTPRINT(FPHY, PHY_TXPWR, ("power diff rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), pwr_diff));
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if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_40)
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customer_pwr_limit = pHalData->PwrGroupHT40[rf][Channel-1];
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else
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customer_pwr_limit = pHalData->PwrGroupHT20[rf][Channel-1];
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//RTPRINT(FPHY, PHY_TXPWR, ("customer pwr limit rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), customer_pwr_limit));
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if(pwr_diff >= customer_pwr_limit)
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pwr_diff = 0;
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else
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pwr_diff = customer_pwr_limit - pwr_diff;
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for (i=0; i<4; i++)
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{
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pwr_diff_limit[i] = (u1Byte)((pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]&(0x7f<<(i*8)))>>(i*8));
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if(pwr_diff_limit[i] > pwr_diff)
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pwr_diff_limit[i] = pwr_diff;
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}
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customer_limit = (pwr_diff_limit[3]<<24) | (pwr_diff_limit[2]<<16) |
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(pwr_diff_limit[1]<<8) | (pwr_diff_limit[0]);
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//RTPRINT(FPHY, PHY_TXPWR, ("Customer's limit rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), customer_limit));
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writeVal = customer_limit + ((index<2)?powerBase0[rf]:powerBase1[rf]);
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//RTPRINT(FPHY, PHY_TXPWR, ("Customer, writeVal rf(%c)= 0x%x\n", ((rf==0)?'A':'B'), writeVal));
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break;
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default:
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chnlGroup = 0;
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writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
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((index<2)?powerBase0[rf]:powerBase1[rf]);
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//RTPRINT(FPHY, PHY_TXPWR, ("RTK better performance, writeVal rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
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break;
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}
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// 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism.
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// Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism.
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// In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder.
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//92d do not need this
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if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
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writeVal = 0x14141414;
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else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)
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writeVal = 0x00000000;
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// 20100628 Joseph: High power mode for BT-Coexist mechanism.
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// This mechanism is only applied when Driver-Highpower-Mechanism is OFF.
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if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT1)
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{
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//RTPRINT(FBT, BT_TRACE, ("Tx Power (-6)\n"));
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writeVal = writeVal - 0x06060606;
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}
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else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT2)
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{
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//RTPRINT(FBT, BT_TRACE, ("Tx Power (-0)\n"));
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writeVal = writeVal ;
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}
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/*
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if(pMgntInfo->bDisableTXPowerByRate)
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{
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// add for OID_RT_11N_TX_POWER_BY_RATE ,disable tx powre change by rate
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writeVal = 0x2c2c2c2c;
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}
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*/
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*(pOutWriteVal+rf) = writeVal;
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}
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}
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static void writeOFDMPowerReg8812(
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IN PADAPTER Adapter,
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IN u8 index,
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IN u32* pValue
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)
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{
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HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
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u2Byte RegOffset_A[6] = {
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rTxAGC_A_Ofdm18_Ofdm6_JAguar,
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rTxAGC_A_Ofdm54_Ofdm24_JAguar,
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rTxAGC_A_MCS3_MCS0_JAguar,
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rTxAGC_A_MCS7_MCS4_JAguar,
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rTxAGC_A_MCS11_MCS8_JAguar,
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rTxAGC_A_MCS15_MCS12_JAguar
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};
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u2Byte RegOffset_B[6] = {
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rTxAGC_B_Ofdm18_Ofdm6_JAguar,
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rTxAGC_B_Ofdm54_Ofdm24_JAguar,
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rTxAGC_B_MCS3_MCS0_JAguar,
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rTxAGC_B_MCS7_MCS4_JAguar,
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rTxAGC_B_MCS11_MCS8_JAguar,
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rTxAGC_B_MCS15_MCS12_JAguar
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};
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u8 i, rf, pwr_val[4];
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u32 writeVal;
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u16 RegOffset;
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for(rf=0; rf<2; rf++)
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{
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writeVal = pValue[rf];
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for(i=0; i<RF_PATH_MAX_92C_88E; i++)
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{
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pwr_val[i] = (u8)((writeVal & (0x7f<<(i*8)))>>(i*8));
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if (pwr_val[i] > RF6052_MAX_TX_PWR)
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pwr_val[i] = RF6052_MAX_TX_PWR;
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}
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writeVal = (pwr_val[3]<<24) | (pwr_val[2]<<16) |(pwr_val[1]<<8) |pwr_val[0];
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if(rf == 0)
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RegOffset = RegOffset_A[index];
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else
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RegOffset = RegOffset_B[index];
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PHY_SetBBReg(Adapter, RegOffset, bMaskDWord, writeVal);
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//RTPRINT(FPHY, PHY_TXPWR, ("Set 0x%x = %08x\n", RegOffset, writeVal));
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}
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}
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VOID
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PHY_RF6052SetCckTxPower8812(
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IN PADAPTER Adapter,
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IN u8* pPowerlevel)
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{
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HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
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struct dm_priv *pdmpriv = &pHalData->dmpriv;
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struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
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u32 TxAGC[2]={0, 0}, tmpval=0;
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BOOLEAN TurboScanOff = _FALSE;
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u8 idx1, idx2;
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u8* ptr;
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//FOR CE ,must disable turbo scan
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TurboScanOff = _TRUE;
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if(pmlmeext->sitesurvey_res.state == SCAN_PROCESS)
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{
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TxAGC[RF_PATH_A] = 0x3f3f3f3f;
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TxAGC[RF_PATH_B] = 0x3f3f3f3f;
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TurboScanOff = _TRUE;//disable turbo scan
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if(TurboScanOff)
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{
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for(idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++)
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{
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TxAGC[idx1] =
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pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) |
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(pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24);
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#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
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// 2010/10/18 MH For external PA module. We need to limit power index to be less than 0x20.
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if (TxAGC[idx1] > 0x20 && pHalData->ExternalPA_5G)
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TxAGC[idx1] = 0x20;
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#endif
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}
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}
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}
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else
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{
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// 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism.
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// Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism.
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// In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder.
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if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
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{
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TxAGC[RF_PATH_A] = 0x10101010;
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TxAGC[RF_PATH_B] = 0x10101010;
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}
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else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)
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{
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TxAGC[RF_PATH_A] = 0x00000000;
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TxAGC[RF_PATH_B] = 0x00000000;
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}
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else
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{
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for(idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++)
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{
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TxAGC[idx1] =
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pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) |
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(pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24);
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}
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if(pHalData->EEPROMRegulatory==0)
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{
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tmpval = (pHalData->MCSTxPowerLevelOriginalOffset[0][6]) +
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(pHalData->MCSTxPowerLevelOriginalOffset[0][7]<<8);
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TxAGC[RF_PATH_A] += tmpval;
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tmpval = (pHalData->MCSTxPowerLevelOriginalOffset[0][14]) +
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(pHalData->MCSTxPowerLevelOriginalOffset[0][15]<<24);
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TxAGC[RF_PATH_B] += tmpval;
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}
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}
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}
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for(idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++)
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{
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ptr = (u8*)(&(TxAGC[idx1]));
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for(idx2=0; idx2<4; idx2++)
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{
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if(*ptr > RF6052_MAX_TX_PWR)
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*ptr = RF6052_MAX_TX_PWR;
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ptr++;
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}
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}
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// rf-A cck tx power
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|
tmpval = TxAGC[RF_PATH_A]&0xff;
|
|
PHY_SetBBReg(Adapter, rTxAGC_A_CCK11_CCK1_JAguar, bMaskByte1, tmpval);
|
|
//RT_DISP(FPHY, PHY_TXPWR, ("CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_A_CCK1_Mcs32));
|
|
tmpval = TxAGC[RF_PATH_A]>>8;
|
|
PHY_SetBBReg(Adapter, rTxAGC_A_CCK11_CCK1_JAguar, 0xffffff00, tmpval);
|
|
//RT_DISP(FPHY, PHY_TXPWR, ("CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_B_CCK11_A_CCK2_11));
|
|
|
|
// rf-B cck tx power
|
|
tmpval = TxAGC[RF_PATH_B]>>24;
|
|
PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_CCK1_JAguar, bMaskByte0, tmpval);
|
|
//RT_DISP(FPHY, PHY_TXPWR, ("CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_B_CCK11_A_CCK2_11));
|
|
tmpval = TxAGC[RF_PATH_B]&0x00ffffff;
|
|
PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_CCK1_JAguar, 0xffffff00, tmpval);
|
|
//RT_DISP(FPHY, PHY_TXPWR, ("CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_B_CCK1_55_Mcs32));
|
|
|
|
} /* PHY_RF6052SetCckTxPower */
|
|
|
|
VOID
|
|
PHY_RF6052SetOFDMTxPower8812(
|
|
IN PADAPTER Adapter,
|
|
IN u8* pPowerLevelOFDM,
|
|
IN u8* pPowerLevelBW20,
|
|
IN u8* pPowerLevelBW40,
|
|
IN u8 Channel)
|
|
{
|
|
u32 writeVal[2], powerBase0[2], powerBase1[2], pwrtrac_value;
|
|
u8 index = 0;
|
|
|
|
|
|
//DBG_871X("PHY_RF6052SetOFDMTxPower, channel(%d) \n", Channel);
|
|
|
|
getPowerBase8812(Adapter, pPowerLevelOFDM,pPowerLevelBW20,pPowerLevelBW40, Channel, &powerBase0[0], &powerBase1[0]);
|
|
|
|
for(index=0; index<6; index++)
|
|
{
|
|
getTxPowerWriteValByRegulatory8812(Adapter, Channel, index,
|
|
&powerBase0[0], &powerBase1[0], &writeVal[0]);
|
|
|
|
writeOFDMPowerReg8812(Adapter, index, &writeVal[0]);
|
|
}
|
|
}
|
|
|
|
static int
|
|
phy_RF6052_Config_ParaFile_8812(
|
|
IN PADAPTER Adapter
|
|
)
|
|
{
|
|
u8 eRFPath;
|
|
int rtStatus = _SUCCESS;
|
|
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
|
|
static char sz8812RadioAFile[] = RTL8812_PHY_RADIO_A;
|
|
static char sz8812RadioBFile[] = RTL8812_PHY_RADIO_B;
|
|
static char sz8812TxPwrTrack[] = RTL8812_TXPWR_TRACK;
|
|
static char sz8821RadioAFile[] = RTL8821_PHY_RADIO_A;
|
|
static char sz8821RadioBFile[] = RTL8821_PHY_RADIO_B;
|
|
static char sz8821TxPwrTrack[] = RTL8821_TXPWR_TRACK;
|
|
char *pszRadioAFile = NULL, *pszRadioBFile = NULL, *pszTxPwrTrack = NULL;
|
|
|
|
|
|
if(IS_HARDWARE_TYPE_8812(Adapter))
|
|
{
|
|
pszRadioAFile = sz8812RadioAFile;
|
|
pszRadioBFile = sz8812RadioBFile;
|
|
pszTxPwrTrack = sz8812TxPwrTrack;
|
|
}
|
|
else
|
|
{
|
|
pszRadioAFile = sz8821RadioAFile;
|
|
pszRadioBFile = sz8821RadioBFile;
|
|
pszTxPwrTrack = sz8821TxPwrTrack;
|
|
}
|
|
|
|
|
|
//3//-----------------------------------------------------------------
|
|
//3// <2> Initialize RF
|
|
//3//-----------------------------------------------------------------
|
|
//for(eRFPath = RF_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
|
|
for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
|
|
{
|
|
/*----Initialize RF fom connfiguration file----*/
|
|
switch(eRFPath)
|
|
{
|
|
case RF_PATH_A:
|
|
#ifdef CONFIG_EMBEDDED_FWIMG
|
|
if(HAL_STATUS_FAILURE ==ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv,CONFIG_RF_RADIO, (ODM_RF_RADIO_PATH_E)eRFPath))
|
|
rtStatus= _FAIL;
|
|
#else
|
|
rtStatus = PHY_ConfigRFWithParaFile(Adapter, pszRadioAFile, eRFPath);
|
|
#endif//#ifdef CONFIG_EMBEDDED_FWIMG
|
|
break;
|
|
case RF_PATH_B:
|
|
#ifdef CONFIG_EMBEDDED_FWIMG
|
|
if(HAL_STATUS_FAILURE ==ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv,CONFIG_RF_RADIO, (ODM_RF_RADIO_PATH_E)eRFPath))
|
|
rtStatus= _FAIL;
|
|
#else
|
|
rtStatus =PHY_ConfigRFWithParaFile(Adapter, pszRadioBFile, eRFPath);
|
|
#endif
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
if(rtStatus != _SUCCESS){
|
|
DBG_871X("%s():Radio[%d] Fail!!", __FUNCTION__, eRFPath);
|
|
goto phy_RF6052_Config_ParaFile_Fail;
|
|
}
|
|
|
|
}
|
|
|
|
//3 -----------------------------------------------------------------
|
|
//3 Configuration of Tx Power Tracking
|
|
//3 -----------------------------------------------------------------
|
|
|
|
#ifdef CONFIG_EMBEDDED_FWIMG
|
|
ODM_ConfigRFWithTxPwrTrackHeaderFile(&pHalData->odmpriv);
|
|
#else
|
|
PHY_ConfigRFWithTxPwrTrackParaFile(Adapter, pszTxPwrTrack);
|
|
#endif
|
|
|
|
//RT_TRACE(COMP_INIT, DBG_LOUD, ("<---phy_RF6052_Config_ParaFile_8812()\n"));
|
|
|
|
phy_RF6052_Config_ParaFile_Fail:
|
|
return rtStatus;
|
|
}
|
|
|
|
|
|
int
|
|
PHY_RF6052_Config_8812(
|
|
IN PADAPTER Adapter)
|
|
{
|
|
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
|
|
int rtStatus = _SUCCESS;
|
|
|
|
// Initialize general global value
|
|
if(pHalData->rf_type == RF_1T1R)
|
|
pHalData->NumTotalRFPath = 1;
|
|
else
|
|
pHalData->NumTotalRFPath = 2;
|
|
|
|
//
|
|
// Config BB and RF
|
|
//
|
|
rtStatus = phy_RF6052_Config_ParaFile_8812(Adapter);
|
|
|
|
return rtStatus;
|
|
|
|
}
|
|
|
|
|
|
/* End of HalRf6052.c */
|
|
|