mirror of
https://github.com/gnab/rtl8812au
synced 2024-10-18 13:02:05 +00:00
411 lines
16 KiB
C
411 lines
16 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*
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******************************************************************************/
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#ifndef __RTL8192D_HAL_H__
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#define __RTL8192D_HAL_H__
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//#include "hal_com.h"
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#if 1
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#include "hal_data.h"
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#else
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#include "../hal/OUTSRC/odm_precomp.h"
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#endif
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#include "rtl8192d_spec.h"
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#include "Hal8192DPhyReg.h"
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#include "Hal8192DPhyCfg.h"
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#include "rtl8192d_rf.h"
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#include "rtl8192d_dm.h"
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#include "rtl8192d_recv.h"
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#include "rtl8192d_xmit.h"
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#include "rtl8192d_cmd.h"
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#include "rtl8192d_led.h"
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#ifdef CONFIG_PCI_HCI
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#define RTL819X_DEFAULT_RF_TYPE RF_2T2R
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//---------------------------------------------------------------------
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// RTL8192DE From file
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//---------------------------------------------------------------------
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#define RTL8192D_FW_IMG "rtl8192DE\\rtl8192dfw.bin"
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#define RTL8192D_PHY_REG "rtl8192DE\\PHY_REG.txt"
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#define RTL8192D_PHY_REG_PG "rtl8192DE\\PHY_REG_PG.txt"
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#define RTL8192D_PHY_REG_MP "rtl8192DE\\PHY_REG_MP.txt"
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#define RTL8192D_AGC_TAB "rtl8192DE\\AGC_TAB.txt"
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#define RTL8192D_AGC_TAB_2G "rtl8192DE\\AGC_TAB_2G.txt"
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#define RTL8192D_AGC_TAB_5G "rtl8192DE\\AGC_TAB_5G.txt"
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#define RTL8192D_PHY_RADIO_A "rtl8192DE\\radio_a.txt"
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#define RTL8192D_PHY_RADIO_B "rtl8192DE\\radio_b.txt"
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#define RTL8192D_PHY_RADIO_A_intPA "rtl8192DE\\radio_a_intPA.txt"
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#define RTL8192D_PHY_RADIO_B_intPA "rtl8192DE\\radio_b_intPA.txt"
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#define RTL8192D_PHY_MACREG "rtl8192DE\\MAC_REG.txt"
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//---------------------------------------------------------------------
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// RTL8192DE From header
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//---------------------------------------------------------------------
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// Fw Array
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#define Rtl8192D_FwImageArray Rtl8192DEFwImgArray
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// MAC/BB/PHY Array
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#define Rtl8192D_MAC_Array Rtl8192DEMAC_2T_Array
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#define Rtl8192D_AGCTAB_Array Rtl8192DEAGCTAB_Array
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#define Rtl8192D_AGCTAB_5GArray Rtl8192DEAGCTAB_5GArray
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#define Rtl8192D_AGCTAB_2GArray Rtl8192DEAGCTAB_2GArray
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#define Rtl8192D_AGCTAB_2TArray Rtl8192DEAGCTAB_2TArray
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#define Rtl8192D_AGCTAB_1TArray Rtl8192DEAGCTAB_1TArray
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#define Rtl8192D_PHY_REG_2TArray Rtl8192DEPHY_REG_2TArray
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#define Rtl8192D_PHY_REG_1TArray Rtl8192DEPHY_REG_1TArray
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#define Rtl8192D_PHY_REG_Array_PG Rtl8192DEPHY_REG_Array_PG
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#define Rtl8192D_PHY_REG_Array_MP Rtl8192DEPHY_REG_Array_MP
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#define Rtl8192D_RadioA_2TArray Rtl8192DERadioA_2TArray
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#define Rtl8192D_RadioA_1TArray Rtl8192DERadioA_1TArray
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#define Rtl8192D_RadioB_2TArray Rtl8192DERadioB_2TArray
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#define Rtl8192D_RadioB_1TArray Rtl8192DERadioB_1TArray
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#define Rtl8192D_RadioA_2T_intPAArray Rtl8192DERadioA_2T_intPAArray
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#define Rtl8192D_RadioB_2T_intPAArray Rtl8192DERadioB_2T_intPAArray
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// Array length
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#define Rtl8192D_FwImageArrayLength Rtl8192DEImgArrayLength
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#define Rtl8192D_MAC_ArrayLength Rtl8192DEMAC_2T_ArrayLength
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#define Rtl8192D_AGCTAB_5GArrayLength Rtl8192DEAGCTAB_5GArrayLength
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#define Rtl8192D_AGCTAB_2GArrayLength Rtl8192DEAGCTAB_2GArrayLength
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#define Rtl8192D_AGCTAB_2TArrayLength Rtl8192DEAGCTAB_2TArrayLength
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#define Rtl8192D_AGCTAB_1TArrayLength Rtl8192DEAGCTAB_1TArrayLength
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#define Rtl8192D_AGCTAB_ArrayLength Rtl8192DEAGCTAB_ArrayLength
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#define Rtl8192D_PHY_REG_2TArrayLength Rtl8192DEPHY_REG_2TArrayLength
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#define Rtl8192D_PHY_REG_1TArrayLength Rtl8192DEPHY_REG_1TArrayLength
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#define Rtl8192D_PHY_REG_Array_PGLength Rtl8192DEPHY_REG_Array_PGLength
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#define Rtl8192D_PHY_REG_Array_MPLength Rtl8192DEPHY_REG_Array_MPLength
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#define Rtl8192D_RadioA_2TArrayLength Rtl8192DERadioA_2TArrayLength
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#define Rtl8192D_RadioB_2TArrayLength Rtl8192DERadioB_2TArrayLength
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#define Rtl8192D_RadioA_2T_intPAArrayLength Rtl8192DERadioA_2T_intPAArrayLength
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#define Rtl8192D_RadioB_2T_intPAArrayLength Rtl8192DERadioB_2T_intPAArrayLength
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#elif defined(CONFIG_USB_HCI)
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#define RTL819X_DEFAULT_RF_TYPE RF_1T2R
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//---------------------------------------------------------------------
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// RTL8192DU From file
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//---------------------------------------------------------------------
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#define RTL8192D_FW_IMG "rtl8192DU\\rtl8192dfw.bin"
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#define RTL8192D_PHY_REG "rtl8192DU\\PHY_REG.txt"
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#define RTL8192D_PHY_REG_PG "rtl8192DU\\PHY_REG_PG.txt"
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#define RTL8192D_PHY_REG_MP "rtl8192DU\\PHY_REG_MP.txt"
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#define RTL8192D_AGC_TAB "rtl8192DU\\AGC_TAB.txt"
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#define RTL8192D_AGC_TAB_2G "rtl8192DU\\AGC_TAB_2G.txt"
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#define RTL8192D_AGC_TAB_5G "rtl8192DU\\AGC_TAB_5G.txt"
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#define RTL8192D_PHY_RADIO_A "rtl8192DU\\radio_a.txt"
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#define RTL8192D_PHY_RADIO_B "rtl8192DU\\radio_b.txt"
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#define RTL8192D_PHY_RADIO_A_intPA "rtl8192DU\\radio_a_intPA.txt"
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#define RTL8192D_PHY_RADIO_B_intPA "rtl8192DU\\radio_b_intPA.txt"
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#define RTL8192D_PHY_MACREG "rtl8192DU\\MAC_REG.txt"
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//---------------------------------------------------------------------
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// RTL8192DU From header
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//---------------------------------------------------------------------
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// Fw Array
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#define Rtl8192D_FwImageArray Rtl8192DUFwImgArray
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// MAC/BB/PHY Array
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#define Rtl8192D_MAC_Array Rtl8192DUMAC_2T_Array
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#define Rtl8192D_AGCTAB_Array Rtl8192DUAGCTAB_Array
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#define Rtl8192D_AGCTAB_5GArray Rtl8192DUAGCTAB_5GArray
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#define Rtl8192D_AGCTAB_2GArray Rtl8192DUAGCTAB_2GArray
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#define Rtl8192D_AGCTAB_2TArray Rtl8192DUAGCTAB_2TArray
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#define Rtl8192D_AGCTAB_1TArray Rtl8192DUAGCTAB_1TArray
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#define Rtl8192D_PHY_REG_2TArray Rtl8192DUPHY_REG_2TArray
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#define Rtl8192D_PHY_REG_1TArray Rtl8192DUPHY_REG_1TArray
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#define Rtl8192D_PHY_REG_Array_PG Rtl8192DUPHY_REG_Array_PG
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#define Rtl8192D_PHY_REG_Array_MP Rtl8192DUPHY_REG_Array_MP
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#define Rtl8192D_RadioA_2TArray Rtl8192DURadioA_2TArray
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#define Rtl8192D_RadioA_1TArray Rtl8192DURadioA_1TArray
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#define Rtl8192D_RadioB_2TArray Rtl8192DURadioB_2TArray
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#define Rtl8192D_RadioB_1TArray Rtl8192DURadioB_1TArray
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#define Rtl8192D_RadioA_2T_intPAArray Rtl8192DURadioA_2T_intPAArray
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#define Rtl8192D_RadioB_2T_intPAArray Rtl8192DURadioB_2T_intPAArray
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// Array length
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#define Rtl8192D_FwImageArrayLength Rtl8192DUImgArrayLength
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#define Rtl8192D_MAC_ArrayLength Rtl8192DUMAC_2T_ArrayLength
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#define Rtl8192D_AGCTAB_5GArrayLength Rtl8192DUAGCTAB_5GArrayLength
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#define Rtl8192D_AGCTAB_2GArrayLength Rtl8192DUAGCTAB_2GArrayLength
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#define Rtl8192D_AGCTAB_2TArrayLength Rtl8192DUAGCTAB_2TArrayLength
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#define Rtl8192D_AGCTAB_1TArrayLength Rtl8192DUAGCTAB_1TArrayLength
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#define Rtl8192D_AGCTAB_ArrayLength Rtl8192DUAGCTAB_ArrayLength
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#define Rtl8192D_PHY_REG_2TArrayLength Rtl8192DUPHY_REG_2TArrayLength
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#define Rtl8192D_PHY_REG_1TArrayLength Rtl8192DUPHY_REG_1TArrayLength
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#define Rtl8192D_PHY_REG_Array_PGLength Rtl8192DUPHY_REG_Array_PGLength
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#define Rtl8192D_PHY_REG_Array_MPLength Rtl8192DUPHY_REG_Array_MPLength
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#define Rtl8192D_RadioA_2TArrayLength Rtl8192DURadioA_2TArrayLength
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#define Rtl8192D_RadioB_2TArrayLength Rtl8192DURadioB_2TArrayLength
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#define Rtl8192D_RadioA_2T_intPAArrayLength Rtl8192DURadioA_2T_intPAArrayLength
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#define Rtl8192D_RadioB_2T_intPAArrayLength Rtl8192DURadioB_2T_intPAArrayLength
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// The file name "_2T" is for 92CU, "_1T" is for 88CU. Modified by tynli. 2009.11.24.
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/* #define Rtl819XFwImageArray Rtl8192DUFwImgArray
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#define Rtl819XMAC_Array Rtl8192DUMAC_2TArray
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#define Rtl819XAGCTAB_Array Rtl8192DUAGCTAB_Array
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#define Rtl819XAGCTAB_5GArray Rtl8192DUAGCTAB_5GArray
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#define Rtl819XAGCTAB_2GArray Rtl8192DUAGCTAB_2GArray
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#define Rtl819XPHY_REG_2TArray Rtl8192DUPHY_REG_2TArray
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#define Rtl819XPHY_REG_1TArray Rtl8192DUPHY_REG_1TArray
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#define Rtl819XRadioA_2TArray Rtl8192DURadioA_2TArray
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#define Rtl819XRadioA_1TArray Rtl8192DURadioA_1TArray
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#define Rtl819XRadioA_2T_intPAArray Rtl8192DURadioA_2T_intPAArray
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#define Rtl819XRadioB_2TArray Rtl8192DURadioB_2TArray
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#define Rtl819XRadioB_1TArray Rtl8192DURadioB_1TArray
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#define Rtl819XRadioB_2T_intPAArray Rtl8192DURadioB_2T_intPAArray
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#define Rtl819XPHY_REG_Array_PG Rtl8192DUPHY_REG_Array_PG
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#define Rtl819XPHY_REG_Array_MP Rtl8192DUPHY_REG_Array_MP
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#define Rtl819XAGCTAB_2TArray Rtl8192DUAGCTAB_2TArray
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#define Rtl819XAGCTAB_1TArray Rtl8192DUAGCTAB_1TArray*/
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#endif
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//
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// Check if FW header exists. We do not consider the lower 4 bits in this case.
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// By tynli. 2009.12.04.
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//
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#define IS_FW_HEADER_EXIST_92D(_pFwHdr) ((le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x92C0 ||\
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(le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88C0 ||\
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(le16_to_cpu(_pFwHdr->Signature)&0xFFFF) == 0x92D0 ||\
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(le16_to_cpu(_pFwHdr->Signature)&0xFFFF) == 0x92D1 ||\
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(le16_to_cpu(_pFwHdr->Signature)&0xFFFF) == 0x92D2 ||\
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(le16_to_cpu(_pFwHdr->Signature)&0xFFFF) == 0x92D3 )
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#define FW_8192D_SIZE 0x8020 // Max FW len = 32k + 32(FW header length).
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#define FW_8192D_START_ADDRESS 0x1000
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#define FW_8192D_END_ADDRESS 0x1FFF
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typedef struct _RT_FIRMWARE_8192D{
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FIRMWARE_SOURCE eFWSource;
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u8* szFwBuffer;
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u32 ulFwLength;
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} RT_FIRMWARE_8192D, *PRT_FIRMWARE_8192D;
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//
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// This structure must be cared byte-ordering
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//
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// Added by tynli. 2009.12.04.
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typedef struct _RT_8192D_FIRMWARE_HDR {//8-byte alinment required
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//--- LONG WORD 0 ----
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u16 Signature; // 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut
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u8 Category; // AP/NIC and USB/PCI
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u8 Function; // Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions
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u16 Version; // FW Version
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u8 Subversion; // FW Subversion, default 0x00
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u8 Rsvd1;
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//--- LONG WORD 1 ----
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u8 Month; // Release time Month field
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u8 Date; // Release time Date field
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u8 Hour; // Release time Hour field
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u8 Minute; // Release time Minute field
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u16 RamCodeSize; // The size of RAM code
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u16 Rsvd2;
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//--- LONG WORD 2 ----
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u32 SvnIdx; // The SVN entry index
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u32 Rsvd3;
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//--- LONG WORD 3 ----
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u32 Rsvd4;
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u32 Rsvd5;
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}RT_8192D_FIRMWARE_HDR, *PRT_8192D_FIRMWARE_HDR;
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#define DRIVER_EARLY_INT_TIME_8192D 0x05
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#define BCN_DMA_ATIME_INT_TIME_8192D 0x02
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typedef enum _BT_CurState{
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BT_OFF = 0,
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BT_ON = 1,
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} BT_CurState, *PBT_CurState;
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typedef enum _BT_ServiceType{
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BT_SCO = 0,
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BT_A2DP = 1,
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BT_HID = 2,
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BT_HID_Idle = 3,
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BT_Scan = 4,
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BT_Idle = 5,
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BT_OtherAction = 6,
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BT_Busy = 7,
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BT_OtherBusy = 8,
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} BT_ServiceType, *PBT_ServiceType;
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typedef struct _BT_COEXIST_STR{
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u8 BluetoothCoexist;
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u8 BT_Ant_Num;
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u8 BT_CoexistType;
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u8 BT_State;
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u8 BT_CUR_State; //0:on, 1:off
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u8 BT_Ant_isolation; //0:good, 1:bad
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u8 BT_PapeCtrl; //0:SW, 1:SW/HW dynamic
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u8 BT_Service;
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u8 BT_RadioSharedType;
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u8 Ratio_Tx;
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u8 Ratio_PRI;
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}BT_COEXIST_STR, *PBT_COEXIST_STR;
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// Note: We will divide number of page equally for each queue other than public queue!
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#define TX_TOTAL_PAGE_NUMBER_8192D 0xF8
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#define TX_PAGE_BOUNDARY (TX_TOTAL_PAGE_NUMBER_8192D + 1)
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// For Normal Chip Setting
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// (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8192D
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#define NORMAL_PAGE_NUM_PUBQ 0x56
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// For Test Chip Setting
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// (HPQ + LPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8192D
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#define TEST_PAGE_NUM_PUBQ 0x89
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#define TX_TOTAL_PAGE_NUMBER_92D_DUAL_MAC 0x7A
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#define NORMAL_PAGE_NUM_PUBQ_92D_DUAL_MAC 0x5A
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#define NORMAL_PAGE_NUM_HPQ_92D_DUAL_MAC 0x10
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#define NORMAL_PAGE_NUM_LPQ_92D_DUAL_MAC 0x10
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#define NORMAL_PAGE_NUM_NORMALQ_92D_DUAL_MAC 0
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#define TX_PAGE_BOUNDARY_DUAL_MAC (TX_TOTAL_PAGE_NUMBER_92D_DUAL_MAC + 1)
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// For Test Chip Setting
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#define WMM_TEST_TX_TOTAL_PAGE_NUMBER 0xF5
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#define WMM_TEST_TX_PAGE_BOUNDARY (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) //F6
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#define WMM_TEST_PAGE_NUM_PUBQ 0xA3
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#define WMM_TEST_PAGE_NUM_HPQ 0x29
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#define WMM_TEST_PAGE_NUM_LPQ 0x29
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//Note: For Normal Chip Setting ,modify later
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#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER 0xF5
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#define WMM_NORMAL_TX_PAGE_BOUNDARY (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) //F6
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#define WMM_NORMAL_PAGE_NUM_PUBQ 0xB0
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#define WMM_NORMAL_PAGE_NUM_HPQ 0x29
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#define WMM_NORMAL_PAGE_NUM_LPQ 0x1C
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#define WMM_NORMAL_PAGE_NUM_NPQ 0x1C
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#define WMM_NORMAL_PAGE_NUM_PUBQ_92D 0X65//0x82
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#define WMM_NORMAL_PAGE_NUM_HPQ_92D 0X30//0x29
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#define WMM_NORMAL_PAGE_NUM_LPQ_92D 0X30
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#define WMM_NORMAL_PAGE_NUM_NPQ_92D 0X30
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//-------------------------------------------------------------------------
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// Chip specific
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//-------------------------------------------------------------------------
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#define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
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#define CHIP_BONDING_92C_1T2R 0x1
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#define CHIP_BONDING_88C_USB_MCARD 0x2
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#define CHIP_BONDING_88C_USB_HP 0x1
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//-------------------------------------------------------------------------
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// Channel Plan
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//-------------------------------------------------------------------------
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#define EFUSE_REAL_CONTENT_LEN 1024
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#define EFUSE_MAP_LEN 256
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#define EFUSE_MAX_SECTION 32
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#define EFUSE_MAX_SECTION_BASE 16
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// <Roger_Notes> To prevent out of boundary programming case, leave 1byte and program full section
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// 9bytes + 1byt + 5bytes and pre 1byte.
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// For worst case:
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// | 2byte|----8bytes----|1byte|--7bytes--| //92D
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#define EFUSE_OOB_PROTECT_BYTES 18 // PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte.
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typedef enum _PA_MODE {
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PA_MODE_EXTERNAL = 0x00,
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PA_MODE_INTERNAL_SP3T = 0x01,
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PA_MODE_INTERNAL_SPDT = 0x02
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} PA_MODE;
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/* Copy from rtl8192c */
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enum c2h_id_8192d {
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C2H_DBG = 0,
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C2H_TSF = 1,
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C2H_AP_RPT_RSP = 2,
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C2H_CCX_TX_RPT = 3,
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|
C2H_BT_RSSI = 4,
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|
C2H_BT_OP_MODE = 5,
|
|
C2H_EXT_RA_RPT = 6,
|
|
C2H_HW_INFO_EXCH = 10,
|
|
C2H_C2H_H2C_TEST = 11,
|
|
C2H_BT_INFO = 12,
|
|
C2H_BT_MP_INFO = 15,
|
|
MAX_C2HEVENT
|
|
};
|
|
|
|
#ifdef CONFIG_PCI_HCI
|
|
//
|
|
// Function disabled.
|
|
//
|
|
#define DF_TX_BIT BIT0
|
|
#define DF_RX_BIT BIT1
|
|
#define DF_IO_BIT BIT2
|
|
#define DF_IO_D3_BIT BIT3
|
|
|
|
#define RT_DF_TYPE u32
|
|
//#define RT_DISABLE_FUNC(__pAdapter, __FuncBits) ((__pAdapter)->DisabledFunctions |= ((RT_DF_TYPE)(__FuncBits)))
|
|
//#define RT_ENABLE_FUNC(__pAdapter, __FuncBits) ((__pAdapter)->DisabledFunctions &= (~((RT_DF_TYPE)(__FuncBits))))
|
|
//#define RT_IS_FUNC_DISABLED(__pAdapter, __FuncBits) ( (__pAdapter)->DisabledFunctions & (__FuncBits) )
|
|
|
|
void InterruptRecognized8192DE(PADAPTER Adapter, PRT_ISR_CONTENT pIsrContent);
|
|
VOID UpdateInterruptMask8192DE(PADAPTER Adapter, u32 AddMSR, u32 RemoveMSR);
|
|
#endif
|
|
|
|
|
|
#define GET_RF_TYPE(priv) (GET_HAL_DATA(priv)->rf_type)
|
|
|
|
int FirmwareDownload92D(IN PADAPTER Adapter);
|
|
VOID rtl8192d_FirmwareSelfReset(IN PADAPTER Adapter);
|
|
void rtl8192d_ReadChipVersion(IN PADAPTER Adapter);
|
|
VOID rtl8192d_EfuseParseChnlPlan(PADAPTER Adapter, u8 *hwinfo, BOOLEAN AutoLoadFail);
|
|
VOID rtl8192d_ReadTxPowerInfo(PADAPTER Adapter, u8* PROMContent, BOOLEAN AutoLoadFail);
|
|
VOID rtl8192d_ResetDualMacSwitchVariables(IN PADAPTER Adapter);
|
|
u8 GetEEPROMSize8192D(PADAPTER Adapter);
|
|
BOOLEAN PHY_CheckPowerOffFor8192D(PADAPTER Adapter);
|
|
VOID PHY_SetPowerOnFor8192D(PADAPTER Adapter);
|
|
//void PHY_ConfigMacPhyMode92D(PADAPTER Adapter);
|
|
void rtl8192d_free_hal_data(_adapter * padapter);
|
|
void rtl8192d_set_hal_ops(struct hal_ops *pHalFunc);
|
|
void rtl8192d_clone_haldata(_adapter* dst_adapter, _adapter* src_adapter);
|
|
#endif
|
|
|