mirror of
https://github.com/gnab/rtl8812au
synced 2024-11-26 23:25:28 +00:00
266 lines
11 KiB
C
266 lines
11 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*******************************************************************************/
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#ifndef __RTL8192E_SPEC_H__
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#define __RTL8192E_SPEC_H__
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#include <drv_conf.h>
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//============================================================
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// 8192E Regsiter offset definition
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//============================================================
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//============================================================
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//
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//============================================================
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//-----------------------------------------------------
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//
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// 0x0000h ~ 0x00FFh System Configuration
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//
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//-----------------------------------------------------
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#define REG_AFE_CTRL1_8192E 0x0024
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#define REG_AFE_CTRL2_8192E 0x0028
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#define REG_AFE_CTRL3_8192E 0x002c
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#define REG_SDIO_CTRL_8192E 0x0070
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#define REG_OPT_CTRL_8192E 0x0074
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#define REG_RF_B_CTRL_8192E 0x0076
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#define REG_AFE_CTRL4_8192E 0x0078
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#define REG_LDO_SWR_CTRL 0x007C
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#define REG_FW_DRV_MSG_8192E 0x0088
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#define REG_HMEBOX_E2_E3_8192E 0x008C
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#define REG_HIMR0_8192E 0x00B0
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#define REG_HISR0_8192E 0x00B4
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#define REG_HIMR1_8192E 0x00B8
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#define REG_HISR1_8192E 0x00BC
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#define REG_SYS_CFG1_8192E 0x00F0
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#define REG_SYS_CFG2_8192E 0x00FC
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//-----------------------------------------------------
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//
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// 0x0100h ~ 0x01FFh MACTOP General Configuration
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//
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//-----------------------------------------------------
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#define REG_PKTBUF_DBG_ADDR (REG_PKTBUF_DBG_CTRL)
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#define REG_RXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+2)
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#define REG_TXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+3)
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#define REG_RSVD3_8192E 0x0168
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#define REG_C2HEVT_CMD_SEQ_88XX 0x01A1
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#define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2
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#define REG_C2HEVT_CMD_LEN_88XX 0x01AE
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#define REG_HMEBOX_EXT0_8192E 0x01F0
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#define REG_HMEBOX_EXT1_8192E 0x01F4
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#define REG_HMEBOX_EXT2_8192E 0x01F8
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#define REG_HMEBOX_EXT3_8192E 0x01FC
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//-----------------------------------------------------
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//
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// 0x0200h ~ 0x027Fh TXDMA Configuration
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//
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//-----------------------------------------------------
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#define REG_DWBCN0_CTRL 0x0208
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#define REG_AUTO_LLT 0x0224
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#define REG_DWBCN1_CTRL 0x0228
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//-----------------------------------------------------
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//
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// 0x0280h ~ 0x02FFh RXDMA Configuration
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//
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//-----------------------------------------------------
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#define REG_RXDMA_8192E 0x0290
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#define REG_EARLY_MODE_CONTROL_8192E 0x02BC
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#define REG_RSVD5_8192E 0x02F0
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#define REG_RSVD6_8192E 0x02F4
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#define REG_RSVD7_8192E 0x02F8
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#define REG_RSVD8_8192E 0x02FC
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//-----------------------------------------------------
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//
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// 0x0300h ~ 0x03FFh PCIe
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//
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//-----------------------------------------------------
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#define REG_PCIE_MULTIFET_CTRL_8192E 0x036A //PCIE Multi-Fethc Control
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//-----------------------------------------------------
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//
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// 0x0400h ~ 0x047Fh Protocol Configuration
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//
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//-----------------------------------------------------
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#define REG_TXBF_CTRL_8192E 0x042C
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#define REG_ARFR1_8192E 0x044C
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#define REG_CCK_CHECK_8192E 0x0454
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#define REG_AMPDU_MAX_TIME_8192E 0x0456
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#define REG_BCNQ1_BDNY_8192E 0x0457
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#define REG_AMPDU_MAX_LENGTH_8192E 0x0458
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#define REG_NDPA_OPT_CTRL_8192E 0x045F
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#define REG_DATA_SC_8192E 0x0483
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#define REG_TXRPT_START_OFFSET 0x04AC
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#define REG_AMPDU_BURST_MODE_8192E 0x04BC
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#define REG_HT_SINGLE_AMPDU_8192E 0x04C7
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#define REG_MACID_PKT_DROP0_8192E 0x04D0
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//-----------------------------------------------------
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//
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// 0x0500h ~ 0x05FFh EDCA Configuration
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//
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//-----------------------------------------------------
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#define REG_CTWND_8192E 0x0572
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#define REG_SECONDARY_CCA_CTRL_8192E 0x0577
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#define REG_SCH_TXCMD_8192E 0x05F8
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//-----------------------------------------------------
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//
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// 0x0600h ~ 0x07FFh WMAC Configuration
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//
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//-----------------------------------------------------
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#define REG_MAC_CR_8192E 0x0600
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#define REG_MAC_TX_SM_STATE_8192E 0x06B4
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// Power
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#define REG_BFMER0_INFO_8192E 0x06E4
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#define REG_BFMER1_INFO_8192E 0x06EC
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#define REG_CSI_RPT_PARAM_BW20_8192E 0x06F4
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#define REG_CSI_RPT_PARAM_BW40_8192E 0x06F8
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#define REG_CSI_RPT_PARAM_BW80_8192E 0x06FC
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// Hardware Port 2
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#define REG_BFMEE_SEL_8192E 0x0714
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#define REG_SND_PTCL_CTRL_8192E 0x0718
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//-----------------------------------------------------
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//
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// Redifine register definition for compatibility
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//
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//-----------------------------------------------------
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// TODO: use these definition when using REG_xxx naming rule.
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// NOTE: DO NOT Remove these definition. Use later.
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#define ISR_8192E REG_HISR0_8192E
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//----------------------------------------------------------------------------
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// 8192E IMR/ISR bits (offset 0xB0, 8bits)
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//----------------------------------------------------------------------------
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#define IMR_DISABLED_8192E 0
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// IMR DW0(0x00B0-00B3) Bit 0-31
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#define IMR_TIMER2_8192E BIT31 // Timeout interrupt 2
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#define IMR_TIMER1_8192E BIT30 // Timeout interrupt 1
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#define IMR_PSTIMEOUT_8192E BIT29 // Power Save Time Out Interrupt
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#define IMR_GTINT4_8192E BIT28 // When GTIMER4 expires, this bit is set to 1
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#define IMR_GTINT3_8192E BIT27 // When GTIMER3 expires, this bit is set to 1
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#define IMR_TXBCN0ERR_8192E BIT26 // Transmit Beacon0 Error
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#define IMR_TXBCN0OK_8192E BIT25 // Transmit Beacon0 OK
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#define IMR_TSF_BIT32_TOGGLE_8192E BIT24 // TSF Timer BIT32 toggle indication interrupt
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#define IMR_BCNDMAINT0_8192E BIT20 // Beacon DMA Interrupt 0
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#define IMR_BCNDERR0_8192E BIT16 // Beacon Queue DMA OK0
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#define IMR_HSISR_IND_ON_INT_8192E BIT15 // HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1)
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#define IMR_BCNDMAINT_E_8192E BIT14 // Beacon DMA Interrupt Extension for Win7
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#define IMR_ATIMEND_8192E BIT12 // CTWidnow End or ATIM Window End
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#define IMR_C2HCMD_8192E BIT10 // CPU to Host Command INT Status, Write 1 clear
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#define IMR_CPWM2_8192E BIT9 // CPU power Mode exchange INT Status, Write 1 clear
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#define IMR_CPWM_8192E BIT8 // CPU power Mode exchange INT Status, Write 1 clear
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#define IMR_HIGHDOK_8192E BIT7 // High Queue DMA OK
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#define IMR_MGNTDOK_8192E BIT6 // Management Queue DMA OK
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#define IMR_BKDOK_8192E BIT5 // AC_BK DMA OK
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#define IMR_BEDOK_8192E BIT4 // AC_BE DMA OK
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#define IMR_VIDOK_8192E BIT3 // AC_VI DMA OK
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#define IMR_VODOK_8192E BIT2 // AC_VO DMA OK
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#define IMR_RDU_8192E BIT1 // Rx Descriptor Unavailable
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#define IMR_ROK_8192E BIT0 // Receive DMA OK
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// IMR DW1(0x00B4-00B7) Bit 0-31
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#define IMR_BCNDMAINT7_8192E BIT27 // Beacon DMA Interrupt 7
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#define IMR_BCNDMAINT6_8192E BIT26 // Beacon DMA Interrupt 6
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#define IMR_BCNDMAINT5_8192E BIT25 // Beacon DMA Interrupt 5
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#define IMR_BCNDMAINT4_8192E BIT24 // Beacon DMA Interrupt 4
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#define IMR_BCNDMAINT3_8192E BIT23 // Beacon DMA Interrupt 3
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#define IMR_BCNDMAINT2_8192E BIT22 // Beacon DMA Interrupt 2
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#define IMR_BCNDMAINT1_8192E BIT21 // Beacon DMA Interrupt 1
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#define IMR_BCNDOK7_8192E BIT20 // Beacon Queue DMA OK Interrup 7
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#define IMR_BCNDOK6_8192E BIT19 // Beacon Queue DMA OK Interrup 6
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#define IMR_BCNDOK5_8192E BIT18 // Beacon Queue DMA OK Interrup 5
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#define IMR_BCNDOK4_8192E BIT17 // Beacon Queue DMA OK Interrup 4
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#define IMR_BCNDOK3_8192E BIT16 // Beacon Queue DMA OK Interrup 3
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#define IMR_BCNDOK2_8192E BIT15 // Beacon Queue DMA OK Interrup 2
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#define IMR_BCNDOK1_8192E BIT14 // Beacon Queue DMA OK Interrup 1
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#define IMR_ATIMEND_E_8192E BIT13 // ATIM Window End Extension for Win7
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#define IMR_TXERR_8192E BIT11 // Tx Error Flag Interrupt Status, write 1 clear.
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#define IMR_RXERR_8192E BIT10 // Rx Error Flag INT Status, Write 1 clear
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#define IMR_TXFOVW_8192E BIT9 // Transmit FIFO Overflow
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#define IMR_RXFOVW_8192E BIT8 // Receive FIFO Overflow
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//----------------------------------------------------------------------------
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// 8192E Auto LLT bits (offset 0x224, 8bits)
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//----------------------------------------------------------------------------
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//224 REG_AUTO_LLT
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#define BIT_SHIFT_TXPKTNUM 24
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#define BIT_MASK_TXPKTNUM 0xff
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#define BIT_TXPKTNUM(x) (((x) & BIT_MASK_TXPKTNUM) << BIT_SHIFT_TXPKTNUM)
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#define BIT_TDE_DBG_SEL BIT(23)
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#define BIT_AUTO_INIT_LLT BIT(16)
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#define BIT_SHIFT_Tx_OQT_free_space 8
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#define BIT_MASK_Tx_OQT_free_space 0xff
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#define BIT_Tx_OQT_free_space(x) (((x) & BIT_MASK_Tx_OQT_free_space) << BIT_SHIFT_Tx_OQT_free_space)
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//----------------------------------------------------------------------------
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// 8192E Auto LLT bits (offset 0x290, 32bits)
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//----------------------------------------------------------------------------
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#define BIT_DMA_MODE BIT1
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#define BIT_USB_RXDMA_AGG_EN BIT31
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//----------------------------------------------------------------------------
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// 8192E REG_SYS_CFG1 (offset 0xF0, 32bits)
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//----------------------------------------------------------------------------
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#define BIT_SPSLDO_SEL BIT24
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//----------------------------------------------------------------------------
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// 8192E REG_CCK_CHECK (offset 0x454, 8bits)
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//----------------------------------------------------------------------------
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#define BIT_BCN_PORT_SEL BIT5
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//============================================================================
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// Regsiter Bit and Content definition
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//============================================================================
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//2 ACMHWCTRL 0x05C0
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#define AcmHw_HwEn_8192E BIT(0)
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#define AcmHw_VoqEn_8192E BIT(1)
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#define AcmHw_ViqEn_8192E BIT(2)
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#define AcmHw_BeqEn_8192E BIT(3)
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#define AcmHw_VoqStatus_8192E BIT(5)
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#define AcmHw_ViqStatus_8192E BIT(6)
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#define AcmHw_BeqStatus_8192E BIT(7)
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#endif //__RTL8192E_SPEC_H__
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