mirror of
https://github.com/morrownr/8821cu-20210916.git
synced 2024-12-28 17:09:32 +00:00
271 lines
14 KiB
C
271 lines
14 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#ifndef __HAL_PHY_REG_H__
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#define __HAL_PHY_REG_H__
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/* for PutRFRegsetting & GetRFRegSetting BitMask*/
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#define bRFRegOffsetMask 0xfffff
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/* alias for phydm coding style */
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#define REG_OFDM_0_XA_TX_IQ_IMBALANCE rOFDM0_XATxIQImbalance
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#define REG_OFDM_0_ECCA_THRESHOLD rOFDM0_ECCAThreshold
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#define REG_FPGA0_XB_LSSI_READ_BACK rFPGA0_XB_LSSIReadBack
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#define REG_FPGA0_TX_GAIN_STAGE rFPGA0_TxGainStage
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#define REG_OFDM_0_XA_AGC_CORE1 rOFDM0_XAAGCCore1
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#define REG_OFDM_0_XB_AGC_CORE1 rOFDM0_XBAGCCore1
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#define REG_A_TX_SCALE_JAGUAR rA_TxScale_Jaguar
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#define REG_B_TX_SCALE_JAGUAR rB_TxScale_Jaguar
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#define REG_FPGA0_XAB_RF_INTERFACE_SW rFPGA0_XAB_RFInterfaceSW
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#define REG_FPGA0_XAB_RF_PARAMETER rFPGA0_XAB_RFParameter
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#define REG_FPGA0_XA_HSSI_PARAMETER1 rFPGA0_XA_HSSIParameter1
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#define REG_FPGA0_XA_LSSI_PARAMETER rFPGA0_XA_LSSIParameter
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#define REG_FPGA0_XA_RF_INTERFACE_OE rFPGA0_XA_RFInterfaceOE
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#define REG_FPGA0_XB_HSSI_PARAMETER1 rFPGA0_XB_HSSIParameter1
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#define REG_FPGA0_XB_LSSI_PARAMETER rFPGA0_XB_LSSIParameter
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#define REG_FPGA0_XB_LSSI_READ_BACK rFPGA0_XB_LSSIReadBack
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#define REG_FPGA0_XB_RF_INTERFACE_OE rFPGA0_XB_RFInterfaceOE
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#define REG_FPGA0_XCD_RF_INTERFACE_SW rFPGA0_XCD_RFInterfaceSW
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#define REG_FPGA0_XCD_SWITCH_CONTROL rFPGA0_XCD_SwitchControl
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#define REG_FPGA1_TX_BLOCK rFPGA1_TxBlock
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#define REG_FPGA1_TX_INFO rFPGA1_TxInfo
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#define REG_IQK_AGC_CONT rIQK_AGC_Cont
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#define REG_IQK_AGC_PTS rIQK_AGC_Pts
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#define REG_IQK_AGC_RSP rIQK_AGC_Rsp
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#define REG_OFDM_0_AGC_RSSI_TABLE rOFDM0_AGCRSSITable
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#define REG_OFDM_0_ECCA_THRESHOLD rOFDM0_ECCAThreshold
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#define REG_OFDM_0_RX_IQ_EXT_ANTA rOFDM0_RxIQExtAnta
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#define REG_OFDM_0_TR_MUX_PAR rOFDM0_TRMuxPar
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#define REG_OFDM_0_TRX_PATH_ENABLE rOFDM0_TRxPathEnable
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#define REG_OFDM_0_XA_AGC_CORE1 rOFDM0_XAAGCCore1
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#define REG_OFDM_0_XA_RX_IQ_IMBALANCE rOFDM0_XARxIQImbalance
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#define REG_OFDM_0_XA_TX_IQ_IMBALANCE rOFDM0_XATxIQImbalance
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#define REG_OFDM_0_XB_AGC_CORE1 rOFDM0_XBAGCCore1
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#define REG_OFDM_0_XB_RX_IQ_IMBALANCE rOFDM0_XBRxIQImbalance
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#define REG_OFDM_0_XB_TX_IQ_IMBALANCE rOFDM0_XBTxIQImbalance
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#define REG_OFDM_0_XC_TX_AFE rOFDM0_XCTxAFE
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#define REG_OFDM_0_XD_TX_AFE rOFDM0_XDTxAFE
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/*#define REG_A_CFO_LONG_DUMP_92E rA_CfoLongDump_92E*/
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#define REG_A_CFO_LONG_DUMP_JAGUAR rA_CfoLongDump_Jaguar
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/*#define REG_A_CFO_SHORT_DUMP_92E rA_CfoShortDump_92E*/
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#define REG_A_CFO_SHORT_DUMP_JAGUAR rA_CfoShortDump_Jaguar
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#define REG_A_RFE_PINMUX_JAGUAR rA_RFE_Pinmux_Jaguar
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/*#define REG_A_RSSI_DUMP_92E rA_RSSIDump_92E*/
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#define REG_A_RSSI_DUMP_JAGUAR rA_RSSIDump_Jaguar
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/*#define REG_A_RX_SNR_DUMP_92E rA_RXsnrDump_92E*/
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#define REG_A_RX_SNR_DUMP_JAGUAR rA_RXsnrDump_Jaguar
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/*#define REG_A_TX_AGC rA_TXAGC*/
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#define REG_A_TX_SCALE_JAGUAR rA_TxScale_Jaguar
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#define REG_BW_INDICATION_JAGUAR rBWIndication_Jaguar
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/*#define REG_B_BBSWING rB_BBSWING*/
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/*#define REG_B_CFO_LONG_DUMP_92E rB_CfoLongDump_92E*/
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#define REG_B_CFO_LONG_DUMP_JAGUAR rB_CfoLongDump_Jaguar
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/*#define REG_B_CFO_SHORT_DUMP_92E rB_CfoShortDump_92E*/
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#define REG_B_CFO_SHORT_DUMP_JAGUAR rB_CfoShortDump_Jaguar
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/*#define REG_B_RSSI_DUMP_92E rB_RSSIDump_92E*/
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#define REG_B_RSSI_DUMP_JAGUAR rB_RSSIDump_Jaguar
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/*#define REG_B_RX_SNR_DUMP_92E rB_RXsnrDump_92E*/
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#define REG_B_RX_SNR_DUMP_JAGUAR rB_RXsnrDump_Jaguar
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/*#define REG_B_TX_AGC rB_TXAGC*/
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#define REG_B_TX_SCALE_JAGUAR rB_TxScale_Jaguar
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#define REG_BLUE_TOOTH rBlue_Tooth
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#define REG_CCK_0_AFE_SETTING rCCK0_AFESetting
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/*#define REG_C_BBSWING rC_BBSWING*/
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/*#define REG_C_TX_AGC rC_TXAGC*/
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#define REG_C_TX_SCALE_JAGUAR2 rC_TxScale_Jaguar2
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#define REG_CONFIG_ANT_A rConfig_AntA
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#define REG_CONFIG_ANT_B rConfig_AntB
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#define REG_CONFIG_PMPD_ANT_A rConfig_Pmpd_AntA
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#define REG_CONFIG_PMPD_ANT_B rConfig_Pmpd_AntB
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#define REG_DPDT_CONTROL rDPDT_control
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/*#define REG_D_BBSWING rD_BBSWING*/
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/*#define REG_D_TX_AGC rD_TXAGC*/
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#define REG_D_TX_SCALE_JAGUAR2 rD_TxScale_Jaguar2
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#define REG_FPGA0_ANALOG_PARAMETER4 rFPGA0_AnalogParameter4
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#define REG_FPGA0_IQK rFPGA0_IQK
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#define REG_FPGA0_PSD_FUNCTION rFPGA0_PSDFunction
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#define REG_FPGA0_PSD_REPORT rFPGA0_PSDReport
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#define REG_FPGA0_RFMOD rFPGA0_RFMOD
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#define REG_FPGA0_TX_GAIN_STAGE rFPGA0_TxGainStage
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#define REG_FPGA0_XAB_RF_INTERFACE_SW rFPGA0_XAB_RFInterfaceSW
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#define REG_FPGA0_XAB_RF_PARAMETER rFPGA0_XAB_RFParameter
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#define REG_FPGA0_XA_HSSI_PARAMETER1 rFPGA0_XA_HSSIParameter1
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#define REG_FPGA0_XA_LSSI_PARAMETER rFPGA0_XA_LSSIParameter
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#define REG_FPGA0_XA_RF_INTERFACE_OE rFPGA0_XA_RFInterfaceOE
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#define REG_FPGA0_XB_HSSI_PARAMETER1 rFPGA0_XB_HSSIParameter1
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#define REG_FPGA0_XB_LSSI_PARAMETER rFPGA0_XB_LSSIParameter
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#define REG_FPGA0_XB_LSSI_READ_BACK rFPGA0_XB_LSSIReadBack
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#define REG_FPGA0_XB_RF_INTERFACE_OE rFPGA0_XB_RFInterfaceOE
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#define REG_FPGA0_XCD_RF_INTERFACE_SW rFPGA0_XCD_RFInterfaceSW
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#define REG_FPGA0_XCD_SWITCH_CONTROL rFPGA0_XCD_SwitchControl
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#define REG_FPGA1_TX_BLOCK rFPGA1_TxBlock
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#define REG_FPGA1_TX_INFO rFPGA1_TxInfo
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#define REG_IQK_AGC_CONT rIQK_AGC_Cont
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#define REG_IQK_AGC_PTS rIQK_AGC_Pts
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#define REG_IQK_AGC_RSP rIQK_AGC_Rsp
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#define REG_OFDM_0_AGC_RSSI_TABLE rOFDM0_AGCRSSITable
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#define REG_OFDM_0_ECCA_THRESHOLD rOFDM0_ECCAThreshold
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#define REG_OFDM_0_RX_IQ_EXT_ANTA rOFDM0_RxIQExtAnta
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#define REG_OFDM_0_TR_MUX_PAR rOFDM0_TRMuxPar
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#define REG_OFDM_0_TRX_PATH_ENABLE rOFDM0_TRxPathEnable
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#define REG_OFDM_0_XA_AGC_CORE1 rOFDM0_XAAGCCore1
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#define REG_OFDM_0_XA_RX_IQ_IMBALANCE rOFDM0_XARxIQImbalance
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#define REG_OFDM_0_XA_TX_IQ_IMBALANCE rOFDM0_XATxIQImbalance
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#define REG_OFDM_0_XB_AGC_CORE1 rOFDM0_XBAGCCore1
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#define REG_OFDM_0_XB_RX_IQ_IMBALANCE rOFDM0_XBRxIQImbalance
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#define REG_OFDM_0_XB_TX_IQ_IMBALANCE rOFDM0_XBTxIQImbalance
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#define REG_OFDM_0_XC_TX_AFE rOFDM0_XCTxAFE
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#define REG_OFDM_0_XD_TX_AFE rOFDM0_XDTxAFE
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#define REG_PMPD_ANAEN rPMPD_ANAEN
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#define REG_PDP_ANT_A rPdp_AntA
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#define REG_PDP_ANT_A_4 rPdp_AntA_4
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#define REG_PDP_ANT_B rPdp_AntB
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#define REG_PDP_ANT_B_4 rPdp_AntB_4
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#define REG_PWED_TH_JAGUAR rPwed_TH_Jaguar
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#define REG_RX_CCK rRx_CCK
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#define REG_RX_IQK rRx_IQK
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#define REG_RX_IQK_PI_A rRx_IQK_PI_A
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#define REG_RX_IQK_PI_B rRx_IQK_PI_B
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#define REG_RX_IQK_TONE_A rRx_IQK_Tone_A
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#define REG_RX_IQK_TONE_B rRx_IQK_Tone_B
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#define REG_RX_OFDM rRx_OFDM
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#define REG_RX_POWER_AFTER_IQK_A_2 rRx_Power_After_IQK_A_2
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#define REG_RX_POWER_AFTER_IQK_B_2 rRx_Power_After_IQK_B_2
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#define REG_RX_POWER_BEFORE_IQK_A_2 rRx_Power_Before_IQK_A_2
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#define REG_RX_POWER_BEFORE_IQK_B_2 rRx_Power_Before_IQK_B_2
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#define REG_RX_TO_RX rRx_TO_Rx
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#define REG_RX_WAIT_CCA rRx_Wait_CCA
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#define REG_RX_WAIT_RIFS rRx_Wait_RIFS
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#define REG_S0_S1_PATH_SWITCH rS0S1_PathSwitch
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/*#define REG_S1_RXEVM_DUMP_92E rS1_RXevmDump_92E*/
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#define REG_S1_RXEVM_DUMP_JAGUAR rS1_RXevmDump_Jaguar
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/*#define REG_S2_RXEVM_DUMP_92E rS2_RXevmDump_92E*/
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#define REG_S2_RXEVM_DUMP_JAGUAR rS2_RXevmDump_Jaguar
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#define REG_SYM_WLBT_PAPE_SEL rSYM_WLBT_PAPE_SEL
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#define REG_SINGLE_TONE_CONT_TX_JAGUAR rSingleTone_ContTx_Jaguar
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#define REG_SLEEP rSleep
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#define REG_STANDBY rStandby
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#define REG_TX_AGC_A_CCK_11_CCK_1_JAGUAR rTxAGC_A_CCK11_CCK1_JAguar
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#define REG_TX_AGC_A_CCK_1_MCS32 rTxAGC_A_CCK1_Mcs32
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#define REG_TX_AGC_A_MCS11_MCS8_JAGUAR rTxAGC_A_MCS11_MCS8_JAguar
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#define REG_TX_AGC_A_MCS15_MCS12_JAGUAR rTxAGC_A_MCS15_MCS12_JAguar
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#define REG_TX_AGC_A_MCS19_MCS16_JAGUAR rTxAGC_A_MCS19_MCS16_JAguar
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#define REG_TX_AGC_A_MCS23_MCS20_JAGUAR rTxAGC_A_MCS23_MCS20_JAguar
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#define REG_TX_AGC_A_MCS3_MCS0_JAGUAR rTxAGC_A_MCS3_MCS0_JAguar
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#define REG_TX_AGC_A_MCS7_MCS4_JAGUAR rTxAGC_A_MCS7_MCS4_JAguar
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#define REG_TX_AGC_A_MCS03_MCS00 rTxAGC_A_Mcs03_Mcs00
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#define REG_TX_AGC_A_MCS07_MCS04 rTxAGC_A_Mcs07_Mcs04
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#define REG_TX_AGC_A_MCS11_MCS08 rTxAGC_A_Mcs11_Mcs08
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#define REG_TX_AGC_A_MCS15_MCS12 rTxAGC_A_Mcs15_Mcs12
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#define REG_TX_AGC_A_NSS1_INDEX3_NSS1_INDEX0_JAGUAR rTxAGC_A_Nss1Index3_Nss1Index0_JAguar
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#define REG_TX_AGC_A_NSS1_INDEX7_NSS1_INDEX4_JAGUAR rTxAGC_A_Nss1Index7_Nss1Index4_JAguar
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#define REG_TX_AGC_A_NSS2_INDEX1_NSS1_INDEX8_JAGUAR rTxAGC_A_Nss2Index1_Nss1Index8_JAguar
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#define REG_TX_AGC_A_NSS2_INDEX5_NSS2_INDEX2_JAGUAR rTxAGC_A_Nss2Index5_Nss2Index2_JAguar
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#define REG_TX_AGC_A_NSS2_INDEX9_NSS2_INDEX6_JAGUAR rTxAGC_A_Nss2Index9_Nss2Index6_JAguar
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#define REG_TX_AGC_A_NSS3_INDEX3_NSS3_INDEX0_JAGUAR rTxAGC_A_Nss3Index3_Nss3Index0_JAguar
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#define REG_TX_AGC_A_NSS3_INDEX7_NSS3_INDEX4_JAGUAR rTxAGC_A_Nss3Index7_Nss3Index4_JAguar
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#define REG_TX_AGC_A_NSS3_INDEX9_NSS3_INDEX8_JAGUAR rTxAGC_A_Nss3Index9_Nss3Index8_JAguar
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#define REG_TX_AGC_A_OFDM18_OFDM6_JAGUAR rTxAGC_A_Ofdm18_Ofdm6_JAguar
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#define REG_TX_AGC_A_OFDM54_OFDM24_JAGUAR rTxAGC_A_Ofdm54_Ofdm24_JAguar
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#define REG_TX_AGC_A_RATE18_06 rTxAGC_A_Rate18_06
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#define REG_TX_AGC_A_RATE54_24 rTxAGC_A_Rate54_24
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#define REG_TX_AGC_B_CCK_11_A_CCK_2_11 rTxAGC_B_CCK11_A_CCK2_11
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#define REG_TX_AGC_B_CCK_11_CCK_1_JAGUAR rTxAGC_B_CCK11_CCK1_JAguar
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#define REG_TX_AGC_B_CCK_1_55_MCS32 rTxAGC_B_CCK1_55_Mcs32
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#define REG_TX_AGC_B_MCS11_MCS8_JAGUAR rTxAGC_B_MCS11_MCS8_JAguar
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#define REG_TX_AGC_B_MCS15_MCS12_JAGUAR rTxAGC_B_MCS15_MCS12_JAguar
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#define REG_TX_AGC_B_MCS19_MCS16_JAGUAR rTxAGC_B_MCS19_MCS16_JAguar
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#define REG_TX_AGC_B_MCS23_MCS20_JAGUAR rTxAGC_B_MCS23_MCS20_JAguar
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#define REG_TX_AGC_B_MCS3_MCS0_JAGUAR rTxAGC_B_MCS3_MCS0_JAguar
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#define REG_TX_AGC_B_MCS7_MCS4_JAGUAR rTxAGC_B_MCS7_MCS4_JAguar
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#define REG_TX_AGC_B_MCS03_MCS00 rTxAGC_B_Mcs03_Mcs00
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#define REG_TX_AGC_B_MCS07_MCS04 rTxAGC_B_Mcs07_Mcs04
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#define REG_TX_AGC_B_MCS11_MCS08 rTxAGC_B_Mcs11_Mcs08
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#define REG_TX_AGC_B_MCS15_MCS12 rTxAGC_B_Mcs15_Mcs12
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#define REG_TX_AGC_B_NSS1_INDEX3_NSS1_INDEX0_JAGUAR rTxAGC_B_Nss1Index3_Nss1Index0_JAguar
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#define REG_TX_AGC_B_NSS1_INDEX7_NSS1_INDEX4_JAGUAR rTxAGC_B_Nss1Index7_Nss1Index4_JAguar
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#define REG_TX_AGC_B_NSS2_INDEX1_NSS1_INDEX8_JAGUAR rTxAGC_B_Nss2Index1_Nss1Index8_JAguar
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#define REG_TX_AGC_B_NSS2_INDEX5_NSS2_INDEX2_JAGUAR rTxAGC_B_Nss2Index5_Nss2Index2_JAguar
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#define REG_TX_AGC_B_NSS2_INDEX9_NSS2_INDEX6_JAGUAR rTxAGC_B_Nss2Index9_Nss2Index6_JAguar
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#define REG_TX_AGC_B_NSS3_INDEX3_NSS3_INDEX0_JAGUAR rTxAGC_B_Nss3Index3_Nss3Index0_JAguar
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#define REG_TX_AGC_B_NSS3_INDEX7_NSS3_INDEX4_JAGUAR rTxAGC_B_Nss3Index7_Nss3Index4_JAguar
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#define REG_TX_AGC_B_NSS3_INDEX9_NSS3_INDEX8_JAGUAR rTxAGC_B_Nss3Index9_Nss3Index8_JAguar
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#define REG_TX_AGC_B_OFDM18_OFDM6_JAGUAR rTxAGC_B_Ofdm18_Ofdm6_JAguar
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#define REG_TX_AGC_B_OFDM54_OFDM24_JAGUAR rTxAGC_B_Ofdm54_Ofdm24_JAguar
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#define REG_TX_AGC_B_RATE18_06 rTxAGC_B_Rate18_06
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#define REG_TX_AGC_B_RATE54_24 rTxAGC_B_Rate54_24
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#define REG_TX_AGC_C_CCK_11_CCK_1_JAGUAR rTxAGC_C_CCK11_CCK1_JAguar
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#define REG_TX_AGC_C_MCS11_MCS8_JAGUAR rTxAGC_C_MCS11_MCS8_JAguar
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#define REG_TX_AGC_C_MCS15_MCS12_JAGUAR rTxAGC_C_MCS15_MCS12_JAguar
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#define REG_TX_AGC_C_MCS19_MCS16_JAGUAR rTxAGC_C_MCS19_MCS16_JAguar
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#define REG_TX_AGC_C_MCS23_MCS20_JAGUAR rTxAGC_C_MCS23_MCS20_JAguar
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#define REG_TX_AGC_C_MCS3_MCS0_JAGUAR rTxAGC_C_MCS3_MCS0_JAguar
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#define REG_TX_AGC_C_MCS7_MCS4_JAGUAR rTxAGC_C_MCS7_MCS4_JAguar
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#define REG_TX_AGC_C_NSS1_INDEX3_NSS1_INDEX0_JAGUAR rTxAGC_C_Nss1Index3_Nss1Index0_JAguar
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#define REG_TX_AGC_C_NSS1_INDEX7_NSS1_INDEX4_JAGUAR rTxAGC_C_Nss1Index7_Nss1Index4_JAguar
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#define REG_TX_AGC_C_NSS2_INDEX1_NSS1_INDEX8_JAGUAR rTxAGC_C_Nss2Index1_Nss1Index8_JAguar
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#define REG_TX_AGC_C_NSS2_INDEX5_NSS2_INDEX2_JAGUAR rTxAGC_C_Nss2Index5_Nss2Index2_JAguar
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#define REG_TX_AGC_C_NSS2_INDEX9_NSS2_INDEX6_JAGUAR rTxAGC_C_Nss2Index9_Nss2Index6_JAguar
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#define REG_TX_AGC_C_NSS3_INDEX3_NSS3_INDEX0_JAGUAR rTxAGC_C_Nss3Index3_Nss3Index0_JAguar
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#define REG_TX_AGC_C_NSS3_INDEX7_NSS3_INDEX4_JAGUAR rTxAGC_C_Nss3Index7_Nss3Index4_JAguar
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#define REG_TX_AGC_C_NSS3_INDEX9_NSS3_INDEX8_JAGUAR rTxAGC_C_Nss3Index9_Nss3Index8_JAguar
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#define REG_TX_AGC_C_OFDM18_OFDM6_JAGUAR rTxAGC_C_Ofdm18_Ofdm6_JAguar
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#define REG_TX_AGC_C_OFDM54_OFDM24_JAGUAR rTxAGC_C_Ofdm54_Ofdm24_JAguar
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#define REG_TX_AGC_D_CCK_11_CCK_1_JAGUAR rTxAGC_D_CCK11_CCK1_JAguar
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#define REG_TX_AGC_D_MCS11_MCS8_JAGUAR rTxAGC_D_MCS11_MCS8_JAguar
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#define REG_TX_AGC_D_MCS15_MCS12_JAGUAR rTxAGC_D_MCS15_MCS12_JAguar
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#define REG_TX_AGC_D_MCS19_MCS16_JAGUAR rTxAGC_D_MCS19_MCS16_JAguar
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#define REG_TX_AGC_D_MCS23_MCS20_JAGUAR rTxAGC_D_MCS23_MCS20_JAguar
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#define REG_TX_AGC_D_MCS3_MCS0_JAGUAR rTxAGC_D_MCS3_MCS0_JAguar
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#define REG_TX_AGC_D_MCS7_MCS4_JAGUAR rTxAGC_D_MCS7_MCS4_JAguar
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#define REG_TX_AGC_D_NSS1_INDEX3_NSS1_INDEX0_JAGUAR rTxAGC_D_Nss1Index3_Nss1Index0_JAguar
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#define REG_TX_AGC_D_NSS1_INDEX7_NSS1_INDEX4_JAGUAR rTxAGC_D_Nss1Index7_Nss1Index4_JAguar
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#define REG_TX_AGC_D_NSS2_INDEX1_NSS1_INDEX8_JAGUAR rTxAGC_D_Nss2Index1_Nss1Index8_JAguar
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#define REG_TX_AGC_D_NSS2_INDEX5_NSS2_INDEX2_JAGUAR rTxAGC_D_Nss2Index5_Nss2Index2_JAguar
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#define REG_TX_AGC_D_NSS2_INDEX9_NSS2_INDEX6_JAGUAR rTxAGC_D_Nss2Index9_Nss2Index6_JAguar
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#define REG_TX_AGC_D_NSS3_INDEX3_NSS3_INDEX0_JAGUAR rTxAGC_D_Nss3Index3_Nss3Index0_JAguar
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#define REG_TX_AGC_D_NSS3_INDEX7_NSS3_INDEX4_JAGUAR rTxAGC_D_Nss3Index7_Nss3Index4_JAguar
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#define REG_TX_AGC_D_NSS3_INDEX9_NSS3_INDEX8_JAGUAR rTxAGC_D_Nss3Index9_Nss3Index8_JAguar
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#define REG_TX_AGC_D_OFDM18_OFDM6_JAGUAR rTxAGC_D_Ofdm18_Ofdm6_JAguar
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#define REG_TX_AGC_D_OFDM54_OFDM24_JAGUAR rTxAGC_D_Ofdm54_Ofdm24_JAguar
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#define REG_TX_PATH_JAGUAR rTxPath_Jaguar
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#define REG_TX_CCK_BBON rTx_CCK_BBON
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#define REG_TX_CCK_RFON rTx_CCK_RFON
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#define REG_TX_IQK rTx_IQK
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#define REG_TX_IQK_PI_A rTx_IQK_PI_A
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#define REG_TX_IQK_PI_B rTx_IQK_PI_B
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#define REG_TX_IQK_TONE_A rTx_IQK_Tone_A
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#define REG_TX_IQK_TONE_B rTx_IQK_Tone_B
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#define REG_TX_OFDM_BBON rTx_OFDM_BBON
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#define REG_TX_OFDM_RFON rTx_OFDM_RFON
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#define REG_TX_POWER_AFTER_IQK_A rTx_Power_After_IQK_A
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#define REG_TX_POWER_AFTER_IQK_B rTx_Power_After_IQK_B
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#define REG_TX_POWER_BEFORE_IQK_A rTx_Power_Before_IQK_A
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#define REG_TX_POWER_BEFORE_IQK_B rTx_Power_Before_IQK_B
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#define REG_TX_TO_RX rTx_To_Rx
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#define REG_TX_TO_TX rTx_To_Tx
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#define REG_APK rAPK
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#define REG_ANTSEL_SW_JAGUAR r_ANTSEL_SW_Jaguar
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#define rf_welut_jaguar RF_WeLut_Jaguar
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#define rf_mode_table_addr RF_ModeTableAddr
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#define rf_mode_table_data0 RF_ModeTableData0
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#define rf_mode_table_data1 RF_ModeTableData1
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#define RX_SMOOTH_FACTOR Rx_Smooth_Factor
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#endif /* __HAL_PHY_REG_H__ */
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