mirror of
https://github.com/morrownr/8821cu-20210916.git
synced 2024-11-18 19:44:48 +00:00
263 lines
6.9 KiB
C
263 lines
6.9 KiB
C
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/******************************************************************************
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*
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* Copyright(c) 2016 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#include "mp_precomp.h"
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#include "../phydm_precomp.h"
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#if (RTL8821C_SUPPORT == 1)
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void odm_config_rf_reg_8821c(struct dm_struct *dm, u32 addr, u32 data,
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enum rf_path rf_path, u32 reg_addr)
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{
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if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) {
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if (addr == 0xffe) {
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phydm_set_reg_by_fw(dm,
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PHYDM_HALMAC_CMD_DELAY_MS,
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reg_addr,
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data,
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RFREGOFFSETMASK,
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rf_path,
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50);
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} else if (addr == 0xfe) {
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phydm_set_reg_by_fw(dm,
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PHYDM_HALMAC_CMD_DELAY_US,
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reg_addr,
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data,
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RFREGOFFSETMASK,
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rf_path,
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100);
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} else {
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phydm_set_reg_by_fw(dm,
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PHYDM_HALMAC_CMD_RF_W,
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reg_addr,
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data,
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RFREGOFFSETMASK,
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rf_path,
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0);
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phydm_set_reg_by_fw(dm,
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PHYDM_HALMAC_CMD_DELAY_US,
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reg_addr,
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data,
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RFREGOFFSETMASK,
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rf_path,
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1);
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}
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} else {
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if (addr == 0xffe) {
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#ifdef CONFIG_LONG_DELAY_ISSUE
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ODM_sleep_ms(50);
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#else
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ODM_delay_ms(50);
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#endif
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} else if (addr == 0xfe) {
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#ifdef CONFIG_LONG_DELAY_ISSUE
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ODM_sleep_us(100);
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#else
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ODM_delay_us(100);
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#endif
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} else {
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odm_set_rf_reg(dm, rf_path, reg_addr, RFREGOFFSETMASK, data);
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/* Add 1us delay between BB/RF register setting. */
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ODM_delay_us(1);
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}
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}
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}
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void odm_config_rf_radio_a_8821c(struct dm_struct *dm, u32 addr, u32 data)
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{
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u32 content = 0x1000; /* RF_Content: radioa_txt */
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u32 maskfor_phy_set = (u32)(content & 0xE000);
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odm_config_rf_reg_8821c(dm, addr, data, RF_PATH_A, addr | maskfor_phy_set);
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PHYDM_DBG(dm, ODM_COMP_INIT,
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"===> odm_config_rf_with_header_file: [RadioA] %08X %08X\n",
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addr, data);
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}
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void odm_config_mac_8821c(struct dm_struct *dm, u32 addr, u8 data)
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{
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if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD)
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phydm_set_reg_by_fw(dm,
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PHYDM_HALMAC_CMD_MAC_W8,
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addr,
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data,
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0,
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(enum rf_path)0,
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0);
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else
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odm_write_1byte(dm, addr, data);
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PHYDM_DBG(dm, ODM_COMP_INIT, "===> config_mac: [MAC_REG] %08X %08X\n",
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addr, data);
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}
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void odm_update_agc_big_jump_lmt_8821c(struct dm_struct *dm, u32 addr, u32 data)
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{
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struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
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u8 rf_gain_idx = (u8)((data & 0xFF000000) >> 24);
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u8 bb_gain_idx = (u8)((data & 0x00ff0000) >> 16);
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u8 agc_table_idx = (u8)((data & 0x00000f00) >> 8);
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static boolean is_limit;
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if (addr != 0x81c)
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return;
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/*dbg_print("data = 0x%x, rf_gain_idx = 0x%x, bb_gain_idx = 0x%x, agc_table_idx = 0x%x\n", data, rf_gain_idx, bb_gain_idx, agc_table_idx);*/
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/*dbg_print("rf_gain_idx = 0x%x, dig_t->rf_gain_idx = 0x%x\n", rf_gain_idx, dig_t->rf_gain_idx);*/
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if (bb_gain_idx > 0x3c) {
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if (rf_gain_idx == dig_t->rf_gain_idx && is_limit == false) {
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is_limit = true;
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dig_t->big_jump_lmt[agc_table_idx] = bb_gain_idx - 2;
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PHYDM_DBG(dm, DBG_DIG,
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"===> [AGC_TAB] big_jump_lmt [%d] = 0x%x\n",
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agc_table_idx,
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dig_t->big_jump_lmt[agc_table_idx]);
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}
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} else {
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is_limit = false;
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}
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dig_t->rf_gain_idx = rf_gain_idx;
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}
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void odm_config_bb_agc_8821c(struct dm_struct *dm, u32 addr, u32 bitmask,
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u32 data)
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{
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odm_update_agc_big_jump_lmt_8821c(dm, addr, data);
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if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD)
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phydm_set_reg_by_fw(dm,
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PHYDM_HALMAC_CMD_BB_W32,
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addr,
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data,
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bitmask,
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(enum rf_path)0,
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0);
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else
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odm_set_bb_reg(dm, addr, bitmask, data);
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PHYDM_DBG(dm, ODM_COMP_INIT, "===> config_bb: [AGC_TAB] %08X %08X\n",
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addr, data);
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}
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void odm_config_bb_phy_reg_pg_8821c(struct dm_struct *dm, u32 band, u32 rf_path,
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u32 tx_num, u32 addr, u32 bitmask, u32 data)
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{
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#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
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phy_store_tx_power_by_rate(dm->adapter, band, rf_path, tx_num, addr, bitmask, data);
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#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
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PHY_StoreTxPowerByRate(dm->adapter, band, rf_path, tx_num, addr, bitmask, data);
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#endif
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PHYDM_DBG(dm, ODM_COMP_INIT,
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"===> odm_config_bb_with_header_file: [PHY_REG] %08X %08X %08X\n",
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addr, bitmask, data);
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}
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void odm_config_bb_phy_8821c(struct dm_struct *dm, u32 addr, u32 bitmask,
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u32 data)
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{
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if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) {
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u32 delay_time = 0;
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if (addr >= 0xf9 && addr <= 0xfe) {
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if (addr == 0xfe || addr == 0xfb)
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delay_time = 50;
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else if (addr == 0xfd || addr == 0xfa)
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delay_time = 5;
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else
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delay_time = 1;
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if (addr >= 0xfc && addr <= 0xfe)
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phydm_set_reg_by_fw(dm,
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PHYDM_HALMAC_CMD_DELAY_MS,
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addr,
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data,
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bitmask,
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(enum rf_path)0,
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delay_time);
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else
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phydm_set_reg_by_fw(dm,
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PHYDM_HALMAC_CMD_DELAY_US,
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addr,
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data,
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bitmask,
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(enum rf_path)0,
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delay_time);
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} else {
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phydm_set_reg_by_fw(dm,
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PHYDM_HALMAC_CMD_BB_W32,
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addr,
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data,
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bitmask,
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(enum rf_path)0,
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0);
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}
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} else {
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if (addr == 0xfe)
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#ifdef CONFIG_LONG_DELAY_ISSUE
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ODM_sleep_ms(50);
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#else
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ODM_delay_ms(50);
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#endif
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else if (addr == 0xfd)
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ODM_delay_ms(5);
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else if (addr == 0xfc)
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ODM_delay_ms(1);
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else if (addr == 0xfb)
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ODM_delay_us(50);
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else if (addr == 0xfa)
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ODM_delay_us(5);
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else if (addr == 0xf9)
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ODM_delay_us(1);
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else
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odm_set_bb_reg(dm, addr, bitmask, data);
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}
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PHYDM_DBG(dm, ODM_COMP_INIT, "===> config_bb: [PHY_REG] %08X %08X\n",
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addr, data);
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}
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void odm_config_bb_txpwr_lmt_8821c_ex(struct dm_struct *dm, u8 regulation,
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u8 band, u8 bandwidth, u8 rate_section,
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u8 rf_path, u8 channel, s8 power_limit)
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{
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#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
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phy_set_tx_power_limit_ex(dm, regulation, band, bandwidth, rate_section,
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rf_path, channel, power_limit);
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#endif
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#if 0
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PHY_SetTxPowerLimit_ex(dm, regulation, band, bandwidth, rate_section,
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rf_path, channel, power_limit);
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#endif
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}
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void odm_config_bb_txpwr_lmt_8821c(struct dm_struct *dm, u8 *regulation,
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u8 *band, u8 *bandwidth, u8 *rate_section,
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u8 *rf_path, u8 *channel, u8 *power_limit)
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{
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#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
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phy_set_tx_power_limit(dm, regulation, band,
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bandwidth, rate_section, rf_path, channel, power_limit);
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#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
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PHY_SetTxPowerLimit(dm, regulation, band,
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bandwidth, rate_section, rf_path, channel, power_limit);
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#endif
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}
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#endif
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