mirror of
https://github.com/morrownr/8821cu-20210916.git
synced 2024-11-01 09:15:22 +00:00
385 lines
13 KiB
C
385 lines
13 KiB
C
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/******************************************************************************
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*
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* Copyright(c) 2016 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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/*************************************************************
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* Description:
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*
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* This file is for 8192E TXBF mechanism
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*
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************************************************************/
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#include "mp_precomp.h"
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#include "../phydm_precomp.h"
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#ifdef PHYDM_BEAMFORMING_SUPPORT
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#if (RTL8192E_SUPPORT == 1)
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void hal_txbf_8192e_set_ndpa_rate(
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void *dm_void,
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u8 BW,
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u8 rate)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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odm_write_1byte(dm, REG_NDPA_OPT_CTRL_8192E, (rate << 2 | BW));
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}
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void hal_txbf_8192e_rf_mode(
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void *dm_void,
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struct _RT_BEAMFORMING_INFO *beam_info)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
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if (dm->rf_type == RF_1T1R)
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return;
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odm_set_rf_reg(dm, RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); /*RF mode table write enable*/
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odm_set_rf_reg(dm, RF_PATH_B, RF_WE_LUT, 0x80000, 0x1); /*RF mode table write enable*/
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if (beam_info->beamformee_su_cnt > 0) {
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/*Path_A*/
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odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0xfffff, 0x18000); /*Select RX mode 0x30=0x18000*/
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odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x0000f); /*Set Table data*/
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odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0x77fc2); /*@Enable TXIQGEN in RX mode*/
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/*Path_B*/
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odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, 0x18000); /*Select RX mode*/
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odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x0000f); /*Set Table data*/
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odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0x77fc2); /*@Enable TXIQGEN in RX mode*/
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} else {
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/*Path_A*/
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odm_set_rf_reg(dm, RF_PATH_A, RF_0x30, 0xfffff, 0x18000); /*Select RX mode*/
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odm_set_rf_reg(dm, RF_PATH_A, RF_0x31, 0xfffff, 0x0000f); /*Set Table data*/
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odm_set_rf_reg(dm, RF_PATH_A, RF_0x32, 0xfffff, 0x77f82); /*@Disable TXIQGEN in RX mode*/
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/*Path_B*/
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odm_set_rf_reg(dm, RF_PATH_B, RF_0x30, 0xfffff, 0x18000); /*Select RX mode*/
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odm_set_rf_reg(dm, RF_PATH_B, RF_0x31, 0xfffff, 0x0000f); /*Set Table data*/
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odm_set_rf_reg(dm, RF_PATH_B, RF_0x32, 0xfffff, 0x77f82); /*@Disable TXIQGEN in RX mode*/
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}
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odm_set_rf_reg(dm, RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); /*RF mode table write disable*/
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odm_set_rf_reg(dm, RF_PATH_B, RF_WE_LUT, 0x80000, 0x0); /*RF mode table write disable*/
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if (beam_info->beamformee_su_cnt > 0) {
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odm_set_bb_reg(dm, R_0x90c, MASKDWORD, 0x83321333);
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odm_set_bb_reg(dm, R_0xa04, MASKBYTE3, 0xc1);
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} else
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odm_set_bb_reg(dm, R_0x90c, MASKDWORD, 0x81121313);
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}
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void hal_txbf_8192e_fw_txbf_cmd(
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void *dm_void)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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u8 idx, period0 = 0, period1 = 0;
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u8 PageNum0 = 0xFF, PageNum1 = 0xFF;
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u8 u1_tx_bf_parm[3] = {0};
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struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
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for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) {
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if (beam_info->beamformee_entry[idx].beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED) {
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if (idx == 0) {
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if (beam_info->beamformee_entry[idx].is_sound)
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PageNum0 = 0xFE;
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else
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PageNum0 = 0xFF; /* stop sounding */
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period0 = (u8)(beam_info->beamformee_entry[idx].sound_period);
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} else if (idx == 1) {
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if (beam_info->beamformee_entry[idx].is_sound)
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PageNum1 = 0xFE;
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else
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PageNum1 = 0xFF; /* stop sounding */
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period1 = (u8)(beam_info->beamformee_entry[idx].sound_period);
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}
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}
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}
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u1_tx_bf_parm[0] = PageNum0;
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u1_tx_bf_parm[1] = PageNum1;
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u1_tx_bf_parm[2] = (period1 << 4) | period0;
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odm_fill_h2c_cmd(dm, PHYDM_H2C_TXBF, 3, u1_tx_bf_parm);
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PHYDM_DBG(dm, DBG_TXBF,
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"[%s] PageNum0 = %d period0 = %d, PageNum1 = %d period1 %d\n",
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__func__, PageNum0, period0, PageNum1, period1);
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}
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void hal_txbf_8192e_download_ndpa(
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void *dm_void,
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u8 idx)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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u8 u1b_tmp = 0, tmp_reg422 = 0, head_page;
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u8 bcn_valid_reg = 0, count = 0, dl_bcn_count = 0;
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boolean is_send_beacon = false;
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u8 tx_page_bndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8812;
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/*@default reseved 1 page for the IC type which is undefined.*/
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struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
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struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx;
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PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
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#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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*dm->is_fw_dw_rsvd_page_in_progress = true;
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#endif
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if (idx == 0)
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head_page = 0xFE;
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else
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head_page = 0xFE;
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phydm_get_hal_def_var_handler_interface(dm, HAL_DEF_TX_PAGE_BOUNDARY, (u8 *)&tx_page_bndy);
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/*Set REG_CR bit 8. DMA beacon by SW.*/
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u1b_tmp = odm_read_1byte(dm, REG_CR_8192E + 1);
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odm_write_1byte(dm, REG_CR_8192E + 1, (u1b_tmp | BIT(0)));
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/*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/
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tmp_reg422 = odm_read_1byte(dm, REG_FWHW_TXQ_CTRL_8192E + 2);
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odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8192E + 2, tmp_reg422 & (~BIT(6)));
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if (tmp_reg422 & BIT(6)) {
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PHYDM_DBG(dm, DBG_TXBF,
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"%s There is an adapter is sending beacon.\n",
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__func__);
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is_send_beacon = true;
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}
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/*TDECTRL[15:8] 0x209[7:0] = 0xFE/0xFD NDPA Head for TXDMA*/
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odm_write_1byte(dm, REG_DWBCN0_CTRL_8192E + 1, head_page);
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do {
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/*@Clear beacon valid check bit.*/
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bcn_valid_reg = odm_read_1byte(dm, REG_DWBCN0_CTRL_8192E + 2);
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odm_write_1byte(dm, REG_DWBCN0_CTRL_8192E + 2, (bcn_valid_reg | BIT(0)));
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/* @download NDPA rsvd page. */
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beamforming_send_ht_ndpa_packet(dm, p_beam_entry->mac_addr, p_beam_entry->sound_bw, BEACON_QUEUE);
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#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
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if (dm->support_interface == ODM_ITRF_PCIE) {
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u1b_tmp = odm_read_1byte(dm, REG_MGQ_TXBD_NUM_8192E + 3);
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count = 0;
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while ((count < 20) && (u1b_tmp & BIT(4))) {
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count++;
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ODM_delay_us(10);
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u1b_tmp = odm_read_1byte(dm, REG_MGQ_TXBD_NUM_8192E + 3);
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}
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odm_write_1byte(dm, REG_MGQ_TXBD_NUM_8192E + 3, u1b_tmp | BIT(4));
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}
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#endif
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/*@check rsvd page download OK.*/
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bcn_valid_reg = odm_read_1byte(dm, REG_DWBCN0_CTRL_8192E + 2);
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count = 0;
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while (!(bcn_valid_reg & BIT(0)) && count < 20) {
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count++;
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ODM_delay_us(10);
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bcn_valid_reg = odm_read_1byte(dm, REG_DWBCN0_CTRL_8192E + 2);
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}
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dl_bcn_count++;
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} while (!(bcn_valid_reg & BIT(0)) && dl_bcn_count < 5);
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if (!(bcn_valid_reg & BIT(0)))
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PHYDM_DBG(dm, DBG_TXBF, "%s Download RSVD page failed!\n",
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__func__);
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/*TDECTRL[15:8] 0x209[7:0] = 0xF9 Beacon Head for TXDMA*/
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odm_write_1byte(dm, REG_DWBCN0_CTRL_8192E + 1, tx_page_bndy);
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/*To make sure that if there exists an adapter which would like to send beacon.*/
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/*@If exists, the origianl value of 0x422[6] will be 1, we should check this to*/
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/*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause*/
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/*the beacon cannot be sent by HW.*/
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/*@2010.06.23. Added by tynli.*/
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if (is_send_beacon)
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odm_write_1byte(dm, REG_FWHW_TXQ_CTRL_8192E + 2, tmp_reg422);
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/*@Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/
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/*@Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/
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u1b_tmp = odm_read_1byte(dm, REG_CR_8192E + 1);
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odm_write_1byte(dm, REG_CR_8192E + 1, (u1b_tmp & (~BIT(0))));
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p_beam_entry->beamform_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSED;
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#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
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*dm->is_fw_dw_rsvd_page_in_progress = false;
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#endif
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}
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void hal_txbf_8192e_enter(
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void *dm_void,
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u8 bfer_bfee_idx)
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{
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struct dm_struct *dm = (struct dm_struct *)dm_void;
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u8 i = 0;
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u8 bfer_idx = (bfer_bfee_idx & 0xF0) >> 4;
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u8 bfee_idx = (bfer_bfee_idx & 0xF);
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u32 csi_param;
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struct _RT_BEAMFORMING_INFO *beamforming_info = &dm->beamforming_info;
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struct _RT_BEAMFORMEE_ENTRY beamformee_entry;
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struct _RT_BEAMFORMER_ENTRY beamformer_entry;
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u16 sta_id = 0;
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PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
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hal_txbf_8192e_rf_mode(dm, beamforming_info);
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if (dm->rf_type == RF_2T2R)
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odm_write_4byte(dm, 0xd80, 0x00000000); /*nc =2*/
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if (beamforming_info->beamformer_su_cnt > 0 && bfer_idx < BEAMFORMER_ENTRY_NUM) {
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beamformer_entry = beamforming_info->beamformer_entry[bfer_idx];
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/*Sounding protocol control*/
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odm_write_1byte(dm, REG_SND_PTCL_CTRL_8192E, 0xCB);
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/*@MAC address/Partial AID of Beamformer*/
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if (bfer_idx == 0) {
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for (i = 0; i < 6; i++)
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odm_write_1byte(dm, (REG_ASSOCIATED_BFMER0_INFO_8192E + i), beamformer_entry.mac_addr[i]);
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} else {
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for (i = 0; i < 6; i++)
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odm_write_1byte(dm, (REG_ASSOCIATED_BFMER1_INFO_8192E + i), beamformer_entry.mac_addr[i]);
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}
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/*@CSI report parameters of Beamformer Default use nc = 2*/
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csi_param = 0x03090309;
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odm_write_4byte(dm, REG_CSI_RPT_PARAM_BW20_8192E, csi_param);
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odm_write_4byte(dm, REG_CSI_RPT_PARAM_BW40_8192E, csi_param);
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odm_write_4byte(dm, REG_CSI_RPT_PARAM_BW80_8192E, csi_param);
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/*Timeout value for MAC to leave NDP_RX_standby_state (60 us, Test chip) (80 us, MP chip)*/
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odm_write_1byte(dm, REG_SND_PTCL_CTRL_8192E + 3, 0x50);
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}
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if (beamforming_info->beamformee_su_cnt > 0 && bfee_idx < BEAMFORMEE_ENTRY_NUM) {
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beamformee_entry = beamforming_info->beamformee_entry[bfee_idx];
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if (phydm_acting_determine(dm, phydm_acting_as_ibss))
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sta_id = beamformee_entry.mac_id;
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else
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sta_id = beamformee_entry.p_aid;
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PHYDM_DBG(dm, DBG_TXBF, "[%s], sta_id=0x%X\n", __func__,
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sta_id);
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/*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/
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if (bfee_idx == 0) {
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odm_write_2byte(dm, REG_TXBF_CTRL_8192E, sta_id);
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odm_write_1byte(dm, REG_TXBF_CTRL_8192E + 3, odm_read_1byte(dm, REG_TXBF_CTRL_8192E + 3) | BIT(4) | BIT(6) | BIT(7));
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} else
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odm_write_2byte(dm, REG_TXBF_CTRL_8192E + 2, sta_id | BIT(12) | BIT(14) | BIT(15));
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/*@CSI report parameters of Beamformee*/
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if (bfee_idx == 0) {
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/*@Get BIT24 & BIT25*/
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u8 tmp = odm_read_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E + 3) & 0x3;
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odm_write_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E + 3, tmp | 0x60);
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odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E, sta_id | BIT(9));
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} else {
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||
|
|
/*Set BIT25*/
|
||
|
|
odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E + 2, sta_id | 0xE200);
|
||
|
|
}
|
||
|
|
phydm_beamforming_notify(dm);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
void hal_txbf_8192e_leave(
|
||
|
|
void *dm_void,
|
||
|
|
u8 idx)
|
||
|
|
{
|
||
|
|
struct dm_struct *dm = (struct dm_struct *)dm_void;
|
||
|
|
struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
|
||
|
|
|
||
|
|
hal_txbf_8192e_rf_mode(dm, beam_info);
|
||
|
|
|
||
|
|
/* @Clear P_AID of Beamformee
|
||
|
|
* Clear MAC addresss of Beamformer
|
||
|
|
* Clear Associated Bfmee Sel
|
||
|
|
*/
|
||
|
|
if (beam_info->beamform_cap == BEAMFORMING_CAP_NONE)
|
||
|
|
odm_write_1byte(dm, REG_SND_PTCL_CTRL_8192E, 0xC8);
|
||
|
|
|
||
|
|
if (idx == 0) {
|
||
|
|
odm_write_2byte(dm, REG_TXBF_CTRL_8192E, 0);
|
||
|
|
odm_write_4byte(dm, REG_ASSOCIATED_BFMER0_INFO_8192E, 0);
|
||
|
|
odm_write_2byte(dm, REG_ASSOCIATED_BFMER0_INFO_8192E + 4, 0);
|
||
|
|
odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E, 0);
|
||
|
|
} else {
|
||
|
|
odm_write_2byte(dm, REG_TXBF_CTRL_8192E + 2, odm_read_1byte(dm, REG_TXBF_CTRL_8192E + 2) & 0xF000);
|
||
|
|
odm_write_4byte(dm, REG_ASSOCIATED_BFMER1_INFO_8192E, 0);
|
||
|
|
odm_write_2byte(dm, REG_ASSOCIATED_BFMER1_INFO_8192E + 4, 0);
|
||
|
|
odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E + 2, odm_read_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8192E + 2) & 0x60);
|
||
|
|
}
|
||
|
|
|
||
|
|
PHYDM_DBG(dm, DBG_TXBF, "[%s] idx %d\n", __func__, idx);
|
||
|
|
}
|
||
|
|
|
||
|
|
void hal_txbf_8192e_status(
|
||
|
|
void *dm_void,
|
||
|
|
u8 idx)
|
||
|
|
{
|
||
|
|
struct dm_struct *dm = (struct dm_struct *)dm_void;
|
||
|
|
u16 beam_ctrl_val;
|
||
|
|
u32 beam_ctrl_reg;
|
||
|
|
struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
|
||
|
|
struct _RT_BEAMFORMEE_ENTRY beamform_entry = beam_info->beamformee_entry[idx];
|
||
|
|
|
||
|
|
if (phydm_acting_determine(dm, phydm_acting_as_ibss))
|
||
|
|
beam_ctrl_val = beamform_entry.mac_id;
|
||
|
|
else
|
||
|
|
beam_ctrl_val = beamform_entry.p_aid;
|
||
|
|
|
||
|
|
if (idx == 0)
|
||
|
|
beam_ctrl_reg = REG_TXBF_CTRL_8192E;
|
||
|
|
else {
|
||
|
|
beam_ctrl_reg = REG_TXBF_CTRL_8192E + 2;
|
||
|
|
beam_ctrl_val |= BIT(12) | BIT(14) | BIT(15);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (beamform_entry.beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSED && beam_info->apply_v_matrix == true) {
|
||
|
|
if (beamform_entry.sound_bw == CHANNEL_WIDTH_20)
|
||
|
|
beam_ctrl_val |= BIT(9);
|
||
|
|
else if (beamform_entry.sound_bw == CHANNEL_WIDTH_40)
|
||
|
|
beam_ctrl_val |= BIT(10);
|
||
|
|
} else
|
||
|
|
beam_ctrl_val &= ~(BIT(9) | BIT(10) | BIT(11));
|
||
|
|
|
||
|
|
odm_write_2byte(dm, beam_ctrl_reg, beam_ctrl_val);
|
||
|
|
|
||
|
|
PHYDM_DBG(dm, DBG_TXBF,
|
||
|
|
"[%s] idx %d beam_ctrl_reg %x beam_ctrl_val %x\n", __func__,
|
||
|
|
idx, beam_ctrl_reg, beam_ctrl_val);
|
||
|
|
}
|
||
|
|
|
||
|
|
void hal_txbf_8192e_fw_tx_bf(
|
||
|
|
void *dm_void,
|
||
|
|
u8 idx)
|
||
|
|
{
|
||
|
|
struct dm_struct *dm = (struct dm_struct *)dm_void;
|
||
|
|
struct _RT_BEAMFORMING_INFO *beam_info = &dm->beamforming_info;
|
||
|
|
struct _RT_BEAMFORMEE_ENTRY *p_beam_entry = beam_info->beamformee_entry + idx;
|
||
|
|
|
||
|
|
PHYDM_DBG(dm, DBG_TXBF, "[%s] Start!\n", __func__);
|
||
|
|
|
||
|
|
if (p_beam_entry->beamform_entry_state == BEAMFORMING_ENTRY_STATE_PROGRESSING)
|
||
|
|
hal_txbf_8192e_download_ndpa(dm, idx);
|
||
|
|
|
||
|
|
hal_txbf_8192e_fw_txbf_cmd(dm);
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif /* @#if (RTL8192E_SUPPORT == 1)*/
|
||
|
|
|
||
|
|
#endif
|