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rtl8812au
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Merge pull request #386 from pecastro/v5.6.4-pec-add-8814 

Add RTL8814AU support to v5.6.4 branch
v5.6.4
Christian Bremvåg 2019-08-17 22:03:27 +02:00 committed by GitHub
parent 3da4742d19 7e494793c2
commit f13efdd4cd
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
53 changed files with 44540 additions and 51 deletions
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7
Makefile
View File

@ -46,7 +46,7 @@ CONFIG_RTL8812A = y
CONFIG_RTL8821A = n
CONFIG_RTL8192E = n
CONFIG_RTL8723B = n
CONFIG_RTL8814A = n
CONFIG_RTL8814A = y
CONFIG_RTL8723C = n
CONFIG_RTL8188F = n
CONFIG_RTL8188GTV = n
@ -218,7 +218,7 @@ ifeq ($(CONFIG_PCI_HCI), y)
HCI_NAME = pci
endif
ifeq ($(CONFIG_RTL8812A)_$(CONFIG_RTL8821A)_$(CONFIG_RTL8814A), y_n_n)
ifeq ($(CONFIG_RTL8812A)_$(CONFIG_RTL8821A)_$(CONFIG_RTL8814A), y_n_y)
EXTRA_CFLAGS += -DDRV_NAME=\"rtl88xxau\"
ifeq ($(CONFIG_USB_HCI), y)
@ -320,7 +320,7 @@ EXTRA_CFLAGS += -DCONFIG_RTL8188E
_HAL_INTFS_FILES += hal/HalPwrSeqCmd.o \
hal/$(RTL871X)/Hal8188EPwrSeq.o\
hal/$(RTL871X)/$(RTL871X)_xmit.o\
hal/$(RTL871X)/$(RTL871X)_xmit.o\
hal/$(RTL871X)/$(RTL871X)_sreset.o
_HAL_INTFS_FILES += hal/$(RTL871X)/$(RTL871X)_hal_init.o \
@ -2405,4 +2405,3 @@ clean:
rm -fr *.mod.c *.mod *.o .*.cmd *.ko *~
rm -fr .tmp_versions
endif

93
hal/efuse/rtl8814a/HalEfuseMask8814A_PCIE.c 100644
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@ -0,0 +1,93 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#include <drv_types.h>
#include "HalEfuseMask8814A_PCIE.h"
/******************************************************************************
* MPCIE.TXT
******************************************************************************/
u1Byte Array_MP_8814A_MPCIE[] = {
0xFF,
0xFF,
0xFF,
0xFF,
0xFF,
0xFF,
0xFF,
0xFF,
0xFF,
0xFF,
0xFF,
0xFF,
0xF3,
0xFF,
0x10,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
};
u2Byte
EFUSE_GetArrayLen_MP_8814A_MPCIE(VOID)
{
return sizeof(Array_MP_8814A_MPCIE)/sizeof(u1Byte);
}
VOID
EFUSE_GetMaskArray_MP_8814A_MPCIE(pu1Byte Array)
{
u2Byte len = EFUSE_GetArrayLen_MP_8814A_MPCIE(), i = 0;
for (i = 0; i < len; ++i)
Array[i] = Array_MP_8814A_MPCIE[i];
}
BOOLEAN
EFUSE_IsAddressMasked_MP_8814A_MPCIE(u2Byte Offset)
{
int r = Offset/16;
int c = (Offset%16) / 2;
int result = 0;
if (c < 4) /*Upper double word*/
result = (Array_MP_8814A_MPCIE[r] & (0x10 << c));
else
result = (Array_MP_8814A_MPCIE[r] & (0x01 << (c-4)));
return (result > 0) ? 0 : 1;
}

33
hal/efuse/rtl8814a/HalEfuseMask8814A_PCIE.h 100644
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@ -0,0 +1,33 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/******************************************************************************
* MPCIE.TXT
******************************************************************************/
u2Byte EFUSE_GetArrayLen_MP_8814A_MPCIE(VOID);
VOID EFUSE_GetMaskArray_MP_8814A_MPCIE(pu1Byte Array);
BOOLEAN EFUSE_IsAddressMasked_MP_8814A_MPCIE(u2Byte Offset);

90
hal/efuse/rtl8814a/HalEfuseMask8814A_USB.c 100644
View File

@ -0,0 +1,90 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#include <drv_types.h>
#include "HalEfuseMask8814A_USB.h"
/******************************************************************************
* MUSB.TXT
******************************************************************************/
u1Byte Array_MP_8814A_MUSB[] = {
0xFF,
0xFF,
0xFF,
0xFF,
0xFF,
0xFF,
0xFF,
0xFF,
0xFF,
0xFF,
0xFF,
0xFF,
0xF3,
0x7F,
0xFF,
0xFF,
0xFF,
0x70,
0x04,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
};
u2Byte EFUSE_GetArrayLen_MP_8814A_MUSB(VOID)
{
return sizeof(Array_MP_8814A_MUSB)/sizeof(u1Byte);
}
VOID EFUSE_GetMaskArray_MP_8814A_MUSB(pu1Byte Array)
{
u2Byte len = EFUSE_GetArrayLen_MP_8814A_MUSB(), i = 0;
for (i = 0; i < len; ++i)
Array[i] = Array_MP_8814A_MUSB[i];
}
BOOLEAN EFUSE_IsAddressMasked_MP_8814A_MUSB(u2Byte Offset)
{
int r = Offset/16;
int c = (Offset%16) / 2;
int result = 0;
if (c < 4) /*Upper double word*/
result = (Array_MP_8814A_MUSB[r] & (0x10 << c));
else
result = (Array_MP_8814A_MUSB[r] & (0x01 << (c-4)));
return (result > 0) ? 0 : 1;
}

33
hal/efuse/rtl8814a/HalEfuseMask8814A_USB.h 100644
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@ -0,0 +1,33 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/******************************************************************************
* MUSB.TXT
******************************************************************************/
u2Byte EFUSE_GetArrayLen_MP_8814A_MUSB(VOID);
VOID EFUSE_GetMaskArray_MP_8814A_MUSB(pu1Byte Array);
BOOLEAN EFUSE_IsAddressMasked_MP_8814A_MUSB(u2Byte Offset);

1745
hal/phydm/halrf/rtl8814a/halrf_8814a_ap.c 100644
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File diff suppressed because it is too large Load Diff

108
hal/phydm/halrf/rtl8814a/halrf_8814a_ap.h 100644
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@ -0,0 +1,108 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HALRF_8814A_H__
#define __HALRF_8814A_H__
/*--------------------------Define Parameters-------------------------------*/
#define IQK_DELAY_TIME_8814A 10 //ms
#define index_mapping_NUM_8814A 15
#define AVG_THERMAL_NUM_8814A 4
#define RF_T_METER_8814A 0x42
#define MAX_PATH_NUM_8814A 4
#include "../halphyrf_ap.h"
void configure_txpower_track_8814a(
struct txpwrtrack_cfg *config
);
void
get_delta_swing_table_8814a(
void *dm_void,
u8* *temperature_up_a,
u8* *temperature_down_a,
u8* *temperature_up_b,
u8* *temperature_down_b
);
VOID
get_delta_swing_table_8814a_patch_cd(
void *dm_void,
u8* *temperature_up_c,
u8* *temperature_down_c,
u8* *temperature_up_d,
u8* *temperature_down_d
);
void
odm_tx_pwr_track_set_pwr8814a(
struct dm_struct *dm,
enum pwrtrack_method method,
u8 rf_path,
u8 channel_mapped_index
);
u1Byte
check_rd_gain_offset(
struct dm_struct *dm,
enum pwrtrack_method method,
u8 rf_path,
);
//
// LC calibrate
//
void
phy_lc_calibrate_8814a(
void *dm_void
);
void
phy_lc_calibrate_8814a(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
struct dm_struct *dm,
#else
void *adapter,
#endif
boolean is2T
);
//
// AP calibrate
//
void
phy_ap_calibrate_8814a(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
struct dm_struct *dm,
#else
void *adapter,
#endif
s1Byte delta);
void
phy_digital_predistortion_8814a(void *adapter);
#endif // #ifndef __HAL_PHY_RF_8814A_H__

553
hal/phydm/halrf/rtl8814a/halrf_8814a_ce.c 100644
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@ -0,0 +1,553 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#include "mp_precomp.h"
#include "../../phydm_precomp.h"
/*---------------------------Define Local Constant---------------------------*/
// 2010/04/25 MH Define the max tx power tracking tx agc power.
#define ODM_TXPWRTRACK_MAX_IDX_8814A 6
/*---------------------------Define Local Constant---------------------------*/
//3============================================================
//3 Tx Power Tracking
//3============================================================
// Add CheckRFGainOffset By YuChen to make sure that RF gain offset will not over upperbound 4'b1010
u8
CheckRFGainOffset(
struct dm_struct *dm,
enum pwrtrack_method Method,
u8 RFPath
)
{
s1Byte UpperBound = 10, LowerBound = -5; // 4'b1010 = 10
s1Byte Final_RF_Index = 0;
boolean bPositive = false;
u32 bit_mask = 0;
u8 Final_OFDM_Swing_Index = 0, TxScalingUpperBound = 28, TxScalingLowerBound = 4;// upper bound +2dB, lower bound -10dB
struct dm_rf_calibration_struct * cali_info = &(dm->rf_calibrate_info);
if(Method == MIX_MODE) //normal Tx power tracking
{
PHYDM_DBG(dm,DBG_COMP_MCC,"is 8814 MP chip\n");
bit_mask = BIT(19);
cali_info->absolute_ofdm_swing_idx[RFPath] = cali_info->absolute_ofdm_swing_idx[RFPath] + cali_info->kfree_offset[RFPath];
PHYDM_DBG(dm, DBG_COMP_MCC,"=========================== [Path-%d] TXBB Offset============================\n", RFPath);
PHYDM_DBG(dm, DBG_COMP_MCC,"absolute_ofdm_swing_idx[RFPath](%d) = absolute_ofdm_swing_idx[RFPath](%d) + kfree_offset[RFPath](%d), RFPath=%d\n", cali_info->absolute_ofdm_swing_idx[RFPath], cali_info->absolute_ofdm_swing_idx[RFPath], cali_info->kfree_offset[RFPath], RFPath);
if (cali_info->absolute_ofdm_swing_idx[RFPath] >= 0) /* check if RF_Index is positive or not*/
bPositive = true;
else
bPositive = false;
odm_set_rf_reg(dm, RFPath, rRF_TxGainOffset, bit_mask, bPositive);
bit_mask = BIT(18)|BIT(17)|BIT(16)|BIT(15);
Final_RF_Index = cali_info->absolute_ofdm_swing_idx[RFPath] / 2; /*TxBB 1 step equal 1dB, BB swing 1step equal 0.5dB*/
}
if(Final_RF_Index > UpperBound) //Upper bound = 10dB, if more htan upper bound, then move to bb swing max = +2dB
{
odm_set_rf_reg(dm, RFPath, rRF_TxGainOffset, bit_mask, UpperBound); //set RF Reg0x55 per path
Final_OFDM_Swing_Index = cali_info->default_ofdm_index + (cali_info->absolute_ofdm_swing_idx[RFPath] - (UpperBound << 1));
PHYDM_DBG(dm, DBG_COMP_MCC,"Final_OFDM_Swing_Index(%d) = default_ofdm_index(%d) + (absolute_ofdm_swing_idx[RFPath](%d) - (UpperBound(%d) << 1)), RFPath=%d\n", Final_OFDM_Swing_Index, cali_info->default_ofdm_index, cali_info->absolute_ofdm_swing_idx[RFPath], UpperBound, RFPath);
if (Final_OFDM_Swing_Index > TxScalingUpperBound) { /* bb swing upper bound = +2dB */
Final_OFDM_Swing_Index = TxScalingUpperBound;
PHYDM_DBG(dm, DBG_COMP_MCC,"Final_OFDM_Swing_Index(%d) > TxScalingUpperBound(%d) Final_OFDM_Swing_Index = TxScalingUpperBound\n", Final_OFDM_Swing_Index, TxScalingUpperBound);
PHYDM_DBG(dm, DBG_COMP_MCC,"===========================================================================\n");
}
return Final_OFDM_Swing_Index;
}
else if(Final_RF_Index < LowerBound) // lower bound = -5dB
{
odm_set_rf_reg(dm, RFPath, rRF_TxGainOffset, bit_mask, (-1)*(LowerBound)); //set RF Reg0x55 per path
Final_OFDM_Swing_Index = cali_info->default_ofdm_index - ((LowerBound<<1) - cali_info->absolute_ofdm_swing_idx[RFPath]);
PHYDM_DBG(dm, DBG_COMP_MCC,"Final_OFDM_Swing_Index(%d) = default_ofdm_index(%d) - ((LowerBound(%d)<<1) - absolute_ofdm_swing_idx[RFPath](%d)), RFPath=%d\n", Final_OFDM_Swing_Index, cali_info->default_ofdm_index, LowerBound, cali_info->absolute_ofdm_swing_idx[RFPath], RFPath);
if (Final_OFDM_Swing_Index < TxScalingLowerBound) { /* BB swing lower bound = -10dB */
Final_OFDM_Swing_Index = TxScalingLowerBound;
PHYDM_DBG(dm, DBG_COMP_MCC,"Final_OFDM_Swing_Index(%d) > TxScalingLowerBound(%d) Final_OFDM_Swing_Index = TxScalingLowerBound\n", Final_OFDM_Swing_Index, TxScalingLowerBound);
PHYDM_DBG(dm, DBG_COMP_MCC,"===========================================================================\n");
}
return Final_OFDM_Swing_Index;
}
else // normal case
{
if(bPositive == true)
odm_set_rf_reg(dm, RFPath, rRF_TxGainOffset, bit_mask, Final_RF_Index); //set RF Reg0x55 per path
else
odm_set_rf_reg(dm, RFPath, rRF_TxGainOffset, bit_mask, (-1)*Final_RF_Index); //set RF Reg0x55 per path
Final_OFDM_Swing_Index = cali_info->default_ofdm_index + (cali_info->absolute_ofdm_swing_idx[RFPath])%2;
PHYDM_DBG(dm, DBG_COMP_MCC,"Final_OFDM_Swing_Index(%d) = default_ofdm_index(%d) + (absolute_ofdm_swing_idx[RFPath])//2(%d), RFPath=%d\n", Final_OFDM_Swing_Index, cali_info->default_ofdm_index, (cali_info->absolute_ofdm_swing_idx[RFPath])%2, RFPath);
PHYDM_DBG(dm, DBG_COMP_MCC,"===========================================================================\n");
return Final_OFDM_Swing_Index;
}
return false;
}
VOID
ODM_TxPwrTrackSetPwr8814A(
IN PVOID pDM_VOID,
enum pwrtrack_method Method,
u8 RFPath,
u8 ChannelMappedIndex
)
{
struct dm_struct * dm = (struct dm_struct *)pDM_VOID;
void * adapter = dm->adapter;
PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
struct dm_rf_calibration_struct * cali_info = &(dm->rf_calibrate_info);
u8 Final_OFDM_Swing_Index = 0;
if (Method == MIX_MODE)
{
PHYDM_DBG(dm, DBG_COMP_MCC,"cali_info->default_ofdm_index=%d, cali_info->absolute_ofdm_swing_idx[RFPath]=%d, RF_Path = %d\n", cali_info->default_ofdm_index, cali_info->absolute_ofdm_swing_idx[RFPath], RFPath);
Final_OFDM_Swing_Index = CheckRFGainOffset(dm, MIX_MODE, RFPath);
}
else if(Method == TSSI_MODE)
{
odm_set_rf_reg(dm, RFPath, rRF_TxGainOffset, BIT(18)|BIT(17)|BIT(16)|BIT(15), 0);
}
else if(Method == BBSWING) // use for mp driver clean power tracking status
{
cali_info->absolute_ofdm_swing_idx[RFPath] = cali_info->absolute_ofdm_swing_idx[RFPath] + cali_info->kfree_offset[RFPath];
Final_OFDM_Swing_Index = cali_info->default_ofdm_index + (cali_info->absolute_ofdm_swing_idx[RFPath]);
odm_set_rf_reg(dm, RFPath, rRF_TxGainOffset, BIT(18)|BIT(17)|BIT(16)|BIT(15), 0);
}
if((Method == MIX_MODE) || (Method == BBSWING))
{
PHYDM_DBG(dm, DBG_COMP_MCC,"=========================== [Path-%d] BBSWING Offset============================\n", RFPath);
switch(RFPath)
{
case RF_PATH_A:
odm_set_bb_reg(dm, rA_TxScale_Jaguar, 0xFFE00000, tx_scaling_table_jaguar[Final_OFDM_Swing_Index]); //set BBswing
PHYDM_DBG(dm,DBG_COMP_MCC,"******Path_A Compensate with BBSwing , Final_OFDM_Swing_Index = %d \n", Final_OFDM_Swing_Index);
break;
case RF_PATH_B:
odm_set_bb_reg(dm, rB_TxScale_Jaguar, 0xFFE00000, tx_scaling_table_jaguar[Final_OFDM_Swing_Index]); //set BBswing
PHYDM_DBG(dm,DBG_COMP_MCC,"******Path_B Compensate with BBSwing , Final_OFDM_Swing_Index = %d \n", Final_OFDM_Swing_Index);
break;
case RF_PATH_C:
odm_set_bb_reg(dm, rC_TxScale_Jaguar2, 0xFFE00000, tx_scaling_table_jaguar[Final_OFDM_Swing_Index]); //set BBswing
PHYDM_DBG(dm,DBG_COMP_MCC,"******Path_C Compensate with BBSwing , Final_OFDM_Swing_Index = %d \n", Final_OFDM_Swing_Index);
break;
case RF_PATH_D:
odm_set_bb_reg(dm, rD_TxScale_Jaguar2, 0xFFE00000, tx_scaling_table_jaguar[Final_OFDM_Swing_Index]); //set BBswing
PHYDM_DBG(dm,DBG_COMP_MCC,"******Path_D Compensate with BBSwing , Final_OFDM_Swing_Index = %d \n", Final_OFDM_Swing_Index);
break;
default:
PHYDM_DBG(dm,DBG_COMP_MCC,"Wrong Path name!!!! \n");
break;
}
PHYDM_DBG(dm, DBG_COMP_MCC,"===========================================================================\n");
}
return;
} // ODM_TxPwrTrackSetPwr8814A
VOID
GetDeltaSwingTable_8814A(
IN PVOID pDM_VOID,
u8* *TemperatureUP_A,
u8* *TemperatureDOWN_A,
u8* *TemperatureUP_B,
u8* *TemperatureDOWN_B
)
{
struct dm_struct * dm = (struct dm_struct *)pDM_VOID;
struct _ADAPTER *adapter = dm->adapter;
struct dm_rf_calibration_struct * cali_info = &(dm->rf_calibrate_info);
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
u8 TxRate = 0xFF;
u8 channel = hal_data->current_channel;
if (*(dm->mp_mode) == true) {
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
#if (MP_DRIVER == 1)
PMPT_CONTEXT pMptCtx = &(adapter->mpt_ctx);
TxRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
#endif
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
PMPT_CONTEXT pMptCtx = &(adapter->mppriv.mpt_ctx);
TxRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
#endif
#endif
} else {
u2Byte rate = *(dm->forced_data_rate);
if (!rate) { /*auto rate*/
if (dm->tx_rate != 0xFF) {
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
TxRate = adapter->HalFunc.GetHwRateFromMRateHandler(dm->tx_rate);
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
TxRate = hw_rate_to_m_rate(dm->tx_rate);
#endif
}
} else { /*force rate*/
TxRate = (u8)rate;
}
}
PHYDM_DBG(dm, DBG_COMP_MCC,"Power Tracking TxRate=0x%X\n", TxRate);
if (1 <= channel && channel <= 14) {
if (IS_CCK_RATE(TxRate)) {
*TemperatureUP_A = cali_info->delta_swing_table_idx_2g_cck_a_p;
*TemperatureDOWN_A = cali_info->delta_swing_table_idx_2g_cck_a_n;
*TemperatureUP_B = cali_info->delta_swing_table_idx_2g_cck_b_p;
*TemperatureDOWN_B = cali_info->delta_swing_table_idx_2g_cck_b_n;
} else {
*TemperatureUP_A = cali_info->delta_swing_table_idx_2ga_p;
*TemperatureDOWN_A = cali_info->delta_swing_table_idx_2ga_n;
*TemperatureUP_B = cali_info->delta_swing_table_idx_2gb_p;
*TemperatureDOWN_B = cali_info->delta_swing_table_idx_2gb_n;
}
} else if (36 <= channel && channel <= 64) {
*TemperatureUP_A = cali_info->delta_swing_table_idx_5ga_p[0];
*TemperatureDOWN_A = cali_info->delta_swing_table_idx_5ga_n[0];
*TemperatureUP_B = cali_info->delta_swing_table_idx_5gb_p[0];
*TemperatureDOWN_B = cali_info->delta_swing_table_idx_5gb_n[0];
} else if (100 <= channel && channel <= 144) {
*TemperatureUP_A = cali_info->delta_swing_table_idx_5ga_p[1];
*TemperatureDOWN_A = cali_info->delta_swing_table_idx_5ga_n[1];
*TemperatureUP_B = cali_info->delta_swing_table_idx_5gb_p[1];
*TemperatureDOWN_B = cali_info->delta_swing_table_idx_5gb_n[1];
} else if (149 <= channel && channel <= 173) {
*TemperatureUP_A = cali_info->delta_swing_table_idx_5ga_p[2];
*TemperatureDOWN_A = cali_info->delta_swing_table_idx_5ga_n[2];
*TemperatureUP_B = cali_info->delta_swing_table_idx_5gb_p[2];
*TemperatureDOWN_B = cali_info->delta_swing_table_idx_5gb_n[2];
} else {
*TemperatureUP_A = (u8*)delta_swing_table_idx_2ga_p_8188e;
*TemperatureDOWN_A = (u8*)delta_swing_table_idx_2ga_n_8188e;
*TemperatureUP_B = (u8*)delta_swing_table_idx_2ga_p_8188e;
*TemperatureDOWN_B = (u8*)delta_swing_table_idx_2ga_n_8188e;
}
return;
}
VOID
GetDeltaSwingTable_8814A_PathCD(
IN PVOID pDM_VOID,
u8* *TemperatureUP_C,
u8* *TemperatureDOWN_C,
u8* *TemperatureUP_D,
u8* *TemperatureDOWN_D
)
{
struct dm_struct * dm = (struct dm_struct *)pDM_VOID;
struct _ADAPTER *adapter = dm->adapter;
struct dm_rf_calibration_struct * cali_info = &(dm->rf_calibrate_info);
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
u8 TxRate = 0xFF;
u8 channel = hal_data->current_channel;
if (*(dm->mp_mode) == true) {
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
#if (MP_DRIVER == 1)
PMPT_CONTEXT pMptCtx = &(adapter->mpt_ctx);
TxRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
#endif
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
PMPT_CONTEXT pMptCtx = &(adapter->mppriv.mpt_ctx);
TxRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
#endif
#endif
} else {
u2Byte rate = *(dm->forced_data_rate);
if (!rate) { /*auto rate*/
if (dm->tx_rate != 0xFF) {
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
TxRate = adapter->HalFunc.GetHwRateFromMRateHandler(dm->tx_rate);
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
TxRate = hw_rate_to_m_rate(dm->tx_rate);
#endif
}
} else { /*force rate*/
TxRate = (u8)rate;
}
}
PHYDM_DBG(dm, DBG_COMP_MCC,"Power Tracking TxRate=0x%X\n", TxRate);
if ( 1 <= channel && channel <= 14) {
if (IS_CCK_RATE(TxRate)) {
*TemperatureUP_C = cali_info->delta_swing_table_idx_2g_cck_c_p;
*TemperatureDOWN_C = cali_info->delta_swing_table_idx_2g_cck_c_n;
*TemperatureUP_D = cali_info->delta_swing_table_idx_2g_cck_d_p;
*TemperatureDOWN_D = cali_info->delta_swing_table_idx_2g_cck_d_n;
} else {
*TemperatureUP_C = cali_info->delta_swing_table_idx_2gc_p;
*TemperatureDOWN_C = cali_info->delta_swing_table_idx_2gc_n;
*TemperatureUP_D = cali_info->delta_swing_table_idx_2gd_p;
*TemperatureDOWN_D = cali_info->delta_swing_table_idx_2gd_n;
}
} else if (36 <= channel && channel <= 64) {
*TemperatureUP_C = cali_info->delta_swing_table_idx_5gc_p[0];
*TemperatureDOWN_C = cali_info->delta_swing_table_idx_5gc_n[0];
*TemperatureUP_D = cali_info->delta_swing_table_idx_5gd_p[0];
*TemperatureDOWN_D = cali_info->delta_swing_table_idx_5gd_n[0];
} else if (100 <= channel && channel <= 144) {
*TemperatureUP_C = cali_info->delta_swing_table_idx_5gc_p[1];
*TemperatureDOWN_C = cali_info->delta_swing_table_idx_5gc_n[1];
*TemperatureUP_D = cali_info->delta_swing_table_idx_5gd_p[1];
*TemperatureDOWN_D = cali_info->delta_swing_table_idx_5gd_n[1];
} else if (149 <= channel && channel <= 173) {
*TemperatureUP_C = cali_info->delta_swing_table_idx_5gc_p[2];
*TemperatureDOWN_C = cali_info->delta_swing_table_idx_5gc_n[2];
*TemperatureUP_D = cali_info->delta_swing_table_idx_5gd_p[2];
*TemperatureDOWN_D = cali_info->delta_swing_table_idx_5gd_n[2];
} else {
*TemperatureUP_C = (u8*)delta_swing_table_idx_2ga_p_8188e;
*TemperatureDOWN_C = (u8*)delta_swing_table_idx_2ga_n_8188e;
*TemperatureUP_D = (u8*)delta_swing_table_idx_2ga_p_8188e;
*TemperatureDOWN_D = (u8*)delta_swing_table_idx_2ga_n_8188e;
}
return;
}
void configure_txpower_track_8814a(
struct txpwrtrack_cfg *pConfig
)
{
pConfig->swing_table_size_cck = CCK_TABLE_SIZE;
pConfig->swing_table_size_ofdm = OFDM_TABLE_SIZE;
pConfig->threshold_iqk = 8;
pConfig->average_thermal_num = AVG_THERMAL_NUM_8814A;
pConfig->rf_path_count = MAX_PATH_NUM_8814A;
pConfig->thermal_reg_addr = RF_T_METER_88E;
pConfig->odm_tx_pwr_track_set_pwr = ODM_TxPwrTrackSetPwr8814A;
pConfig->do_iqk = DoIQK_8814A;
pConfig->phy_lc_calibrate = phy_lc_calibrate_8814a;
pConfig->get_delta_swing_table = GetDeltaSwingTable_8814A;
pConfig->get_delta_swing_table8814only = GetDeltaSwingTable_8814A_PathCD;
}
VOID
_phy_lc_calibrate_8814a(
IN struct dm_struct * dm,
IN boolean is2T
)
{
u32 /*RF_Amode=0, RF_Bmode=0,*/ LC_Cal = 0, tmp = 0, cnt;
//Check continuous TX and Packet TX
u32 reg0x914 = odm_read_4byte(dm, rSingleTone_ContTx_Jaguar);;
// Backup RF reg18.
if((reg0x914 & 0x70000) == 0)
odm_write_1byte(dm, REG_TXPAUSE, 0xFF);
//3 3. Read RF reg18
LC_Cal = odm_get_rf_reg(dm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask);
//3 4. Set LC calibration begin bit15
odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, 0x1b126);
ODM_delay_ms(100);
for (cnt = 0; cnt < 100; cnt++) {
if (odm_get_rf_reg(dm, RF_PATH_A, RF_CHNLBW, 0x8000) != 0x1)
break;
ODM_delay_ms(10);
}
PHYDM_DBG(dm, DBG_CMN,"retry cnt = %d\n", cnt);
odm_set_rf_reg( dm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, 0x13126);
odm_set_rf_reg( dm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, 0x13124);
//3 Restore original situation
if((reg0x914 & 70000) == 0)
odm_write_1byte(dm, REG_TXPAUSE, 0x00);
// Recover channel number
odm_set_rf_reg(dm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, LC_Cal);
//DbgPrint("Call %s\n", __FUNCTION__);
}
VOID
phy_APCalibrate_8814A(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN struct dm_struct * dm,
#else
IN void * padapter,
#endif
IN s1Byte delta,
IN boolean is2T
)
{
}
VOID
phy_lc_calibrate_8814a(
IN PVOID pDM_VOID
)
{
boolean bStartContTx = false, bSingleTone = false, bCarrierSuppression = false;
struct dm_struct * dm = (struct dm_struct *)pDM_VOID;
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
struct _ADAPTER *padapter = dm->adapter;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
#if (MP_DRIVER == 1)
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
PMPT_CONTEXT pMptCtx = &(padapter->mpt_ctx);
bStartContTx = pMptCtx->bStartContTx;
bSingleTone = pMptCtx->bSingleTone;
bCarrierSuppression = pMptCtx->bCarrierSuppression;
#else
PMPT_CONTEXT pMptCtx = &(padapter->mppriv.mpt_ctx);
#endif
#endif
#endif
PHYDM_DBG(dm, DBG_CMN,"===> PHY_LCCalibrate_8814A\n");
//#if (MP_DRIVER == 1)
_phy_lc_calibrate_8814a(dm, true);
//#endif
PHYDM_DBG(dm, DBG_CMN,"<=== PHY_LCCalibrate_8814A\n");
}
VOID
PHY_APCalibrate_8814A(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN struct dm_struct * dm,
#else
IN void * padapter,
#endif
IN s1Byte delta
)
{
}
VOID
PHY_DPCalibrate_8814A(
IN struct dm_struct * dm
)
{
}
boolean
phy_QueryRFPathSwitch_8814A(
IN void * padapter
)
{
return true;
}
/* BOOLEAN PHY_QueryRFPathSwitch_8814A( */
/* IN void * padapter */
/* ) */
/* { */
/* HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter); */
/* #if DISABLE_BB_RF */
/* return true; */
/* #endif */
/* return phy_QueryRFPathSwitch_8814A(padapter); */
/* } */
VOID _phy_SetRFPathSwitch_8814A(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN struct dm_struct * dm,
#else
IN void * padapter,
#endif
IN boolean bMain,
IN boolean is2T
)
{
}
VOID phy_set_rf_path_switch_8814a(
#if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE))
IN struct dm_struct * dm,
#else
IN void * padapter,
#endif
IN boolean bMain
)
{
}

112
hal/phydm/halrf/rtl8814a/halrf_8814a_ce.h 100644
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@ -0,0 +1,112 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HAL_PHY_RF_8814A_H__
#define __HAL_PHY_RF_8814A_H__
/*--------------------------Define Parameters-------------------------------*/
#define AVG_THERMAL_NUM_8814A 4
#define RF_T_METER_8814A 0x42
#include "../halphyrf_ce.h"
void configure_txpower_track_8814a(
struct txpwrtrack_cfg *pConfig
);
VOID
GetDeltaSwingTable_8814A(
IN PVOID pDM_VOID,
u8* *TemperatureUP_A,
u8* *TemperatureDOWN_A,
u8* *TemperatureUP_B,
u8* *TemperatureDOWN_B
);
VOID
GetDeltaSwingTable_8814A_PathCD(
IN PVOID pDM_VOID,
u8* *TemperatureUP_C,
u8* *TemperatureDOWN_C,
u8* *TemperatureUP_D,
u8* *TemperatureDOWN_D
);
VOID
ODM_TxPwrTrackSetPwr8814A(
IN PVOID pDM_VOID,
enum pwrtrack_method Method,
u8 RFPath,
u8 ChannelMappedIndex
);
u8
CheckRFGainOffset(
struct dm_struct *dm,
enum pwrtrack_method Method,
u8 RFPath
);
VOID
phy_iq_calibrate_8814a(
IN PVOID pDM_VOID,
boolean bReCovery
);
//
// LC calibrate
//
void
phy_lc_calibrate_8814a(
IN PVOID pDM_VOID
);
//
// AP calibrate
//
void
PHY_APCalibrate_8814A(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
struct dm_struct * dm,
#else
IN void * padapter,
#endif
IN s1Byte delta
);
VOID
PHY_DPCalibrate_8814A(
struct dm_struct * dm
);
VOID phy_set_rf_path_switch_8814a(
#if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE))
struct dm_struct * dm,
#else
IN void * padapter,
#endif
boolean bMain
);
#endif // #ifndef __HAL_PHY_RF_8188E_H__

522
hal/phydm/halrf/rtl8814a/halrf_8814a_win.c 100644
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@ -0,0 +1,522 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#include "mp_precomp.h"
#include "../phydm_precomp.h"
#if (RTL8814A_SUPPORT == 1)
/*---------------------------Define Local Constant---------------------------*/
// 2010/04/25 MH Define the max tx power tracking tx agc power.
#define ODM_TXPWRTRACK_MAX_IDX_8814A 6
/*---------------------------Define Local Constant---------------------------*/
//3============================================================
//3 Tx Power Tracking
//3============================================================
// Add CheckRFGainOffset By YuChen to make sure that RF gain offset will not over upperbound 4'b1010
u1Byte
CheckRFGainOffset(
PDM_ODM_T dm,
u1Byte RFPath
)
{
u1Byte UpperBound = 10; // 4'b1010 = 10
u1Byte Final_RF_Index = 0;
boolean bPositive = false;
PODM_RF_CAL_T pRFCalibrateInfo = &(dm->RFCalibrateInfo);
if( pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] >= 0) // check if RF_Index is positive or not
{
Final_RF_Index = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] >> 1;
bPositive = true;
ODM_SetRFReg(dm, (ODM_RF_RADIO_PATH_E)RFPath, rRF_TxGainOffset, BIT(15), bPositive);
}
else
{
Final_RF_Index = (-1)*pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] >> 1;
bPositive = false;
ODM_SetRFReg(dm, (ODM_RF_RADIO_PATH_E)RFPath, rRF_TxGainOffset, BIT(15), bPositive);
}
if(bPositive == true)
{
if(Final_RF_Index >= UpperBound)
{
ODM_SetRFReg(dm, (ODM_RF_RADIO_PATH_E)RFPath, rRF_TxGainOffset, 0xF0000, UpperBound); //set RF Reg0x55 per path
return UpperBound;
}
else
{
ODM_SetRFReg(dm, (ODM_RF_RADIO_PATH_E)RFPath, rRF_TxGainOffset, 0xF0000, Final_RF_Index); //set RF Reg0x55 per path
return Final_RF_Index;
}
}
else
{
ODM_SetRFReg(dm, (ODM_RF_RADIO_PATH_E)RFPath, rRF_TxGainOffset, 0xF0000, Final_RF_Index); //set RF Reg0x55 per path
return Final_RF_Index;
}
return false;
}
VOID
ODM_TxPwrTrackSetPwr8814A(
PDM_ODM_T dm,
PWRTRACK_METHOD Method,
u1Byte RFPath,
u1Byte ChannelMappedIndex
)
{
u1Byte Final_OFDM_Swing_Index = 0;
u1Byte Final_CCK_Swing_Index = 0;
u1Byte Final_RF_Index = 0;
u1Byte UpperBound = 10, TxScalingUpperBound = 28; // Upperbound = 4'b1010, TxScalingUpperBound = +2 dB
PODM_RF_CAL_T pRFCalibrateInfo = &(dm->RFCalibrateInfo);
if (Method == MIX_MODE)
{
PHYDM_DBG(dm,DBG_COMP_MCC,"pRFCalibrateInfo->DefaultOfdmIndex=%d, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d, RF_Path = %d\n", pRFCalibrateInfo->DefaultOfdmIndex, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], RFPath);
Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath];
Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath])%2;
Final_RF_Index = CheckRFGainOffset(dm, RFPath); // check if Final_RF_Index >= 10
if((Final_RF_Index == UpperBound) && (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] >= 0)) // check BBSW is not over +2dB
{
Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] - (UpperBound << 1));
if(Final_OFDM_Swing_Index > TxScalingUpperBound)
Final_OFDM_Swing_Index = TxScalingUpperBound;
}
switch(RFPath)
{
case ODM_RF_PATH_A:
ODM_SetBBReg(dm, rA_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[Final_OFDM_Swing_Index]); //set BBswing
PHYDM_DBG(dm,DBG_COMP_MCC,"******Path_A Compensate with BBSwing , Final_OFDM_Swing_Index = %d, Final_RF_Index = %d \n", Final_OFDM_Swing_Index, Final_RF_Index);
break;
case ODM_RF_PATH_B:
ODM_SetBBReg(dm, rB_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[Final_OFDM_Swing_Index]); //set BBswing
PHYDM_DBG(dm,DBG_COMP_MCC,"******Path_B Compensate with BBSwing , Final_OFDM_Swing_Index = %d, Final_RF_Index = %d \n", Final_OFDM_Swing_Index, Final_RF_Index);
break;
case ODM_RF_PATH_C:
ODM_SetBBReg(dm, rC_TxScale_Jaguar2, 0xFFE00000, TxScalingTable_Jaguar[Final_OFDM_Swing_Index]); //set BBswing
PHYDM_DBG(dm,DBG_COMP_MCC,"******Path_C Compensate with BBSwing , Final_OFDM_Swing_Index = %d, Final_RF_Index = %d \n", Final_OFDM_Swing_Index, Final_RF_Index);
break;
case ODM_RF_PATH_D:
ODM_SetBBReg(dm, rD_TxScale_Jaguar2, 0xFFE00000, TxScalingTable_Jaguar[Final_OFDM_Swing_Index]); //set BBswing
PHYDM_DBG(dm,DBG_COMP_MCC,"******Path_D Compensate with BBSwing , Final_OFDM_Swing_Index = %d, Final_RF_Index = %d \n", Final_OFDM_Swing_Index, Final_RF_Index);
break;
default:
PHYDM_DBG(dm,DBG_COMP_MCC,"Wrong Path name!!!! \n");
break;
}
}
return;
} // ODM_TxPwrTrackSetPwr8814A
VOID
GetDeltaSwingTable_8814A(
IN PDM_ODM_T dm,
OUT pu1Byte *TemperatureUP_A,
OUT pu1Byte *TemperatureDOWN_A,
OUT pu1Byte *TemperatureUP_B,
OUT pu1Byte *TemperatureDOWN_B
)
{
void * adapter = dm->adapter;
PODM_RF_CAL_T pRFCalibrateInfo = &(dm->RFCalibrateInfo);
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
u1Byte TxRate = 0xFF;
u1Byte channel = hal_data->CurrentChannel;
if (dm->mp_mode == true) {
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
#if (MP_DRIVER == 1)
PMPT_CONTEXT pMptCtx = &(adapter->MptCtx);
TxRate = MptToMgntRate(pMptCtx->MptRateIndex);
#endif
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
PMPT_CONTEXT pMptCtx = &(adapter->mppriv.MptCtx);
TxRate = MptToMgntRate(pMptCtx->MptRateIndex);
#endif
#endif
} else {
u2Byte rate = *(dm->pForcedDataRate);
if (!rate) { /*auto rate*/
if (rate != 0xFF) {
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
TxRate = adapter->HalFunc.GetHwRateFromMRateHandler(dm->TxRate);
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
TxRate = HwRateToMRate(dm->TxRate);
#endif
}
} else { /*force rate*/
TxRate = (u1Byte)rate;
}
}
PHYDM_DBG(dm, DBG_COMP_MCC,"Power Tracking TxRate=0x%X\n", TxRate);
if (1 <= channel && channel <= 14) {
if (IS_CCK_RATE(TxRate)) {
*TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P;
*TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N;
*TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P;
*TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N;
} else {
*TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P;
*TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N;
*TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P;
*TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N;
}
} else if (36 <= channel && channel <= 64) {
*TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[0];
*TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[0];
*TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[0];
*TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[0];
} else if (100 <= channel && channel <= 144) {
*TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[1];
*TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[1];
*TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[1];
*TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[1];
} else if (149 <= channel && channel <= 173) {
*TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[2];
*TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[2];
*TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[2];
*TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[2];
} else {
*TemperatureUP_A = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E;
*TemperatureDOWN_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E;
*TemperatureUP_B = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E;
*TemperatureDOWN_B = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E;
}
return;
}
VOID
GetDeltaSwingTable_8814A_PathCD(
IN PDM_ODM_T dm,
OUT pu1Byte *TemperatureUP_C,
OUT pu1Byte *TemperatureDOWN_C,
OUT pu1Byte *TemperatureUP_D,
OUT pu1Byte *TemperatureDOWN_D
)
{
void * adapter = dm->adapter;
PODM_RF_CAL_T pRFCalibrateInfo = &(dm->RFCalibrateInfo);
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
u1Byte TxRate = 0xFF;
u1Byte channel = hal_data->CurrentChannel;
if (dm->mp_mode == true) {
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
#if (MP_DRIVER == 1)
PMPT_CONTEXT pMptCtx = &(adapter->MptCtx);
TxRate = MptToMgntRate(pMptCtx->MptRateIndex);
#endif
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
PMPT_CONTEXT pMptCtx = &(adapter->mppriv.MptCtx);
TxRate = MptToMgntRate(pMptCtx->MptRateIndex);
#endif
#endif
} else {
u2Byte rate = *(dm->pForcedDataRate);
if (!rate) { /*auto rate*/
if (rate != 0xFF) {
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
TxRate = adapter->HalFunc.GetHwRateFromMRateHandler(dm->TxRate);
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
TxRate = HwRateToMRate(dm->TxRate);
#endif
}
} else { /*force rate*/
TxRate = (u1Byte)rate;
}
}
PHYDM_DBG(dm, DBG_COMP_MCC,"Power Tracking TxRate=0x%X\n", TxRate);
if ( 1 <= channel && channel <= 14) {
if (IS_CCK_RATE(TxRate)) {
*TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_P;
*TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_N;
*TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_P;
*TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_N;
} else {
*TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_2GC_P;
*TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_2GC_N;
*TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_2GD_P;
*TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_2GD_N;
}
} else if (36 <= channel && channel <= 64) {
*TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P[0];
*TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N[0];
*TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P[0];
*TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N[0];
} else if (100 <= channel && channel <= 144) {
*TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P[1];
*TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N[1];
*TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P[1];
*TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N[1];
} else if (149 <= channel && channel <= 173) {
*TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P[2];
*TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N[2];
*TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P[2];
*TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N[2];
} else {
*TemperatureUP_C = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E;
*TemperatureDOWN_C = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E;
*TemperatureUP_D = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E;
*TemperatureDOWN_D = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E;
}
return;
}
void ConfigureTxpowerTrack_8814A(
PTXPWRTRACK_CFG pConfig
)
{
pConfig->SwingTableSize_CCK = CCK_TABLE_SIZE;
pConfig->SwingTableSize_OFDM = OFDM_TABLE_SIZE;
pConfig->Threshold_IQK = 8;
pConfig->AverageThermalNum = AVG_THERMAL_NUM_8814A;
pConfig->RfPathCount = MAX_PATH_NUM_8814A;
pConfig->ThermalRegAddr = RF_T_METER_88E;
pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr8814A;
pConfig->DoIQK = DoIQK_8814A;
pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8814A;
pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8814A;
pConfig->GetDeltaSwingTable8814only = GetDeltaSwingTable_8814A_PathCD;
}
VOID
phy_LCCalibrate_8814A(
IN PDM_ODM_T dm,
IN boolean is2T
)
{
u4Byte LC_Cal = 0, cnt;
//Check continuous TX and Packet TX
u4Byte reg0x914 = ODM_Read4Byte(dm, rSingleTone_ContTx_Jaguar);;
// Backup RF reg18.
LC_Cal = ODM_GetRFReg(dm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask);
if((reg0x914 & 0x70000) == 0)
ODM_Write1Byte(dm, REG_TXPAUSE_8812A, 0xFF);
//3 3. Read RF reg18
LC_Cal = ODM_GetRFReg(dm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask);
//3 4. Set LC calibration begin bit15
ODM_SetRFReg(dm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, LC_Cal|0x08000);
ODM_delay_ms(100);
for (cnt = 0; cnt < 100; cnt++) {
if (ODM_GetRFReg(dm, ODM_RF_PATH_A, RF_CHNLBW, 0x8000) != 0x1)
break;
ODM_delay_ms(10);
}
PHYDM_DBG(dm, DBG_CMN,"retry cnt = %d\n", cnt);
//3 Restore original situation
if((reg0x914 & 70000) == 0)
ODM_Write1Byte(dm, REG_TXPAUSE_8812A, 0x00);
// Recover channel number
ODM_SetRFReg(dm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, LC_Cal);
DbgPrint("Call %s\n", __FUNCTION__);
}
VOID
phy_APCalibrate_8814A(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T dm,
#else
IN void * padapter,
#endif
IN s1Byte delta,
IN boolean is2T
)
{
}
VOID
PHY_LCCalibrate_8814A(
IN PDM_ODM_T dm
)
{
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
void * padapter = dm->adapter;
#if (MP_DRIVER == 1)
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
PMPT_CONTEXT pMptCtx = &(padapter->MptCtx);
#else
PMPT_CONTEXT pMptCtx = &(padapter->mppriv.MptCtx);
#endif
#endif
#endif
PHYDM_DBG(dm, DBG_CMN,"===> PHY_LCCalibrate_8814A\n");
//#if (MP_DRIVER == 1)
phy_LCCalibrate_8814A(dm, true);
//#endif
PHYDM_DBG(dm, DBG_CMN,"<=== PHY_LCCalibrate_8814A\n");
}
VOID
PHY_APCalibrate_8814A(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T dm,
#else
IN void * padapter,
#endif
IN s1Byte delta
)
{
}
VOID
PHY_DPCalibrate_8814A(
IN PDM_ODM_T dm
)
{
}
boolean
phy_QueryRFPathSwitch_8814A(
IN void * padapter
)
{
return true;
}
/* boolean PHY_QueryRFPathSwitch_8814A( */
/* IN void * padapter */
/* ) */
/* { */
/* #if DISABLE_BB_RF */
/* return true; */
/* #endif */
/* return phy_QueryRFPathSwitch_8814A(padapter); */
/* } */
VOID phy_SetRFPathSwitch_8814A(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T dm,
#else
IN void * padapter,
#endif
IN boolean bMain,
IN boolean is2T
)
{
}
VOID PHY_SetRFPathSwitch_8814A(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T dm,
#else
IN void * padapter,
#endif
IN boolean bMain
)
{
}
#else /* (RTL8814A_SUPPORT == 0)*/
VOID
PHY_LCCalibrate_8814A(
IN PDM_ODM_T dm
){}
VOID
PHY_IQCalibrate_8814A(
IN PDM_ODM_T dm,
IN boolean bReCovery
){}
#endif /* (RTL8814A_SUPPORT == 0)*/

98
hal/phydm/halrf/rtl8814a/halrf_8814a_win.h 100644
View File

@ -0,0 +1,98 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HALRF_8814A_H__
#define __HALRF_8814A_H__
/*--------------------------Define Parameters-------------------------------*/
#define AVG_THERMAL_NUM_8814A 4
#include "halphyrf_win.h"
void configure_txpower_track_8814a(
struct txpwrtrack_cfg *config
);
void
get_delta_swing_table_8814a(
void *dm_void,
u8 **temperature_up_a,
u8 **temperature_down_a,
u8 **temperature_up_b,
u8 **temperature_down_b
);
void
get_delta_swing_table_8814a_path_cd(
void *dm_void,
u8 **temperature_up_c,
u8 **temperature_down_c,
u8 **temperature_up_d,
u8 **temperature_down_d
);
void
odm_tx_pwr_track_set_pwr8814a(
void *dm_void,
enum pwrtrack_method method,
u8 rf_path,
u8 channel_mapped_index
);
u1Byte
check_rf_gain_offset(
void *dm_void,
u8 rf_path,
);
//
// LC calibrate
//
void
phy_lc_calibrate_8814a(
void *dm_void
);
//
// AP calibrate
//
void
phy_iq_calibrate_8814a(
void *dm_void,
boolean is_recovery
);
void
phy_dp_calibrate_8814a(
void *dm_void,
);
void phy_set_rf_path_switch_8814a(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
struct dm_struct *dm,
#else
void *adapter,
#endif
boolean is_main
);
#endif // #ifndef __HAL_PHY_RF_8188E_H__

538
hal/phydm/halrf/rtl8814a/halrf_iqk_8814a.c 100644
View File

@ -0,0 +1,538 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#include "mp_precomp.h"
#include "../../phydm_precomp.h"
/*---------------------------Define Local Constant---------------------------*/
/*---------------------------Define Local Constant---------------------------*/
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
void DoIQK_8814A(
void* pDM_VOID,
u8 DeltaThermalIndex,
u8 ThermalValue,
u8 Threshold
)
{
struct dm_struct * dm = (struct dm_struct *)pDM_VOID;
odm_reset_iqk_result(dm);
dm->rf_calibrate_info.thermal_value_iqk= ThermalValue;
phy_iq_calibrate_8814a(dm, false);
}
#else
/*Originally pConfig->DoIQK is hooked PHY_IQCalibrate_8814A, but DoIQK_8814A and PHY_IQCalibrate_8814A have different arguments*/
void DoIQK_8814A(
void* pDM_VOID,
u8 DeltaThermalIndex,
u8 ThermalValue,
u8 Threshold
)
{
struct dm_struct * dm = (struct dm_struct *)pDM_VOID;
boolean bReCovery = (boolean) DeltaThermalIndex;
phy_iq_calibrate_8814a(dm, bReCovery);
}
#endif
//1 7. IQK
VOID
_IQK_BackupMacBB_8814A(
IN struct dm_struct * dm,
u32* MAC_backup,
u32* BB_backup,
u32* Backup_MAC_REG,
u32* Backup_BB_REG
)
{
u32 i;
//save MACBB default value
for (i = 0; i < MAC_REG_NUM_8814; i++){
MAC_backup[i] = odm_read_4byte(dm, Backup_MAC_REG[i]);
}
for (i = 0; i < BB_REG_NUM_8814; i++){
BB_backup[i] = odm_read_4byte(dm, Backup_BB_REG[i]);
}
PHYDM_DBG(dm, DBG_CMN,"BackupMacBB Success!!!!\n");
}
VOID
_IQK_BackupRF_8814A(
IN struct dm_struct * dm,
u32 RF_backup[][4],
u32* Backup_RF_REG
)
{
u32 i;
//Save RF Parameters
for (i = 0; i < RF_REG_NUM_8814; i++){
RF_backup[i][RF_PATH_A] = odm_get_rf_reg(dm, RF_PATH_A, Backup_RF_REG[i], bRFRegOffsetMask);
RF_backup[i][RF_PATH_B] = odm_get_rf_reg(dm, RF_PATH_B, Backup_RF_REG[i], bRFRegOffsetMask);
RF_backup[i][RF_PATH_C] = odm_get_rf_reg(dm, RF_PATH_C, Backup_RF_REG[i], bRFRegOffsetMask);
RF_backup[i][RF_PATH_D] = odm_get_rf_reg(dm, RF_PATH_D, Backup_RF_REG[i], bRFRegOffsetMask);
}
PHYDM_DBG(dm, DBG_CMN,"BackupRF Success!!!!\n");
}
VOID
_IQK_AFESetting_8814A(
IN struct dm_struct * dm,
IN boolean Do_IQK
)
{
if(Do_IQK)
{
// IQK AFE Setting RX_WAIT_CCA mode
odm_write_4byte(dm, 0xc60, 0x0e808003);
odm_write_4byte(dm, 0xe60, 0x0e808003);
odm_write_4byte(dm, 0x1860, 0x0e808003);
odm_write_4byte(dm, 0x1a60, 0x0e808003);
odm_set_bb_reg(dm, 0x90c, BIT(13), 0x1);
odm_set_bb_reg(dm, 0x764, BIT(10)|BIT(9), 0x3);
odm_set_bb_reg(dm, 0x764, BIT(10)|BIT(9), 0x0);
odm_set_bb_reg(dm, 0x804, BIT(2), 0x1);
odm_set_bb_reg(dm, 0x804, BIT(2), 0x0);
PHYDM_DBG(dm, DBG_CMN,"AFE IQK mode Success!!!!\n");
}
else
{
odm_write_4byte(dm, 0xc60, 0x07808003);
odm_write_4byte(dm, 0xe60, 0x07808003);
odm_write_4byte(dm, 0x1860, 0x07808003);
odm_write_4byte(dm, 0x1a60, 0x07808003);
odm_set_bb_reg(dm, 0x90c, BIT(13), 0x1);
odm_set_bb_reg(dm, 0x764, BIT(10)|BIT(9), 0x3);
odm_set_bb_reg(dm, 0x764, BIT(10)|BIT(9), 0x0);
odm_set_bb_reg(dm, 0x804, BIT(2), 0x1);
odm_set_bb_reg(dm, 0x804, BIT(2), 0x0);
PHYDM_DBG(dm, DBG_CMN,"AFE Normal mode Success!!!!\n");
}
}
VOID
_IQK_RestoreMacBB_8814A(
IN struct dm_struct * dm,
u32* MAC_backup,
u32* BB_backup,
u32* Backup_MAC_REG,
u32* Backup_BB_REG
)
{
u32 i;
//Reload MacBB Parameters
for (i = 0; i < MAC_REG_NUM_8814; i++){
odm_write_4byte(dm, Backup_MAC_REG[i], MAC_backup[i]);
}
for (i = 0; i < BB_REG_NUM_8814; i++){
odm_write_4byte(dm, Backup_BB_REG[i], BB_backup[i]);
}
PHYDM_DBG(dm, DBG_CMN,"RestoreMacBB Success!!!!\n");
}
VOID
_IQK_RestoreRF_8814A(
IN struct dm_struct * dm,
u32* Backup_RF_REG,
u32 RF_backup[][4]
)
{
u32 i;
odm_set_rf_reg(dm, RF_PATH_A, 0xef, bRFRegOffsetMask, 0x0);
odm_set_rf_reg(dm, RF_PATH_B, 0xef, bRFRegOffsetMask, 0x0);
odm_set_rf_reg(dm, RF_PATH_C, 0xef, bRFRegOffsetMask, 0x0);
odm_set_rf_reg(dm, RF_PATH_D, 0xef, bRFRegOffsetMask, 0x0);
for (i = 0; i < RF_REG_NUM_8814; i++){
odm_set_rf_reg(dm, RF_PATH_A, Backup_RF_REG[i], bRFRegOffsetMask, RF_backup[i][RF_PATH_A]);
odm_set_rf_reg(dm, RF_PATH_B, Backup_RF_REG[i], bRFRegOffsetMask, RF_backup[i][RF_PATH_B]);
odm_set_rf_reg(dm, RF_PATH_C, Backup_RF_REG[i], bRFRegOffsetMask, RF_backup[i][RF_PATH_C]);
odm_set_rf_reg(dm, RF_PATH_D, Backup_RF_REG[i], bRFRegOffsetMask, RF_backup[i][RF_PATH_D]);
}
PHYDM_DBG(dm, DBG_CMN,"RestoreRF Success!!!!\n");
}
VOID
PHY_ResetIQKResult_8814A(
IN struct dm_struct * dm
)
{
odm_write_4byte(dm, 0x1b00, 0xf8000000);
odm_write_4byte(dm, 0x1b38, 0x20000000);
odm_write_4byte(dm, 0x1b00, 0xf8000002);
odm_write_4byte(dm, 0x1b38, 0x20000000);
odm_write_4byte(dm, 0x1b00, 0xf8000004);
odm_write_4byte(dm, 0x1b38, 0x20000000);
odm_write_4byte(dm, 0x1b00, 0xf8000006);
odm_write_4byte(dm, 0x1b38, 0x20000000);
odm_write_4byte(dm, 0xc10, 0x100);
odm_write_4byte(dm, 0xe10, 0x100);
odm_write_4byte(dm, 0x1810, 0x100);
odm_write_4byte(dm, 0x1a10, 0x100);
}
VOID
_IQK_ResetNCTL_8814A(
IN struct dm_struct * dm
)
{
odm_write_4byte(dm, 0x1b00, 0xf8000000);
odm_write_4byte(dm, 0x1b80, 0x00000006);
odm_write_4byte(dm, 0x1b00, 0xf8000000);
odm_write_4byte(dm, 0x1b80, 0x00000002);
PHYDM_DBG(dm, DBG_CMN,"ResetNCTL Success!!!!\n");
}
VOID
_IQK_ConfigureMAC_8814A(
IN struct dm_struct * dm
)
{
// ========MAC register setting========
odm_write_1byte(dm, 0x522, 0x3f);
odm_set_bb_reg(dm, 0x550, BIT(11)|BIT(3), 0x0);
odm_write_1byte(dm, 0x808, 0x00); // RX ante off
odm_set_bb_reg(dm, 0x838, 0xf, 0xe); // CCA off
odm_set_bb_reg(dm, 0xa14, BIT(9)|BIT(8), 0x3); // CCK RX Path off
odm_write_4byte(dm, 0xcb0, 0x77777777);
odm_write_4byte(dm, 0xeb0, 0x77777777);
odm_write_4byte(dm, 0x18b4, 0x77777777);
odm_write_4byte(dm, 0x1ab4, 0x77777777);
odm_set_bb_reg(dm, 0x1abc, 0x0ff00000, 0x77);
/*by YN*/
odm_set_bb_reg(dm, 0xcbc, 0xf, 0x0);
}
VOID
_LOK_One_Shot(
IN void* pDM_VOID
)
{
struct dm_struct * dm = (struct dm_struct *)pDM_VOID;
struct dm_iqk_info * pIQK_info = &dm->IQK_info;
u8 Path = 0, delay_count = 0, ii;
boolean LOK_notready = false;
u32 LOK_temp1 = 0, LOK_temp2 = 0;
PHYDM_DBG(dm, DBG_CMN,"============ LOK ============\n");
for(Path =0; Path <=3; Path++){
PHYDM_DBG(dm, DBG_CMN,"==========S%d LOK ==========\n", Path);
odm_set_bb_reg(dm, 0x9a4, BIT(21)|BIT(20), Path); // ADC Clock source
odm_write_4byte(dm, 0x1b00, (0xf8000001|(1<<(4+Path)))); // LOK: CMD ID = 0 {0xf8000011, 0xf8000021, 0xf8000041, 0xf8000081}
ODM_delay_ms(LOK_delay);
delay_count = 0;
LOK_notready = true;
while(LOK_notready){
LOK_notready = (boolean) odm_get_bb_reg(dm, 0x1b00, BIT(0));
ODM_delay_ms(1);
delay_count++;
if(delay_count >= 10){
PHYDM_DBG(dm, DBG_CMN,"S%d LOK timeout!!!\n", Path);
_IQK_ResetNCTL_8814A(dm);
break;
}
}
PHYDM_DBG(dm, DBG_CMN,"S%d ==> delay_count = 0x%d\n", Path, delay_count);
if(!LOK_notready){
odm_write_4byte(dm, 0x1b00, 0xf8000000|(Path<<1));
odm_write_4byte(dm, 0x1bd4, 0x003f0001);
LOK_temp2 = (odm_get_bb_reg(dm, 0x1bfc, 0x003e0000)+0x10)&0x1f;
LOK_temp1 = (odm_get_bb_reg(dm, 0x1bfc, 0x0000003e)+0x10)&0x1f;
for(ii = 1; ii<5; ii++){
LOK_temp1 = LOK_temp1 + ((LOK_temp1 & BIT(4-ii))<<(ii*2));
LOK_temp2 = LOK_temp2 + ((LOK_temp2 & BIT(4-ii))<<(ii*2));
}
PHYDM_DBG(dm, DBG_CMN,"LOK_temp1 = 0x%x, LOK_temp2 = 0x%x\n", LOK_temp1>>4, LOK_temp2>>4);
odm_set_rf_reg(dm, Path, 0x8, 0x07c00, LOK_temp1>>4);
odm_set_rf_reg(dm, Path, 0x8, 0xf8000, LOK_temp2>>4);
PHYDM_DBG(dm, DBG_CMN,"==>S%d fill LOK\n", Path);
}
else{
PHYDM_DBG(dm, DBG_CMN,"==>S%d LOK Fail!!!\n", Path);
odm_set_rf_reg(dm, Path, 0x8, bRFRegOffsetMask, 0x08400);
}
pIQK_info->lok_fail[Path] = LOK_notready;
}
PHYDM_DBG(dm, DBG_CMN,"LOK0_notready = %d, LOK1_notready = %d, LOK2_notready = %d, LOK3_notready = %d\n",
pIQK_info->lok_fail[0], pIQK_info->lok_fail[1], pIQK_info->lok_fail[2], pIQK_info->lok_fail[3]);
}
VOID
_IQK_One_Shot(
IN void* pDM_VOID
)
{
struct dm_struct * dm = (struct dm_struct *)pDM_VOID;
struct dm_iqk_info * pIQK_info = &dm->IQK_info;
u8 Path = 0, delay_count = 0, cal_retry = 0, idx;
boolean notready = true, fail = true;
u32 IQK_CMD;
u16 IQK_Apply[4] = {0xc94, 0xe94, 0x1894, 0x1a94};
for(idx = 0; idx <= 1; idx++){ // ii = 0:TXK , 1: RXK
if(idx == TX_IQK){
PHYDM_DBG(dm, DBG_CMN,"============ WBTXIQK ============\n");
}
else if(idx == RX_IQK){
PHYDM_DBG(dm, DBG_CMN,"============ WBRXIQK ============\n");
}
for(Path =0; Path <=3; Path++){
PHYDM_DBG(dm, DBG_CMN,"==========S%d IQK ==========\n", Path);
cal_retry = 0;
fail = true;
while(fail){
odm_set_bb_reg(dm, 0x9a4, BIT(21)|BIT(20), Path);
if(idx == TX_IQK){
IQK_CMD = (0xf8000001|(*dm->band_width+3)<<8|(1<<(4+Path)));
PHYDM_DBG(dm, DBG_CMN,"TXK_Trigger = 0x%x\n", IQK_CMD);
/*
{0xf8000311, 0xf8000321, 0xf8000341, 0xf8000381} ==> 20 WBTXK (CMD = 3)
{0xf8000411, 0xf8000421, 0xf8000441, 0xf8000481} ==> 40 WBTXK (CMD = 4)
{0xf8000511, 0xf8000521, 0xf8000541, 0xf8000581} ==> 80 WBTXK (CMD = 5)
*/
odm_write_4byte(dm, 0x1b00, IQK_CMD);
}
else if(idx == RX_IQK){
IQK_CMD = (0xf8000001|(9-*dm->band_width)<<8|(1<<(4+Path)));
PHYDM_DBG(dm, DBG_CMN,"TXK_Trigger = 0x%x\n", IQK_CMD);
/*
{0xf8000911, 0xf8000921, 0xf8000941, 0xf8000981} ==> 20 WBRXK (CMD = 9)
{0xf8000811, 0xf8000821, 0xf8000841, 0xf8000881} ==> 40 WBRXK (CMD = 8)
{0xf8000711, 0xf8000721, 0xf8000741, 0xf8000781} ==> 80 WBRXK (CMD = 7)
*/
odm_write_4byte(dm, 0x1b00, IQK_CMD);
}
ODM_delay_ms(WBIQK_delay);
delay_count = 0;
notready = true;
while(notready){
notready = (boolean) odm_get_bb_reg(dm, 0x1b00, BIT(0));
if(!notready){
fail = (boolean) odm_get_bb_reg(dm, 0x1b08, BIT(26));
break;
}
ODM_delay_ms(1);
delay_count++;
if(delay_count >= 20){
PHYDM_DBG(dm, DBG_CMN,"S%d IQK timeout!!!\n", Path);
_IQK_ResetNCTL_8814A(dm);
break;
}
}
if(fail)
cal_retry++;
if(cal_retry >3 )
break;
}
PHYDM_DBG(dm, DBG_CMN,"S%d ==> 0x1b00 = 0x%x\n", Path, odm_read_4byte(dm, 0x1b00));
PHYDM_DBG(dm, DBG_CMN,"S%d ==> 0x1b08 = 0x%x\n", Path, odm_read_4byte(dm, 0x1b08));
PHYDM_DBG(dm, DBG_CMN,"S%d ==> delay_count = 0x%d, cal_retry = %x\n", Path, delay_count, cal_retry);
odm_write_4byte(dm, 0x1b00, 0xf8000000|(Path<<1));
if(!fail){
if(idx == TX_IQK){
pIQK_info->iqc_matrix[idx][Path] = odm_read_4byte(dm, 0x1b38);
}
else if(idx == RX_IQK){
odm_write_4byte(dm, 0x1b3c, 0x20000000);
pIQK_info->iqc_matrix[idx][Path] = odm_read_4byte(dm, 0x1b3c);
}
PHYDM_DBG(dm, DBG_CMN,"S%d_IQC = 0x%x\n", Path, pIQK_info->iqc_matrix[idx][Path]);
}
if(idx == RX_IQK){
if(pIQK_info->iqk_fail[TX_IQK][Path] == false) // TXIQK success in RXIQK
odm_write_4byte( dm, 0x1b38, pIQK_info->iqc_matrix[TX_IQK][Path]);
else
odm_set_bb_reg(dm, IQK_Apply[Path], BIT(0), 0x0);
if(fail) // RXIQK Fail
odm_set_bb_reg(dm, IQK_Apply[Path], (BIT(11)|BIT(10)), 0x0);
}
pIQK_info->iqk_fail[idx][Path] = fail;
}
PHYDM_DBG(dm, DBG_CMN,"IQK0_fail = %d, IQK1_fail = %d, IQK2_fail = %d, IQK3_fail = %d\n",
pIQK_info->iqk_fail[idx][0], pIQK_info->iqk_fail[idx][1], pIQK_info->iqk_fail[idx][2], pIQK_info->iqk_fail[idx][3]);
}
}
VOID
_IQK_Tx_8814A(
IN struct dm_struct * dm,
IN u8 chnlIdx
)
{
PHYDM_DBG(dm, DBG_CMN,"BandWidth = %d, ExtPA2G = %d\n", *dm->band_width, dm->ext_pa);
PHYDM_DBG(dm, DBG_CMN,"Interface = %d, pBandType = %d\n", dm->support_interface, *dm->band_type);
PHYDM_DBG(dm, DBG_CMN,"CutVersion = %x\n", dm->cut_version);
odm_set_rf_reg(dm, RF_PATH_A, 0x58, BIT(19), 0x1);
odm_set_rf_reg(dm, RF_PATH_B, 0x58, BIT(19), 0x1);
odm_set_rf_reg(dm, RF_PATH_C, 0x58, BIT(19), 0x1);
odm_set_rf_reg(dm, RF_PATH_D, 0x58, BIT(19), 0x1);
odm_set_bb_reg(dm, 0xc94, (BIT(11)|BIT(10)|BIT(0)), 0x401);
odm_set_bb_reg(dm, 0xe94, (BIT(11)|BIT(10)|BIT(0)), 0x401);
odm_set_bb_reg(dm, 0x1894, (BIT(11)|BIT(10)|BIT(0)), 0x401);
odm_set_bb_reg(dm, 0x1a94, (BIT(11)|BIT(10)|BIT(0)), 0x401);
if(*dm->band_type == ODM_BAND_5G)
odm_write_4byte(dm, 0x1b00, 0xf8000ff1);
else
odm_write_4byte(dm, 0x1b00, 0xf8000ef1);
ODM_delay_ms(1);
odm_write_4byte(dm, 0x810, 0x20101063);
odm_write_4byte(dm, 0x90c, 0x0B00C000);
_LOK_One_Shot(dm);
_IQK_One_Shot(dm);
}
VOID
_phy_iq_calibrate_8814a(
IN struct dm_struct * dm,
IN u8 Channel
)
{
u32 MAC_backup[MAC_REG_NUM_8814], BB_backup[BB_REG_NUM_8814], RF_backup[RF_REG_NUM_8814][4];
u32 Backup_MAC_REG[MAC_REG_NUM_8814] = {0x520, 0x550};
u32 Backup_BB_REG[BB_REG_NUM_8814] = {0xa14, 0x808, 0x838, 0x90c, 0x810, 0xcb0, 0xeb0,
0x18b4, 0x1ab4, 0x1abc, 0x9a4, 0x764, 0xcbc};
u32 Backup_RF_REG[RF_REG_NUM_8814] = {0x0, 0x8f};
u8 chnlIdx = odm_get_right_chnl_place_for_iqk(Channel);
_IQK_BackupMacBB_8814A(dm, MAC_backup, BB_backup, Backup_MAC_REG, Backup_BB_REG);
_IQK_AFESetting_8814A(dm,true);
_IQK_BackupRF_8814A(dm, RF_backup, Backup_RF_REG);
_IQK_ConfigureMAC_8814A(dm);
_IQK_Tx_8814A(dm, chnlIdx);
_IQK_ResetNCTL_8814A(dm); //for 3-wire to BB use
_IQK_AFESetting_8814A(dm,false);
_IQK_RestoreMacBB_8814A(dm, MAC_backup, BB_backup, Backup_MAC_REG, Backup_BB_REG);
_IQK_RestoreRF_8814A(dm, Backup_RF_REG, RF_backup);
}
/*IQK version:v1.1*/
/*update 0xcbc setting*/
VOID
phy_iq_calibrate_8814a(
IN void* pDM_VOID,
IN boolean bReCovery
)
{
struct dm_struct * dm = (struct dm_struct *)pDM_VOID;
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
struct _ADAPTER * padapter = dm->adapter;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
#if (MP_DRIVER == 1)
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
PMPT_CONTEXT pMptCtx = &(padapter->MptCtx);
#else// (DM_ODM_SUPPORT_TYPE == ODM_CE)
PMPT_CONTEXT pMptCtx = &(padapter->mppriv.mpt_ctx);
#endif
#endif//(MP_DRIVER == 1)
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
if (odm_check_power_status(padapter) == false)
return;
#endif
#if MP_DRIVER == 1
if( pMptCtx->is_single_tone || pMptCtx->is_carrier_suppression )
return;
#endif
#endif
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
_phy_iq_calibrate_8814a(dm, hal_data->current_channel);
/*DBG_871X("%s,%d, do IQK %u ms\n", __func__, __LINE__, rtw_get_passing_time_ms(time_iqk));*/
#else
_phy_iq_calibrate_8814a(dm, *dm->pChannel);
#endif
}
VOID
PHY_IQCalibrate_8814A_Init(
IN void* pDM_VOID
)
{
struct dm_struct * dm = (struct dm_struct *)pDM_VOID;
struct dm_iqk_info *pIQK_info = &dm->IQK_info;
u8 ii, jj;
PHYDM_DBG(dm, DBG_CMN,"=====>PHY_IQCalibrate_8814A_Init\n");
for(jj = 0; jj < 2; jj++){
for(ii = 0; ii < NUM; ii++){
pIQK_info->lok_fail[ii] = true;
pIQK_info->iqk_fail[jj][ii] = true;
pIQK_info->iqc_matrix[jj][ii] = 0x20000000;
}
}
}

58
hal/phydm/halrf/rtl8814a/halrf_iqk_8814a.h 100644
View File

@ -0,0 +1,58 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDM_IQK_8814A_H__
#define __PHYDM_IQK_8814A_H__
/*--------------------------Define Parameters-------------------------------*/
#define MAC_REG_NUM_8814 2
#define BB_REG_NUM_8814 13
#define RF_REG_NUM_8814 2
/*---------------------------End Define Parameters-------------------------------*/
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
VOID
DoIQK_8814A(
PVOID pDM_VOID,
u8 DeltaThermalIndex,
u8 ThermalValue,
u8 Threshold
);
#else
VOID
DoIQK_8814A(
PVOID pDM_VOID,
u8 DeltaThermalIndex,
u8 ThermalValue,
u8 Threshold
);
#endif
VOID
phy_iq_calibrate_8814a(
IN PVOID pDM_VOID,
boolean bReCovery
);
VOID
PHY_IQCalibrate_8814A_Init(
IN PVOID pDM_VOID
);
#endif /* #ifndef __PHYDM_IQK_8814A_H__*/

25
hal/phydm/phydm_hwconfig.c
View File

@ -189,20 +189,12 @@ odm_config_rf_with_header_file(struct dm_struct *dm,
else if (e_rf_path == RF_PATH_D)
READ_AND_CONFIG_MP(8814a, _radiod);
} else if (config_type == CONFIG_RF_TXPWR_LMT) {
if (dm->rfe_type == 0)
READ_AND_CONFIG_MP(8814a, _txpwr_lmt_type0);
else if (dm->rfe_type == 1)
READ_AND_CONFIG_MP(8814a, _txpwr_lmt_type1);
else if (dm->rfe_type == 2)
if (dm->rfe_type == 2)
READ_AND_CONFIG_MP(8814a, _txpwr_lmt_type2);
else if (dm->rfe_type == 3)
READ_AND_CONFIG_MP(8814a, _txpwr_lmt_type3);
else if (dm->rfe_type == 5)
READ_AND_CONFIG_MP(8814a, _txpwr_lmt_type5);
else if (dm->rfe_type == 7)
READ_AND_CONFIG_MP(8814a, _txpwr_lmt_type7);
else if (dm->rfe_type == 8)
READ_AND_CONFIG_MP(8814a, _txpwr_lmt_type8);
else
READ_AND_CONFIG_MP(8814a, _txpwr_lmt);
}
@ -572,14 +564,9 @@ odm_config_rf_with_tx_pwr_track_header_file(struct dm_struct *dm)
READ_AND_CONFIG_MP(8814a, _txpowertrack_type2);
else if (dm->rfe_type == 5)
READ_AND_CONFIG_MP(8814a, _txpowertrack_type5);
else if (dm->rfe_type == 7)
READ_AND_CONFIG_MP(8814a, _txpowertrack_type7);
else if (dm->rfe_type == 8)
READ_AND_CONFIG_MP(8814a, _txpowertrack_type8);
else
READ_AND_CONFIG_MP(8814a, _txpowertrack);
READ_AND_CONFIG_MP(8814a, _txpowertssi);
}
#endif
#if RTL8703B_SUPPORT
@ -914,20 +901,12 @@ odm_config_bb_with_header_file(struct dm_struct *dm,
else if (config_type == CONFIG_BB_AGC_TAB)
READ_AND_CONFIG_MP(8814a, _agc_tab);
else if (config_type == CONFIG_BB_PHY_REG_PG) {
if (dm->rfe_type == 0)
READ_AND_CONFIG_MP(8814a, _phy_reg_pg_type0);
else if (dm->rfe_type == 2)
if (dm->rfe_type == 2)
READ_AND_CONFIG_MP(8814a, _phy_reg_pg_type2);
else if (dm->rfe_type == 3)
READ_AND_CONFIG_MP(8814a, _phy_reg_pg_type3);
else if (dm->rfe_type == 4)
READ_AND_CONFIG_MP(8814a, _phy_reg_pg_type4);
else if (dm->rfe_type == 5)
READ_AND_CONFIG_MP(8814a, _phy_reg_pg_type5);
else if (dm->rfe_type == 7)
READ_AND_CONFIG_MP(8814a, _phy_reg_pg_type7);
else if (dm->rfe_type == 8)
READ_AND_CONFIG_MP(8814a, _phy_reg_pg_type8);
else
READ_AND_CONFIG_MP(8814a, _phy_reg_pg);
} else if (config_type == CONFIG_BB_PHY_REG_MP)

2
hal/phydm/phydm_phystatus.c
View File

@ -890,7 +890,7 @@ s8 phydm_get_cck_rssi(void *dm_void, u8 lna_idx, u8 vga_idx)
#if (RTL8814A_SUPPORT == 1)
case ODM_RTL8814A:
rx_pow = phydm_cck_rssi_8814a(dm, lna_idx, vga_idx);
rx_pow = phydm_cck_rssi_convert(dm, lna_idx, vga_idx);
break;
#endif

47
hal/phydm/rtl8814a/hal8814areg_odm.h 100644
View File

@ -0,0 +1,47 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//============================================================
/* File Name: hal8814areg_odm.h */
//
// Description:
//
// This file is for RTL8814A register definition.
//
//
//============================================================
#ifndef __HAL_8814A_REG_H__
#define __HAL_8814A_REG_H__
//
// Register Definition
//
#define TRX_ANTDIV_PATH 0x860
#define RX_ANTDIV_PATH 0xb2c
#define ODM_R_A_AGC_CORE1_8814A 0xc50
//
// Bitmap Definition
//
#define BIT_FA_RESET_8814A BIT(0)
#endif

4485
hal/phydm/rtl8814a/halhwimg8814a_bb.c 100644
View File

File diff suppressed because it is too large Load Diff

98
hal/phydm/rtl8814a/halhwimg8814a_bb.h 100644
View File

@ -0,0 +1,98 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*Image2HeaderVersion: 2.19*/
#if (RTL8814A_SUPPORT == 1)
#ifndef __INC_MP_BB_HW_IMG_8814A_H
#define __INC_MP_BB_HW_IMG_8814A_H
/******************************************************************************
* AGC_TAB.TXT
******************************************************************************/
void
odm_read_and_config_mp_8814a_agc_tab(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u4Byte odm_get_version_mp_8814a_agc_tab(void);
/******************************************************************************
* PHY_REG.TXT
******************************************************************************/
void
odm_read_and_config_mp_8814a_phy_reg(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u4Byte odm_get_version_mp_8814a_phy_reg(void);
/******************************************************************************
* PHY_REG_MP.TXT
******************************************************************************/
void
odm_read_and_config_mp_8814a_phy_reg_mp(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u4Byte odm_get_version_mp_8814a_phy_reg_mp(void);
/******************************************************************************
* PHY_REG_PG.TXT
******************************************************************************/
void
odm_read_and_config_mp_8814a_phy_reg_pg(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u4Byte odm_get_version_mp_8814a_phy_reg_pg(void);
/******************************************************************************
* PHY_REG_PG_Type2.TXT
******************************************************************************/
void
odm_read_and_config_mp_8814a_phy_reg_pg_type2(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u4Byte odm_get_version_mp_8814a_phy_reg_pg_type2(void);
/******************************************************************************
* PHY_REG_PG_Type3.TXT
******************************************************************************/
void
odm_read_and_config_mp_8814a_phy_reg_pg_type3(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u4Byte odm_get_version_mp_8814a_phy_reg_pg_type3(void);
/******************************************************************************
* PHY_REG_PG_Type5.TXT
******************************************************************************/
void
odm_read_and_config_mp_8814a_phy_reg_pg_type5(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u4Byte odm_get_version_mp_8814a_phy_reg_pg_type5(void);
#endif
#endif /* end of HWIMG_SUPPORT*/

56
hal/phydm/rtl8814a/halhwimg8814a_fw.h 100644
View File

@ -0,0 +1,56 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#if (RTL8814A_SUPPORT == 1)
#ifndef __INC_MP_FW_HW_IMG_8814A_H
#define __INC_MP_FW_HW_IMG_8814A_H
/******************************************************************************
* FW_AP.TXT
******************************************************************************/
void
ODM_ReadFirmware_MP_8814A_FW_AP(
struct dm_struct *dm,
u8 *pFirmware,
u32 *pFirmwareSize
);
u4Byte ODM_GetVersion_MP_8814A_FW_AP(void);
extern u32 array_length_mp_8814a_fw_ap;
extern u8 array_mp_8814a_fw_ap[];
/******************************************************************************
* FW_NIC.TXT
******************************************************************************/
void
ODM_ReadFirmware_MP_8814A_FW_NIC(
struct dm_struct *dm,
u8 *pFirmware,
u32 *pFirmwareSize
);
u4Byte ODM_GetVersion_MP_8814A_FW_NIC(void);
extern u32 array_length_mp_8814a_fw_nic;
extern u8 array_mp_8814a_fw_nic[];
#endif
#endif // end of HWIMG_SUPPORT

321
hal/phydm/rtl8814a/halhwimg8814a_mac.c 100644
View File

@ -0,0 +1,321 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
/*Image2HeaderVersion: 2.19*/
#include "mp_precomp.h"
#include "../phydm_precomp.h"
#if (RTL8814A_SUPPORT == 1)
static boolean
check_positive(
struct dm_struct *dm,
u32 condition1,
u32 condition2,
u32 condition3,
u32 condition4
)
{
u1Byte _board_type = ((dm->board_type & BIT(4)) >> 4) << 0 | /* _GLNA*/
((dm->board_type & BIT(3)) >> 3) << 1 | /* _GPA*/
((dm->board_type & BIT(7)) >> 7) << 2 | /* _ALNA*/
((dm->board_type & BIT(6)) >> 6) << 3 | /* _APA */
((dm->board_type & BIT(2)) >> 2) << 4; /* _BT*/
u4Byte cond1 = condition1, cond2 = condition2, cond3 = condition3, cond4 = condition4;
u4Byte driver1 = dm->cut_version << 24 |
(dm->support_interface & 0xF0) << 16 |
dm->support_platform << 16 |
dm->package_type << 12 |
(dm->support_interface & 0x0F) << 8 |
_board_type;
u4Byte driver2 = (dm->type_glna & 0xFF) << 0 |
(dm->type_gpa & 0xFF) << 8 |
(dm->type_alna & 0xFF) << 16 |
(dm->type_apa & 0xFF) << 24;
u4Byte driver3 = 0;
u4Byte driver4 = (dm->type_glna & 0xFF00) >> 8 |
(dm->type_gpa & 0xFF00) |
(dm->type_alna & 0xFF00) << 8 |
(dm->type_apa & 0xFF00) << 16;
PHYDM_DBG(dm, ODM_COMP_INIT,"===> check_positive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4);
PHYDM_DBG(dm, ODM_COMP_INIT,"===> check_positive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4);
PHYDM_DBG(dm, ODM_COMP_INIT," (Platform, Interface) = (0x%X, 0x%X)\n", dm->support_platform, dm->support_interface);
PHYDM_DBG(dm, ODM_COMP_INIT," (Board, Package) = (0x%X, 0x%X)\n", dm->board_type, dm->package_type);
/*============== Value Defined Check ===============*/
/*QFN Type [15:12] and Cut Version [27:24] need to do value check*/
if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000)))
return false;
if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000)))
return false;
/*=============== Bit Defined Check ================*/
/* We don't care [31:28] */
cond1 &= 0x00FF0FFF;
driver1 &= 0x00FF0FFF;
if ((cond1 & driver1) == cond1) {
u4Byte bit_mask = 0;
if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/
return true;
if ((cond1 & BIT(0)) != 0) /*GLNA*/
bit_mask |= 0x000000FF;
if ((cond1 & BIT(1)) != 0) /*GPA*/
bit_mask |= 0x0000FF00;
if ((cond1 & BIT(2)) != 0) /*ALNA*/
bit_mask |= 0x00FF0000;
if ((cond1 & BIT(3)) != 0) /*APA*/
bit_mask |= 0xFF000000;
if (((cond2 & bit_mask) == (driver2 & bit_mask)) && ((cond4 & bit_mask) == (driver4 & bit_mask))) /* BoardType of each RF path is matched*/
return true;
else
return false;
} else
return false;
}
static boolean
check_negative(
struct dm_struct *dm,
u32 condition1,
u32 condition2
)
{
return true;
}
/******************************************************************************
* MAC_REG.TXT
******************************************************************************/
u4Byte array_mp_8814a_mac_reg[] = {
0x010, 0x0000007C,
0x014, 0x000000DB,
0x016, 0x00000002,
0x073, 0x00000010,
0x420, 0x00000080,
0x421, 0x0000000F,
0x428, 0x0000000A,
0x429, 0x00000010,
0x430, 0x00000000,
0x431, 0x00000000,
0x432, 0x00000000,
0x433, 0x00000001,
0x434, 0x00000004,
0x435, 0x00000005,
0x436, 0x00000007,
0x437, 0x00000008,
0x43C, 0x00000004,
0x43D, 0x00000005,
0x43E, 0x00000007,
0x43F, 0x00000008,
0x440, 0x0000005D,
0x441, 0x00000001,
0x442, 0x00000000,
0x444, 0x00000010,
0x445, 0x000000F0,
0x446, 0x00000001,
0x447, 0x000000FE,
0x448, 0x00000000,
0x449, 0x00000000,
0x44A, 0x00000000,
0x44B, 0x00000040,
0x44C, 0x00000010,
0x44D, 0x000000F0,
0x44E, 0x0000003F,
0x44F, 0x00000000,
0x450, 0x00000000,
0x451, 0x00000000,
0x452, 0x00000000,
0x453, 0x00000040,
0x45E, 0x00000004,
0x49C, 0x00000010,
0x49D, 0x000000F0,
0x49E, 0x00000000,
0x49F, 0x00000006,
0x4A0, 0x000000E0,
0x4A1, 0x00000003,
0x4A2, 0x00000000,
0x4A3, 0x00000040,
0x4A4, 0x00000015,
0x4A5, 0x000000F0,
0x4A6, 0x00000000,
0x4A7, 0x00000006,
0x4A8, 0x000000E0,
0x4A9, 0x00000000,
0x4AA, 0x00000000,
0x4AB, 0x00000000,
0x7DA, 0x00000008,
0x1448, 0x00000006,
0x144A, 0x00000006,
0x144C, 0x00000006,
0x144E, 0x00000006,
0x4C8, 0x000000FF,
0x4C9, 0x00000008,
0x4CA, 0x0000003C,
0x4CB, 0x0000003C,
0x4CC, 0x000000FF,
0x4CD, 0x000000FF,
0x4CE, 0x00000001,
0x4CF, 0x00000008,
0x500, 0x00000026,
0x501, 0x000000A2,
0x502, 0x0000002F,
0x503, 0x00000000,
0x504, 0x00000028,
0x505, 0x000000A3,
0x506, 0x0000005E,
0x507, 0x00000000,
0x508, 0x0000002B,
0x509, 0x000000A4,
0x50A, 0x0000005E,
0x50B, 0x00000000,
0x50C, 0x0000004F,
0x50D, 0x000000A4,
0x50E, 0x00000000,
0x50F, 0x00000000,
0x512, 0x0000001C,
0x514, 0x0000000A,
0x516, 0x0000000A,
0x521, 0x0000002F,
0x525, 0x0000004F,
0x550, 0x00000010,
0x551, 0x00000010,
0x559, 0x00000002,
0x55C, 0x00000064,
0x55D, 0x000000FF,
0x577, 0x00000003,
0x5BE, 0x00000064,
0x604, 0x00000001,
0x605, 0x00000030,
0x607, 0x00000001,
0x608, 0x0000000E,
0x609, 0x0000002A,
0x60A, 0x00000000,
0x60C, 0x00000018,
0x60D, 0x00000050,
0x6A0, 0x000000FF,
0x6A1, 0x000000FF,
0x6A2, 0x000000FF,
0x6A3, 0x000000FF,
0x6A4, 0x000000FF,
0x6A5, 0x000000FF,
0x6DE, 0x00000084,
0x620, 0x000000FF,
0x621, 0x000000FF,
0x622, 0x000000FF,
0x623, 0x000000FF,
0x624, 0x000000FF,
0x625, 0x000000FF,
0x626, 0x000000FF,
0x627, 0x000000FF,
0x638, 0x00000064,
0x63C, 0x0000000A,
0x63D, 0x0000000A,
0x63E, 0x0000000E,
0x63F, 0x0000000E,
0x640, 0x00000040,
0x642, 0x00000040,
0x643, 0x00000000,
0x652, 0x000000C8,
0x66E, 0x00000005,
0x700, 0x00000021,
0x701, 0x00000043,
0x702, 0x00000065,
0x703, 0x00000087,
0x708, 0x00000021,
0x709, 0x00000043,
0x70A, 0x00000065,
0x70B, 0x00000087,
0x718, 0x00000040,
0x7D5, 0x000000BC,
0x7D8, 0x00000028,
0x7D9, 0x00000000,
0x7DA, 0x0000000B,
};
void
odm_read_and_config_mp_8814a_mac_reg(
struct dm_struct * dm
)
{
u4Byte i = 0;
u1Byte c_cond;
boolean is_matched = true, is_skipped = false;
u4Byte array_len = sizeof(array_mp_8814a_mac_reg)/sizeof(u4Byte);
pu4Byte array = array_mp_8814a_mac_reg;
u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
PHYDM_DBG(dm, ODM_COMP_INIT,"===> ODM_ReadAndConfig_MP_8814A_MAC_REG\n");
while ((i + 1) < array_len) {
v1 = array[i];
v2 = array[i + 1];
if (v1 & (BIT(31) | BIT(30))) {/*positive & negative condition*/
if (v1 & BIT(31)) {/* positive condition*/
c_cond = (u1Byte)((v1 & (BIT(29)|BIT(28))) >> 28);
if (c_cond == COND_ENDIF) {/*end*/
is_matched = true;
is_skipped = false;
PHYDM_DBG(dm, ODM_COMP_INIT,"ENDIF\n");
} else if (c_cond == COND_ELSE) { /*else*/
is_matched = is_skipped?false:true;
PHYDM_DBG(dm, ODM_COMP_INIT,"ELSE\n");
} else {/*if , else if*/
pre_v1 = v1;
pre_v2 = v2;
PHYDM_DBG(dm, ODM_COMP_INIT,"IF or ELSE IF\n");
}
} else if (v1 & BIT(30)) { /*negative condition*/
if (is_skipped == false) {
if (check_positive(dm, pre_v1, pre_v2, v1, v2)) {
is_matched = true;
is_skipped = true;
} else {
is_matched = false;
is_skipped = false;
}
} else
is_matched = false;
}
} else {
if (is_matched)
odm_config_mac_8814a(dm, v1, (u1Byte)v2);
}
i = i + 2;
}
}
u4Byte
odm_get_version_mp_8814a_mac_reg(void)
{
return 85;
}
#endif /* end of HWIMG_SUPPORT*/

38
hal/phydm/rtl8814a/halhwimg8814a_mac.h 100644
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*Image2HeaderVersion: 2.19*/
#if (RTL8814A_SUPPORT == 1)
#ifndef __INC_MP_MAC_HW_IMG_8814A_H
#define __INC_MP_MAC_HW_IMG_8814A_H
/******************************************************************************
* MAC_REG.TXT
******************************************************************************/
void
odm_read_and_config_mp_8814a_mac_reg( /* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u4Byte odm_get_version_mp_8814a_mac_reg(void);
#endif
#endif /* end of HWIMG_SUPPORT*/

8842
hal/phydm/rtl8814a/halhwimg8814a_rf.c 100644
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148
hal/phydm/rtl8814a/halhwimg8814a_rf.h 100644
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@ -0,0 +1,148 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*Image2HeaderVersion: 2.19*/
#if (RTL8814A_SUPPORT == 1)
#ifndef __INC_MP_RF_HW_IMG_8814A_H
#define __INC_MP_RF_HW_IMG_8814A_H
/******************************************************************************
* RadioA.TXT
******************************************************************************/
void
odm_read_and_config_mp_8814a_radioa(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u4Byte odm_get_version_mp_8814a_radioa(void);
/******************************************************************************
* RadioB.TXT
******************************************************************************/
void
odm_read_and_config_mp_8814a_radiob(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u4Byte odm_get_version_mp_8814a_radiob(void);
/******************************************************************************
* RadioC.TXT
******************************************************************************/
void
odm_read_and_config_mp_8814a_radioc(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u4Byte odm_get_version_mp_8814a_radioc(void);
/******************************************************************************
* RadioD.TXT
******************************************************************************/
void
odm_read_and_config_mp_8814a_radiod(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u4Byte odm_get_version_mp_8814a_radiod(void);
/******************************************************************************
* TxPowerTrack.TXT
******************************************************************************/
void
odm_read_and_config_mp_8814a_txpowertrack(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u4Byte odm_get_version_mp_8814a_txpowertrack(void);
/******************************************************************************
* TxPowerTrack_Type0.TXT
******************************************************************************/
void
odm_read_and_config_mp_8814a_txpowertrack_type0(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u4Byte odm_get_version_mp_8814a_txpowertrack_type0(void);
/******************************************************************************
* txpowertrack_type2.TXT
******************************************************************************/
void
odm_read_and_config_mp_8814a_txpowertrack_type2(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u4Byte odm_get_version_mp_8814a_txpowertrack_type2(void);
/******************************************************************************
* txpowertrack_type5.TXT
******************************************************************************/
void
odm_read_and_config_mp_8814a_txpowertrack_type5(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u4Byte odm_get_version_mp_8814a_txpowertrack_type5(void);
/******************************************************************************
* txpwr_lmt.TXT
******************************************************************************/
void
odm_read_and_config_mp_8814a_txpwr_lmt(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u4Byte odm_get_version_mp_8814a_txpwr_lmt(void);
/******************************************************************************
* txpwr_lmt_type2.TXT
******************************************************************************/
void
odm_read_and_config_mp_8814a_txpwr_lmt_type2(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u4Byte odm_get_version_mp_8814a_txpwr_lmt_type2(void);
/******************************************************************************
* txpwr_lmt_type3.TXT
******************************************************************************/
void
odm_read_and_config_mp_8814a_txpwr_lmt_type3(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u4Byte odm_get_version_mp_8814a_txpwr_lmt_type3(void);
/******************************************************************************
* txpwr_lmt_type5.TXT
******************************************************************************/
void
odm_read_and_config_mp_8814a_txpwr_lmt_type5(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u4Byte odm_get_version_mp_8814a_txpwr_lmt_type5(void);
#endif
#endif /* end of HWIMG_SUPPORT*/

1745
hal/phydm/rtl8814a/halphyrf_8814a_ap.c 100644
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164
hal/phydm/rtl8814a/halphyrf_8814a_ap.h 100644
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@ -0,0 +1,164 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HAL_PHY_RF_8814A_H__
#define __HAL_PHY_RF_8814A_H__
/*--------------------------Define Parameters-------------------------------*/
#define IQK_DELAY_TIME_8814A 10 //ms
#define index_mapping_NUM_8814A 15
#define AVG_THERMAL_NUM_8814A 4
#define RF_T_METER_8814A 0x42
#define MAX_PATH_NUM_8814A 4
#include "../halphyrf_ap.h"
void ConfigureTxpowerTrack_8814A(
PTXPWRTRACK_CFG pConfig
);
VOID
GetDeltaSwingTable_8814A(
struct dm_struct *dm,
u8* *TemperatureUP_A,
u8* *TemperatureDOWN_A,
u8* *TemperatureUP_B,
u8* *TemperatureDOWN_B
);
VOID
GetDeltaSwingTable_8814A_PathCD(
struct dm_struct *dm,
u8* *TemperatureUP_C,
u8* *TemperatureDOWN_C,
u8* *TemperatureUP_D,
u8* *TemperatureDOWN_D
);
VOID
ConfigureTxpowerTrack_8814A(
IN PTXPWRTRACK_CFG pConfig
);
VOID
ODM_TxPwrTrackSetPwr8814A(
IN PDM_ODM_T dm,
IN PWRTRACK_METHOD Method,
IN u1Byte RFPath,
IN u1Byte ChannelMappedIndex
);
u1Byte
CheckRFGainOffset(
PDM_ODM_T dm,
PWRTRACK_METHOD Method,
u1Byte RFPath
);
//
// LC calibrate
//
void
PHY_LCCalibrate_8814A(
IN PDM_ODM_T dm
);
void
phy_LCCalibrate_8814A(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T dm,
#else
IN void * padapter,
#endif
IN boolean is2T
);
//
// AP calibrate
//
void
PHY_APCalibrate_8814A(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T dm,
#else
IN void * padapter,
#endif
IN s1Byte delta);
void
PHY_DigitalPredistortion_8814A( IN void * padapter);
#if 0 //FOR_8814_IQK
VOID
_PHY_SaveADDARegisters(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T dm,
#else
IN void * padapter,
#endif
IN pu4Byte ADDAReg,
IN pu4Byte ADDABackup,
IN u4Byte RegisterNum
);
VOID
_PHY_PathADDAOn(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T dm,
#else
IN void * padapter,
#endif
IN pu4Byte ADDAReg,
IN boolean isPathAOn,
IN boolean is2T
);
VOID
_PHY_MACSettingCalibration(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T dm,
#else
IN void * padapter,
#endif
IN pu4Byte MACReg,
IN pu4Byte MACBackup
);
VOID
_PHY_PathAStandBy(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T dm
#else
IN void * padapter
#endif
);
#endif
#endif // #ifndef __HAL_PHY_RF_8814A_H__

522
hal/phydm/rtl8814a/halphyrf_8814a_win.c 100644
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@ -0,0 +1,522 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#include "mp_precomp.h"
#include "../phydm_precomp.h"
#if (RTL8814A_SUPPORT == 1)
/*---------------------------Define Local Constant---------------------------*/
// 2010/04/25 MH Define the max tx power tracking tx agc power.
#define ODM_TXPWRTRACK_MAX_IDX_8814A 6
/*---------------------------Define Local Constant---------------------------*/
//3============================================================
//3 Tx Power Tracking
//3============================================================
// Add CheckRFGainOffset By YuChen to make sure that RF gain offset will not over upperbound 4'b1010
u1Byte
CheckRFGainOffset(
PDM_ODM_T dm,
u1Byte RFPath
)
{
u1Byte UpperBound = 10; // 4'b1010 = 10
u1Byte Final_RF_Index = 0;
boolean bPositive = false;
PODM_RF_CAL_T pRFCalibrateInfo = &(dm->RFCalibrateInfo);
if( pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] >= 0) // check if RF_Index is positive or not
{
Final_RF_Index = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] >> 1;
bPositive = true;
ODM_SetRFReg(dm, (ODM_RF_RADIO_PATH_E)RFPath, rRF_TxGainOffset, BIT(15), bPositive);
}
else
{
Final_RF_Index = (-1)*pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] >> 1;
bPositive = false;
ODM_SetRFReg(dm, (ODM_RF_RADIO_PATH_E)RFPath, rRF_TxGainOffset, BIT(15), bPositive);
}
if(bPositive == true)
{
if(Final_RF_Index >= UpperBound)
{
ODM_SetRFReg(dm, (ODM_RF_RADIO_PATH_E)RFPath, rRF_TxGainOffset, 0xF0000, UpperBound); //set RF Reg0x55 per path
return UpperBound;
}
else
{
ODM_SetRFReg(dm, (ODM_RF_RADIO_PATH_E)RFPath, rRF_TxGainOffset, 0xF0000, Final_RF_Index); //set RF Reg0x55 per path
return Final_RF_Index;
}
}
else
{
ODM_SetRFReg(dm, (ODM_RF_RADIO_PATH_E)RFPath, rRF_TxGainOffset, 0xF0000, Final_RF_Index); //set RF Reg0x55 per path
return Final_RF_Index;
}
return false;
}
VOID
ODM_TxPwrTrackSetPwr8814A(
PDM_ODM_T dm,
PWRTRACK_METHOD Method,
u1Byte RFPath,
u1Byte ChannelMappedIndex
)
{
u1Byte Final_OFDM_Swing_Index = 0;
u1Byte Final_CCK_Swing_Index = 0;
u1Byte Final_RF_Index = 0;
u1Byte UpperBound = 10, TxScalingUpperBound = 28; // Upperbound = 4'b1010, TxScalingUpperBound = +2 dB
PODM_RF_CAL_T pRFCalibrateInfo = &(dm->RFCalibrateInfo);
if (Method == MIX_MODE)
{
PHYDM_DBG(dm,DBG_COMP_MCC,"pRFCalibrateInfo->DefaultOfdmIndex=%d, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d, RF_Path = %d\n", pRFCalibrateInfo->DefaultOfdmIndex, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], RFPath);
Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath];
Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath])%2;
Final_RF_Index = CheckRFGainOffset(dm, RFPath); // check if Final_RF_Index >= 10
if((Final_RF_Index == UpperBound) && (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] >= 0)) // check BBSW is not over +2dB
{
Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] - (UpperBound << 1));
if(Final_OFDM_Swing_Index > TxScalingUpperBound)
Final_OFDM_Swing_Index = TxScalingUpperBound;
}
switch(RFPath)
{
case ODM_RF_PATH_A:
ODM_SetBBReg(dm, rA_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[Final_OFDM_Swing_Index]); //set BBswing
PHYDM_DBG(dm,DBG_COMP_MCC,"******Path_A Compensate with BBSwing , Final_OFDM_Swing_Index = %d, Final_RF_Index = %d \n", Final_OFDM_Swing_Index, Final_RF_Index);
break;
case ODM_RF_PATH_B:
ODM_SetBBReg(dm, rB_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[Final_OFDM_Swing_Index]); //set BBswing
PHYDM_DBG(dm,DBG_COMP_MCC,"******Path_B Compensate with BBSwing , Final_OFDM_Swing_Index = %d, Final_RF_Index = %d \n", Final_OFDM_Swing_Index, Final_RF_Index);
break;
case ODM_RF_PATH_C:
ODM_SetBBReg(dm, rC_TxScale_Jaguar2, 0xFFE00000, TxScalingTable_Jaguar[Final_OFDM_Swing_Index]); //set BBswing
PHYDM_DBG(dm,DBG_COMP_MCC,"******Path_C Compensate with BBSwing , Final_OFDM_Swing_Index = %d, Final_RF_Index = %d \n", Final_OFDM_Swing_Index, Final_RF_Index);
break;
case ODM_RF_PATH_D:
ODM_SetBBReg(dm, rD_TxScale_Jaguar2, 0xFFE00000, TxScalingTable_Jaguar[Final_OFDM_Swing_Index]); //set BBswing
PHYDM_DBG(dm,DBG_COMP_MCC,"******Path_D Compensate with BBSwing , Final_OFDM_Swing_Index = %d, Final_RF_Index = %d \n", Final_OFDM_Swing_Index, Final_RF_Index);
break;
default:
PHYDM_DBG(dm,DBG_COMP_MCC,"Wrong Path name!!!! \n");
break;
}
}
return;
} // ODM_TxPwrTrackSetPwr8814A
VOID
GetDeltaSwingTable_8814A(
IN PDM_ODM_T dm,
OUT pu1Byte *TemperatureUP_A,
OUT pu1Byte *TemperatureDOWN_A,
OUT pu1Byte *TemperatureUP_B,
OUT pu1Byte *TemperatureDOWN_B
)
{
void * adapter = dm->adapter;
PODM_RF_CAL_T pRFCalibrateInfo = &(dm->RFCalibrateInfo);
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
u1Byte TxRate = 0xFF;
u1Byte channel = hal_data->CurrentChannel;
if (dm->mp_mode == true) {
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
#if (MP_DRIVER == 1)
PMPT_CONTEXT pMptCtx = &(adapter->MptCtx);
TxRate = MptToMgntRate(pMptCtx->MptRateIndex);
#endif
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
PMPT_CONTEXT pMptCtx = &(adapter->mppriv.MptCtx);
TxRate = MptToMgntRate(pMptCtx->MptRateIndex);
#endif
#endif
} else {
u2Byte rate = *(dm->pForcedDataRate);
if (!rate) { /*auto rate*/
if (rate != 0xFF) {
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
TxRate = adapter->HalFunc.GetHwRateFromMRateHandler(dm->TxRate);
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
TxRate = HwRateToMRate(dm->TxRate);
#endif
}
} else { /*force rate*/
TxRate = (u1Byte)rate;
}
}
PHYDM_DBG(dm, DBG_COMP_MCC,"Power Tracking TxRate=0x%X\n", TxRate);
if (1 <= channel && channel <= 14) {
if (IS_CCK_RATE(TxRate)) {
*TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P;
*TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N;
*TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P;
*TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N;
} else {
*TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P;
*TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N;
*TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P;
*TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N;
}
} else if (36 <= channel && channel <= 64) {
*TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[0];
*TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[0];
*TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[0];
*TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[0];
} else if (100 <= channel && channel <= 144) {
*TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[1];
*TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[1];
*TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[1];
*TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[1];
} else if (149 <= channel && channel <= 173) {
*TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[2];
*TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[2];
*TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[2];
*TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[2];
} else {
*TemperatureUP_A = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E;
*TemperatureDOWN_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E;
*TemperatureUP_B = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E;
*TemperatureDOWN_B = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E;
}
return;
}
VOID
GetDeltaSwingTable_8814A_PathCD(
IN PDM_ODM_T dm,
OUT pu1Byte *TemperatureUP_C,
OUT pu1Byte *TemperatureDOWN_C,
OUT pu1Byte *TemperatureUP_D,
OUT pu1Byte *TemperatureDOWN_D
)
{
void * adapter = dm->adapter;
PODM_RF_CAL_T pRFCalibrateInfo = &(dm->RFCalibrateInfo);
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
u1Byte TxRate = 0xFF;
u1Byte channel = hal_data->CurrentChannel;
if (dm->mp_mode == true) {
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
#if (MP_DRIVER == 1)
PMPT_CONTEXT pMptCtx = &(adapter->MptCtx);
TxRate = MptToMgntRate(pMptCtx->MptRateIndex);
#endif
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
PMPT_CONTEXT pMptCtx = &(adapter->mppriv.MptCtx);
TxRate = MptToMgntRate(pMptCtx->MptRateIndex);
#endif
#endif
} else {
u2Byte rate = *(dm->pForcedDataRate);
if (!rate) { /*auto rate*/
if (rate != 0xFF) {
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
TxRate = adapter->HalFunc.GetHwRateFromMRateHandler(dm->TxRate);
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
TxRate = HwRateToMRate(dm->TxRate);
#endif
}
} else { /*force rate*/
TxRate = (u1Byte)rate;
}
}
PHYDM_DBG(dm, DBG_COMP_MCC,"Power Tracking TxRate=0x%X\n", TxRate);
if ( 1 <= channel && channel <= 14) {
if (IS_CCK_RATE(TxRate)) {
*TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_P;
*TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_N;
*TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_P;
*TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_N;
} else {
*TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_2GC_P;
*TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_2GC_N;
*TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_2GD_P;
*TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_2GD_N;
}
} else if (36 <= channel && channel <= 64) {
*TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P[0];
*TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N[0];
*TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P[0];
*TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N[0];
} else if (100 <= channel && channel <= 144) {
*TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P[1];
*TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N[1];
*TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P[1];
*TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N[1];
} else if (149 <= channel && channel <= 173) {
*TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P[2];
*TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N[2];
*TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P[2];
*TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N[2];
} else {
*TemperatureUP_C = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E;
*TemperatureDOWN_C = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E;
*TemperatureUP_D = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E;
*TemperatureDOWN_D = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E;
}
return;
}
void ConfigureTxpowerTrack_8814A(
PTXPWRTRACK_CFG pConfig
)
{
pConfig->SwingTableSize_CCK = CCK_TABLE_SIZE;
pConfig->SwingTableSize_OFDM = OFDM_TABLE_SIZE;
pConfig->Threshold_IQK = 8;
pConfig->AverageThermalNum = AVG_THERMAL_NUM_8814A;
pConfig->RfPathCount = MAX_PATH_NUM_8814A;
pConfig->ThermalRegAddr = RF_T_METER_88E;
pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr8814A;
pConfig->DoIQK = DoIQK_8814A;
pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8814A;
pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8814A;
pConfig->GetDeltaSwingTable8814only = GetDeltaSwingTable_8814A_PathCD;
}
VOID
phy_LCCalibrate_8814A(
IN PDM_ODM_T dm,
IN boolean is2T
)
{
u4Byte LC_Cal = 0, cnt;
//Check continuous TX and Packet TX
u4Byte reg0x914 = ODM_Read4Byte(dm, rSingleTone_ContTx_Jaguar);;
// Backup RF reg18.
LC_Cal = ODM_GetRFReg(dm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask);
if((reg0x914 & 0x70000) == 0)
ODM_Write1Byte(dm, REG_TXPAUSE_8812A, 0xFF);
//3 3. Read RF reg18
LC_Cal = ODM_GetRFReg(dm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask);
//3 4. Set LC calibration begin bit15
ODM_SetRFReg(dm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, LC_Cal|0x08000);
ODM_delay_ms(100);
for (cnt = 0; cnt < 100; cnt++) {
if (ODM_GetRFReg(dm, ODM_RF_PATH_A, RF_CHNLBW, 0x8000) != 0x1)
break;
ODM_delay_ms(10);
}
PHYDM_DBG(dm, DBG_CMN,"retry cnt = %d\n", cnt);
//3 Restore original situation
if((reg0x914 & 70000) == 0)
ODM_Write1Byte(dm, REG_TXPAUSE_8812A, 0x00);
// Recover channel number
ODM_SetRFReg(dm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, LC_Cal);
DbgPrint("Call %s\n", __FUNCTION__);
}
VOID
phy_APCalibrate_8814A(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T dm,
#else
IN void * padapter,
#endif
IN s1Byte delta,
IN boolean is2T
)
{
}
VOID
PHY_LCCalibrate_8814A(
IN PDM_ODM_T dm
)
{
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
void * padapter = dm->adapter;
#if (MP_DRIVER == 1)
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
PMPT_CONTEXT pMptCtx = &(padapter->MptCtx);
#else
PMPT_CONTEXT pMptCtx = &(padapter->mppriv.MptCtx);
#endif
#endif
#endif
PHYDM_DBG(dm, DBG_CMN,"===> PHY_LCCalibrate_8814A\n");
//#if (MP_DRIVER == 1)
phy_LCCalibrate_8814A(dm, true);
//#endif
PHYDM_DBG(dm, DBG_CMN,"<=== PHY_LCCalibrate_8814A\n");
}
VOID
PHY_APCalibrate_8814A(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T dm,
#else
IN void * padapter,
#endif
IN s1Byte delta
)
{
}
VOID
PHY_DPCalibrate_8814A(
IN PDM_ODM_T dm
)
{
}
boolean
phy_QueryRFPathSwitch_8814A(
IN void * padapter
)
{
return true;
}
/* boolean PHY_QueryRFPathSwitch_8814A( */
/* IN void * padapter */
/* ) */
/* { */
/* #if DISABLE_BB_RF */
/* return true; */
/* #endif */
/* return phy_QueryRFPathSwitch_8814A(padapter); */
/* } */
VOID phy_SetRFPathSwitch_8814A(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T dm,
#else
IN void * padapter,
#endif
IN boolean bMain,
IN boolean is2T
)
{
}
VOID PHY_SetRFPathSwitch_8814A(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T dm,
#else
IN void * padapter,
#endif
IN boolean bMain
)
{
}
#else /* (RTL8814A_SUPPORT == 0)*/
VOID
PHY_LCCalibrate_8814A(
IN PDM_ODM_T dm
){}
VOID
PHY_IQCalibrate_8814A(
IN PDM_ODM_T dm,
IN boolean bReCovery
){}
#endif /* (RTL8814A_SUPPORT == 0)*/

106
hal/phydm/rtl8814a/halphyrf_8814a_win.h 100644
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@ -0,0 +1,106 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HAL_PHY_RF_8814A_H__
#define __HAL_PHY_RF_8814A_H__
/*--------------------------Define Parameters-------------------------------*/
#define AVG_THERMAL_NUM_8814A 4
#include "halphyrf_win.h"
void ConfigureTxpowerTrack_8814A(
PTXPWRTRACK_CFG pConfig
);
VOID
GetDeltaSwingTable_8814A(
IN PDM_ODM_T dm,
OUT pu1Byte *TemperatureUP_A,
OUT pu1Byte *TemperatureDOWN_A,
OUT pu1Byte *TemperatureUP_B,
OUT pu1Byte *TemperatureDOWN_B
);
VOID
GetDeltaSwingTable_8814A_PathCD(
IN PDM_ODM_T dm,
OUT pu1Byte *TemperatureUP_C,
OUT pu1Byte *TemperatureDOWN_C,
OUT pu1Byte *TemperatureUP_D,
OUT pu1Byte *TemperatureDOWN_D
);
VOID
ODM_TxPwrTrackSetPwr8814A(
PDM_ODM_T dm,
PWRTRACK_METHOD Method,
u1Byte RFPath,
u1Byte ChannelMappedIndex
);
u1Byte
CheckRFGainOffset(
PDM_ODM_T dm,
u1Byte RFPath
);
//
// LC calibrate
//
void
PHY_LCCalibrate_8814A(
IN PDM_ODM_T dm
);
//
// AP calibrate
//
void
PHY_APCalibrate_8814A(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T dm,
#else
IN void * padapter,
#endif
IN s1Byte delta
);
VOID
PHY_DPCalibrate_8814A(
IN PDM_ODM_T dm
);
VOID PHY_SetRFPathSwitch_8814A(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T dm,
#else
IN void * padapter,
#endif
IN boolean bMain
);
#endif // #ifndef __HAL_PHY_RF_8188E_H__

219
hal/phydm/rtl8814a/phydm_regconfig8814a.c 100644
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@ -0,0 +1,219 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#include "mp_precomp.h"
#include "../phydm_precomp.h"
#if (RTL8814A_SUPPORT == 1)
void
odm_config_rf_reg_8814a(
struct dm_struct *dm,
u32 Addr,
u32 Data,
enum rf_path RF_PATH,
u32 RegAddr
)
{
if(Addr == 0xfe || Addr == 0xffe)
{
#ifdef CONFIG_LONG_DELAY_ISSUE
ODM_sleep_ms(50);
#else
ODM_delay_ms(50);
#endif
}
else
{
odm_set_rf_reg(dm, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
// Add 1us delay between BB/RF register setting.
ODM_delay_us(1);
}
}
void
odm_config_rf_radio_a_8814a(
struct dm_struct *dm,
u32 Addr,
u32 Data
)
{
u4Byte content = 0x1000; // RF_Content: radioa_txt
u4Byte maskforPhySet= (u4Byte)(content&0xE000);
odm_config_rf_reg_8814a(dm, Addr, Data, RF_PATH_A, Addr|maskforPhySet);
PHYDM_DBG(dm,ODM_COMP_INIT,"===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data);
}
void
odm_config_rf_radio_b_8814a(
struct dm_struct *dm,
u32 Addr,
u32 Data
)
{
u4Byte content = 0x1001; // RF_Content: radiob_txt
u4Byte maskforPhySet= (u4Byte)(content&0xE000);
odm_config_rf_reg_8814a(dm, Addr, Data, RF_PATH_B, Addr|maskforPhySet);
PHYDM_DBG(dm,ODM_COMP_INIT,"===> ODM_ConfigRFWithHeaderFile: [RadioB] %08X %08X\n", Addr, Data);
}
void
odm_config_rf_radio_c_8814a(
struct dm_struct *dm,
u32 Addr,
u32 Data
)
{
u4Byte content = 0x1001; // RF_Content: radiob_txt
u4Byte maskforPhySet= (u4Byte)(content&0xE000);
odm_config_rf_reg_8814a(dm, Addr, Data, RF_PATH_C, Addr|maskforPhySet);
PHYDM_DBG(dm,ODM_COMP_INIT,"===> ODM_ConfigRFWithHeaderFile: [RadioC] %08X %08X\n", Addr, Data);
}
void
odm_config_rf_radio_d_8814a(
struct dm_struct *dm,
u32 Addr,
u32 Data
)
{
u4Byte content = 0x1001; // RF_Content: radiob_txt
u4Byte maskforPhySet= (u4Byte)(content&0xE000);
odm_config_rf_reg_8814a(dm, Addr, Data, RF_PATH_D, Addr|maskforPhySet);
PHYDM_DBG(dm,ODM_COMP_INIT,"===> ODM_ConfigRFWithHeaderFile: [RadioD] %08X %08X\n", Addr, Data);
}
void
odm_config_mac_8814a(
struct dm_struct *dm,
u32 Addr,
IN u1Byte Data
)
{
odm_write_1byte(dm, Addr, Data);
PHYDM_DBG(dm,ODM_COMP_INIT,"===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data);
}
void
odm_config_bb_agc_8814a(
struct dm_struct *dm,
u32 Addr,
u32 Bitmask,
u32 Data
)
{
odm_set_bb_reg(dm, Addr, Bitmask, Data);
// Add 1us delay between BB/RF register setting.
ODM_delay_us(1);
PHYDM_DBG(dm,ODM_COMP_INIT,"===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data);
}
void
odm_config_bb_phy_reg_pg_8814a(
struct dm_struct *dm,
u32 Band,
u32 RfPath,
u32 TxNum,
u32 Addr,
u32 Bitmask,
u32 Data
)
{
if (Addr == 0xfe || Addr == 0xffe)
#ifdef CONFIG_LONG_DELAY_ISSUE
ODM_sleep_ms(50);
#else
ODM_delay_ms(50);
#endif
else
{
#if !(DM_ODM_SUPPORT_TYPE&ODM_AP)
phy_store_tx_power_by_rate(dm->adapter, Band, RfPath, TxNum, Addr, Bitmask, Data);
#endif
}
PHYDM_DBG(dm,ODM_COMP_INIT,"===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", Addr, Bitmask, Data);
}
void
odm_config_bb_phy_8814a(
struct dm_struct *dm,
u32 Addr,
u32 Bitmask,
u32 Data
)
{
if (Addr == 0xfe)
#ifdef CONFIG_LONG_DELAY_ISSUE
ODM_sleep_ms(50);
#else
ODM_delay_ms(50);
#endif
else if (Addr == 0xfd)
ODM_delay_ms(5);
else if (Addr == 0xfc)
ODM_delay_ms(1);
else if (Addr == 0xfb)
ODM_delay_us(50);
else if (Addr == 0xfa)
ODM_delay_us(5);
else if (Addr == 0xf9)
ODM_delay_us(1);
else
{
odm_set_bb_reg(dm, Addr, Bitmask, Data);
}
// Add 1us delay between BB/RF register setting.
ODM_delay_us(1);
PHYDM_DBG(dm,ODM_COMP_INIT,"===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data);
}
void
odm_config_bb_txpwr_lmt_8814a(
struct dm_struct *dm,
u8* Regulation,
u8* Band,
u8* Bandwidth,
u8* RateSection,
u8* RfPath,
u8* Channel,
u8* PowerLimit
)
{
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
phy_set_tx_power_limit(dm, Regulation, Band,
Bandwidth, RateSection, RfPath, Channel, PowerLimit);
#endif
}
#endif

53
hal/phydm/rtl8814a/phydm_regconfig8814a.h 100644
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __INC_ODM_REGCONFIG_H_8814A
#define __INC_ODM_REGCONFIG_H_8814A
#if (RTL8814A_SUPPORT == 1)
void odm_config_rf_reg_8814a(struct dm_struct *dm, u32 addr, u32 data,
enum rf_path RF_PATH, u32 reg_addr);
void odm_config_rf_radio_a_8814a(struct dm_struct *dm, u32 addr, u32 data);
void odm_config_rf_radio_b_8814a(struct dm_struct *dm, u32 addr, u32 data);
void odm_config_rf_radio_c_8814a(struct dm_struct *dm, u32 addr, u32 data);
void odm_config_rf_radio_d_8814a(struct dm_struct *dm, u32 addr, u32 data);
void odm_config_mac_8814a(struct dm_struct *dm, u32 addr, u8 data);
void odm_config_bb_agc_8814a(struct dm_struct *dm, u32 addr, u32 bitmask,
u32 data);
void odm_config_bb_phy_reg_pg_8814a(struct dm_struct *dm, u32 band, u32 rf_path,
u32 tx_num, u32 addr, u32 bitmask,
u32 data);
void odm_config_bb_phy_8814a(struct dm_struct *dm, u32 addr, u32 bitmask,
u32 data);
void odm_config_bb_txpwr_lmt_8814a(struct dm_struct *dm, u8 *regulation,
u8 *band, u8 *bandwidth, u8 *rate_section,
u8 *rf_path, u8 *channel, u8 *power_limit);
#endif
#endif // end of SUPPORT

507
hal/phydm/rtl8814a/phydm_rtl8814a.c 100644
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//============================================================
// include files
//============================================================
#include "mp_precomp.h"
#include "../phydm_precomp.h"
#if (RTL8814A_SUPPORT == 1)
#ifdef PHYDM_PRIMARY_CCA
VOID
odm_Write_Dynamic_CCA_8814A(
struct dm_struct *dm,
u8 CurrentMFstate
)
{
struct phydm_pri_cca_struct* PrimaryCCA = &(dm->dm_pri_cca);
if (PrimaryCCA->MF_state != CurrentMFstate){
ODM_SetBBReg(dm, ODM_REG_L1SBD_PD_CH_11N, BIT(8)|BIT(7), CurrentMFstate);
}
PrimaryCCA->MF_state = CurrentMFstate;
}
VOID
odm_PrimaryCCA_Check_Init_8814A(
struct dm_struct *dm)
{
#if ((DM_ODM_SUPPORT_TYPE == ODM_WIN) || (DM_ODM_SUPPORT_TYPE == ODM_AP))
void * padapter = dm->adapter;
struct phydm_pri_cca_struct* PrimaryCCA = &(dm->dm_pri_cca);
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
hal_data->RTSEN = 0;
PrimaryCCA->DupRTS_flag = 0;
PrimaryCCA->intf_flag = 0;
PrimaryCCA->intf_type = 0;
PrimaryCCA->Monitor_flag = 0;
PrimaryCCA->PriCCA_flag = 0;
PrimaryCCA->CH_offset = 0;
PrimaryCCA->MF_state = 0;
#endif /*((DM_ODM_SUPPORT_TYPE==ODM_WIN) ||(DM_ODM_SUPPORT_TYPE==ODM_AP)) */
}
VOID
odm_DynamicPrimaryCCA_Check_8814A(
struct dm_struct *dm
)
{
if(dm->SupportICType != ODM_RTL8814A)
return;
switch (dm->SupportPlatform)
{
case ODM_WIN:
#if(DM_ODM_SUPPORT_TYPE==ODM_WIN)
odm_DynamicPrimaryCCAMP_8814A(dm);
#endif
break;
case ODM_CE:
#if(DM_ODM_SUPPORT_TYPE==ODM_CE)
#endif
break;
case ODM_AP:
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
odm_DynamicPrimaryCCAAP_8814A(dm);
#endif
break;
}
}
#if(DM_ODM_SUPPORT_TYPE==ODM_WIN)
VOID
odm_DynamicPrimaryCCAMP_8814A(
struct dm_struct *dm
)
{
void * padapter = dm->adapter;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter);
Pfalse_ALARM_STATISTICS FalseAlmCnt = (Pfalse_ALARM_STATISTICS)PhyDM_Get_Structure( dm, PHYDM_FALSEALMCNT);
struct phydm_pri_cca_struct* PrimaryCCA = &(dm->dm_pri_cca);
boolean Is40MHz = false;
u8Byte OFDM_CCA, OFDM_FA, BW_USC_Cnt, BW_LSC_Cnt;
u8 SecCHOffset;
u8 CurMFstate;
static u8 CountDown = Monitor_TIME;
OFDM_CCA = FalseAlmCnt->Cnt_OFDM_CCA;
OFDM_FA = FalseAlmCnt->Cnt_Ofdm_fail;
BW_USC_Cnt = FalseAlmCnt->Cnt_BW_USC;
BW_LSC_Cnt = FalseAlmCnt->Cnt_BW_LSC;
PHYDM_DBG(dm,ODM_COMP_DYNAMIC_PRICCA,"8814A: OFDM CCA=%d\n", OFDM_CCA);
PHYDM_DBG(dm,ODM_COMP_DYNAMIC_PRICCA,"8814A: OFDM FA=%d\n", OFDM_FA);
PHYDM_DBG(dm,ODM_COMP_DYNAMIC_PRICCA,"8814A: BW_USC=%d\n", BW_USC_Cnt);
PHYDM_DBG(dm,ODM_COMP_DYNAMIC_PRICCA,"8814A: BW_LSC=%d\n", BW_LSC_Cnt);
Is40MHz = *(dm->pBandWidth);
SecCHOffset = *(dm->pSecChOffset); // NIC: 2: sec is below, 1: sec is above
//DbgPrint("8814A: SecCHOffset = %d\n", SecCHOffset);
if(!dm->bLinked){
return;
}
else{
if(Is40MHz){
PHYDM_DBG(dm,ODM_COMP_DYNAMIC_PRICCA,"8814A: Cont Down= %d\n", CountDown);
PHYDM_DBG(dm,ODM_COMP_DYNAMIC_PRICCA,"8814A: Primary_CCA_flag=%d\n", PrimaryCCA->PriCCA_flag);
PHYDM_DBG(dm,ODM_COMP_DYNAMIC_PRICCA,"8814A: Intf_Type=%d\n", PrimaryCCA->intf_type);
PHYDM_DBG(dm,ODM_COMP_DYNAMIC_PRICCA,"8814A: Intf_flag=%d\n", PrimaryCCA->intf_flag );
PHYDM_DBG(dm,ODM_COMP_DYNAMIC_PRICCA,"8814A: Duplicate RTS Flag=%d\n", PrimaryCCA->DupRTS_flag);
//DbgPrint("8814A RTS_EN=%d\n", hal_data->RTSEN);
if(PrimaryCCA->PriCCA_flag == 0){
if(SecCHOffset == 2){ // Primary channel is above NOTE: duplicate CTS can remove this condition
if((OFDM_CCA > OFDMCCA_TH) && (BW_LSC_Cnt>(BW_USC_Cnt + BW_Ind_Bias))
&& (OFDM_FA>(OFDM_CCA>>1))){
PrimaryCCA->intf_type = 1;
PrimaryCCA->intf_flag = 1;
CurMFstate = MF_USC;
odm_Write_Dynamic_CCA_8814A(dm, CurMFstate);
PrimaryCCA->PriCCA_flag = 1;
}
else if((OFDM_CCA > OFDMCCA_TH) && (BW_LSC_Cnt>(BW_USC_Cnt + BW_Ind_Bias))
&& (OFDM_FA < (OFDM_CCA>>1))){
PrimaryCCA->intf_type = 2;
PrimaryCCA->intf_flag = 1;
CurMFstate = MF_USC;
odm_Write_Dynamic_CCA_8814A(dm, CurMFstate);
PrimaryCCA->PriCCA_flag = 1;
PrimaryCCA->DupRTS_flag = 1;
hal_data->RTSEN = 1;
}
else{
PrimaryCCA->intf_type = 0;
PrimaryCCA->intf_flag = 0;
CurMFstate = MF_USC_LSC;
odm_Write_Dynamic_CCA_8814A(dm, CurMFstate);
hal_data->RTSEN = 0;
PrimaryCCA->DupRTS_flag = 0;
}
}
else if (SecCHOffset == 1){
if((OFDM_CCA > OFDMCCA_TH) && (BW_USC_Cnt > (BW_LSC_Cnt + BW_Ind_Bias))
&& (OFDM_FA > (OFDM_CCA>>1))){
PrimaryCCA->intf_type = 1;
PrimaryCCA->intf_flag = 1;
CurMFstate = MF_LSC;
odm_Write_Dynamic_CCA_8814A(dm, CurMFstate);
PrimaryCCA->PriCCA_flag = 1;
}
else if((OFDM_CCA > OFDMCCA_TH) && (BW_USC_Cnt>(BW_LSC_Cnt + BW_Ind_Bias))
&& (OFDM_FA < (OFDM_CCA>>1))){
PrimaryCCA->intf_type = 2;
PrimaryCCA->intf_flag = 1;
CurMFstate = MF_LSC;
odm_Write_Dynamic_CCA_8814A(dm, CurMFstate);
PrimaryCCA->PriCCA_flag = 1;
PrimaryCCA->DupRTS_flag = 1;
hal_data->RTSEN = 1;
}
else{
PrimaryCCA->intf_type = 0;
PrimaryCCA->intf_flag = 0;
CurMFstate = MF_USC_LSC;
odm_Write_Dynamic_CCA_8814A(dm, CurMFstate);
hal_data->RTSEN = 0;
PrimaryCCA->DupRTS_flag = 0;
}
}
}
else{ // PrimaryCCA->PriCCA_flag==1
CountDown--;
if(CountDown == 0){
CountDown = Monitor_TIME;
PrimaryCCA->PriCCA_flag = 0;
CurMFstate = MF_USC_LSC;
odm_Write_Dynamic_CCA_8814A(dm, CurMFstate); /* default*/
hal_data->RTSEN = 0;
PrimaryCCA->DupRTS_flag = 0;
PrimaryCCA->intf_type = 0;
PrimaryCCA->intf_flag = 0;
}
}
}
else{
return;
}
}
}
#elif(DM_ODM_SUPPORT_TYPE == ODM_AP)
VOID
odm_DynamicPrimaryCCAAP_8814A(
struct dm_struct *dm
)
{
void * adapter = dm->adapter;
prtl8192cd_priv priv = dm->priv;
Pfalse_ALARM_STATISTICS FalseAlmCnt = (Pfalse_ALARM_STATISTICS)PhyDM_Get_Structure( dm, PHYDM_FALSEALMCNT);
struct phydm_pri_cca_struct* PrimaryCCA = &(dm->dm_pri_cca);
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
u8 i;
static u4Byte Count_Down = Monitor_TIME;
boolean STA_BW = false, STA_BW_pre = false, STA_BW_TMP = false;
boolean bConnected = false;
boolean Is40MHz = false;
u8 SecCHOffset;
u8 CurMFstate;
PSTA_INFO_T pstat;
Is40MHz = *(dm->pBandWidth);
SecCHOffset = *(dm->pSecChOffset); // AP: 1: sec is below, 2: sec is above
for(i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++){
pstat = dm->pODM_StaInfo[i];
if(IS_STA_VALID(pstat)){
STA_BW_TMP = pstat->tx_bw;
if(STA_BW_TMP > STA_BW){
STA_BW = STA_BW_TMP;
}
bConnected = true;
}
}
if(Is40MHz){
if(PrimaryCCA->PriCCA_flag == 0){
if(bConnected){
if(STA_BW == 0){ //2 STA BW=20M
PrimaryCCA->PriCCA_flag = 1;
if(SecCHOffset==1){
CurMFstate = MF_USC;
odm_Write_Dynamic_CCA_8814A(dm, CurMFstate);
}
else if(SecCHOffset==2){
CurMFstate = MF_USC;
odm_Write_Dynamic_CCA_8814A(dm, CurMFstate);
}
}
else{ //2 STA BW=40M
if(PrimaryCCA->intf_flag == 0){
odm_Intf_Detection(dm);
}
else{ // intf_flag = 1
if(PrimaryCCA->intf_type == 1){
if(PrimaryCCA->CH_offset == 1){
CurMFstate = MF_USC;
if(SecCHOffset == 1){ // AP, 1: primary is above 2: primary is below
odm_Write_Dynamic_CCA_8814A(dm, CurMFstate);
}
}
else if(PrimaryCCA->CH_offset == 2){
CurMFstate = MF_LSC;
if(SecCHOffset == 2){
odm_Write_Dynamic_CCA_8814A(dm, CurMFstate);
}
}
}
else if(PrimaryCCA->intf_type==2){
if(PrimaryCCA->CH_offset==1){
//ODM_SetBBReg(dm, ODM_REG_L1SBD_PD_CH_11N, BIT(8)|BIT(7), MF_USC);
hal_data->RTSEN = 1;
}
else if(PrimaryCCA->CH_offset==2){
//ODM_SetBBReg(dm, ODM_REG_L1SBD_PD_CH_11N, BIT(8)|BIT(7), MF_LSC);
hal_data->RTSEN = 1;
}
}
}
}
}
else{ // disconnected interference detection
odm_Intf_Detection(dm);
}// end of disconnected
}
else{ // PrimaryCCA->PriCCA_flag == 1
if(STA_BW==0){
STA_BW_pre = STA_BW;
return;
}
Count_Down--;
if((Count_Down == 0) || ((STA_BW & STA_BW_pre) != 1)){
Count_Down = Monitor_TIME;
PrimaryCCA->PriCCA_flag = 0;
PrimaryCCA->intf_type = 0;
PrimaryCCA->intf_flag = 0;
CurMFstate = MF_USC_LSC;
odm_Write_Dynamic_CCA_8814A(dm, CurMFstate); /* default*/
hal_data->RTSEN = 0;
}
}
STA_BW_pre = STA_BW;
}
else{
//2 Reset
odm_PrimaryCCA_Check_Init(dm);
CurMFstate = MF_USC_LSC;
odm_Write_Dynamic_CCA_8814A(dm, CurMFstate);
Count_Down = Monitor_TIME;
}
}
VOID
odm_Intf_Detection_8814A(
struct dm_struct *dm
)
{
Pfalse_ALARM_STATISTICS FalseAlmCnt = (Pfalse_ALARM_STATISTICS)PhyDM_Get_Structure( dm, PHYDM_FALSEALMCNT);
struct phydm_pri_cca_struct* PrimaryCCA = &(dm->dm_pri_cca);
if((FalseAlmCnt->Cnt_OFDM_CCA>OFDMCCA_TH)
&&(FalseAlmCnt->Cnt_BW_LSC>(FalseAlmCnt->Cnt_BW_USC+BW_Ind_Bias))){
PrimaryCCA->intf_flag = 1;
PrimaryCCA->CH_offset = 1; // 1:LSC, 2:USC
if(FalseAlmCnt->Cnt_Ofdm_fail>(FalseAlmCnt->Cnt_OFDM_CCA>>1)){
PrimaryCCA->intf_type = 1;
}
else{
PrimaryCCA->intf_type = 2;
}
}
else if((FalseAlmCnt->Cnt_OFDM_CCA>OFDMCCA_TH)
&&(FalseAlmCnt->Cnt_BW_USC>(FalseAlmCnt->Cnt_BW_LSC+BW_Ind_Bias))){
PrimaryCCA->intf_flag = 1;
PrimaryCCA->CH_offset = 2; // 1:LSC, 2:USC
if(FalseAlmCnt->Cnt_Ofdm_fail>(FalseAlmCnt->Cnt_OFDM_CCA>>1)){
PrimaryCCA->intf_type = 1;
}
else{
PrimaryCCA->intf_type = 2;
}
}
else{
PrimaryCCA->intf_flag = 0;
PrimaryCCA->intf_type = 0;
PrimaryCCA->CH_offset = 0;
}
}
#endif
#endif /* #ifdef PHYDM_PRIMARY_CCA */
u8
phydm_spur_nbi_setting_8814a(
struct dm_struct *dm
)
{
u8 set_result = 0;
/*dm->pChannel means central frequency, so we can use 20M as input*/
if (dm->rfe_type == 0 || dm->rfe_type == 1 || dm->rfe_type == 6) {
/*channel asked by RF Jeff*/
if (*dm->channel == 14)
set_result = phydm_nbi_setting(dm, FUNC_ENABLE, *dm->channel, 40, 2480, PHYDM_DONT_CARE);
else if (*dm->channel >= 4 || *dm->channel <= 8)
set_result = phydm_nbi_setting(dm, FUNC_ENABLE, *dm->channel, 40, 2440, PHYDM_DONT_CARE);
else
set_result = phydm_nbi_setting(dm, FUNC_ENABLE, *dm->channel, 40, 2440, PHYDM_DONT_CARE);
}
PHYDM_DBG(dm, DBG_CMN,"%s, set_result = 0x%d, pChannel = %d\n", __func__, set_result, *dm->channel);
//printk("%s, set_result = 0x%d, pChannel = %d\n", __func__, set_result, *dm->channel);
dm->nbi_set_result = set_result;
return set_result;
}
void odm_hw_setting_8814a(
struct dm_struct *dm
)
{
#ifdef PHYDM_PRIMARY_CCA
odm_PrimaryCCA_Check_Init_8814A(dm);
odm_DynamicPrimaryCCA_Check_8814A(dm);
odm_Intf_Detection_8814A(dm);
#endif
}
#ifdef DYN_ANT_WEIGHTING_SUPPORT
void phydm_dynamic_ant_weighting_8814a(void *dm_void)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u8 rssi_l2h = 43, rssi_h2l = 37;
u8 reg_8;
PHYDM_DBG(dm, ODM_COMP_API, "PEC DBD: non-existing function start.%s\n",__PRETTY_FUNCTION__);
if (dm->is_disable_dym_ant_weighting)
return;
if (*dm->channel <= 14) {
if (dm->rssi_min >= rssi_l2h) {
odm_set_bb_reg(dm, R_0x854, BIT(3), 0x1);
odm_set_bb_reg(dm, R_0x850, BIT(21) | BIT(22), 0x0);
/*equal weighting*/
reg_8 = (u8)odm_get_bb_reg(dm, R_0xf94, BIT(0) | BIT(1) | BIT(2));
PHYDM_DBG(dm, ODM_COMP_API, "Equal weighting ,rssi_min = %d\n, 0xf94[2:0] = 0x%x\n",
dm->rssi_min, reg_8);
} else if (dm->rssi_min <= rssi_h2l) {
odm_set_bb_reg(dm, R_0x854, BIT(3), 0x1);
odm_set_bb_reg(dm, R_0x850, BIT(21) | BIT(22), 0x1);
/*fix sec_min_wgt = 1/2*/
reg_8 = (u8)odm_get_bb_reg(dm, R_0xf94, BIT(0) | BIT(1) | BIT(2));
PHYDM_DBG(dm, ODM_COMP_API, "AGC weighting ,rssi_min = %d\n, 0xf94[2:0] = 0x%x\n",
dm->rssi_min, reg_8);
}
} else {
odm_set_bb_reg(dm, R_0x854, BIT(3), 0x1);
odm_set_bb_reg(dm, R_0x850, BIT(21) | BIT(22), 0x1);
reg_8 = (u8)odm_get_bb_reg(dm, R_0xf94, BIT(0) | BIT(1) | BIT(2));
PHYDM_DBG(dm, ODM_COMP_API, "AGC weighting ,rssi_min = %d\n, 0xf94[2:0] = 0x%x\n",
dm->rssi_min, reg_8);
/*fix sec_min_wgt = 1/2*/
}
PHYDM_DBG(dm, ODM_COMP_API, "PEC DBD: non-existing function end.%s\n",__PRETTY_FUNCTION__);
}
#endif
void phydm_hwsetting_8814a(struct dm_struct *dm)
{
PHYDM_DBG(dm, ODM_COMP_API, "PEC DBD: non-existing function start.%s\n",__PRETTY_FUNCTION__);
phydm_dynamic_ant_weighting(dm);
PHYDM_DBG(dm, ODM_COMP_API, "PEC DBD: non-existing function end.%s\n",__PRETTY_FUNCTION__);
}
#endif // RTL8814A_SUPPORT == 1

78
hal/phydm/rtl8814a/phydm_rtl8814a.h 100644
View File

@ -0,0 +1,78 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODM_RTL8814A_H__
#define __ODM_RTL8814A_H__
#define OFDMCCA_TH 500
#define BW_Ind_Bias 500
#define MF_USC 2
#define MF_LSC 1
#define MF_USC_LSC 0
#define Monitor_TIME 30
VOID
odm_Write_Dynamic_CCA_8814A(
struct dm_struct *dm,
u8 CurrentMFstate
);
VOID
odm_PrimaryCCA_Check_Init_8814A(
struct dm_struct *dm
);
VOID
odm_DynamicPrimaryCCA_Check_8814A(
struct dm_struct *dm
);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
VOID
odm_DynamicPrimaryCCAMP_8814A(
struct dm_struct *dm
);
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
VOID
odm_DynamicPrimaryCCAAP_8814A(
struct dm_struct *dm
);
VOID
odm_Intf_Detection_8814A(
struct dm_struct *dm
);
#endif
u1Byte
phydm_spur_nbi_setting_8814a(
struct dm_struct *dm
);
void odm_hw_setting_8814a(
struct dm_struct *dm
);
#endif
void phydm_hwsetting_8814a(struct dm_struct *dm);

10
hal/phydm/rtl8814a/version_rtl8814a.h 100644
View File

@ -0,0 +1,10 @@
/*RTL8814A PHY Parameters*/
/*
[Caution]
Since 01/Aug/2015, the commit rules will be simplified.
You do not need to fill up the version.h anymore,
only the maintenance supervisor fills it before formal release.
*/
#define RELEASE_DATE_8814A 20150908
#define COMMIT_BY_8814A "BB_LUKE"
#define RELEASE_VERSION_8814A 81

8
hal/phydm/txbf/haltxbf8814a.c
View File

@ -307,8 +307,8 @@ void hal_txbf_8814a_rf_mode(void *dm_void,
}
/*@for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, BIT(28) | BIT29, 0x2); /*@enable BB TxBF ant mapping register*/
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, BIT30, 0x1); /*@if Nsts > Nc don't apply V matrix*/
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, BIT(28) | BIT(29), 0x2); /*@enable BB TxBF ant mapping register*/
odm_set_bb_reg(dm, REG_BB_TXBF_ANT_SET_BF1_8814A, BIT(30), 0x1); /*@if Nsts > Nc don't apply V matrix*/
if (idx == 0) {
switch (nr_index) {
@ -552,13 +552,13 @@ void hal_txbf_8814a_enter(void *dm_void, u8 bfer_bfee_idx)
/*@CSI report parameters of Beamformee*/
if (bfee_idx == 0) {
/*@Get BIT24 & BIT25*/
/*@Get BIT(24) & BIT(25)*/
u8 tmp = odm_read_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 3) & 0x3;
odm_write_1byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 3, tmp | 0x60);
odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A, sta_id | BIT(9));
} else
odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2, sta_id | 0xE200); /*Set BIT25*/
odm_write_2byte(dm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2, sta_id | 0xE200); /*Set BIT(25)*/
phydm_beamforming_notify(dm);
}

98
hal/rtl8814a/Hal8814PwrSeq.c 100644
View File

@ -0,0 +1,98 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#include "Hal8814PwrSeq.h"
#include <rtl8814a_hal.h>
/*
drivers should parse below arrays and do the corresponding actions
*/
//3 Power on Array
WLAN_PWR_CFG rtl8814A_power_on_flow[RTL8814A_TRANS_CARDEMU_TO_ACT_STEPS+RTL8814A_TRANS_END_STEPS]=
{
RTL8814A_TRANS_CARDEMU_TO_ACT
RTL8814A_TRANS_END
};
//3Radio off GPIO Array
WLAN_PWR_CFG rtl8814A_radio_off_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8814A_TRANS_END_STEPS]=
{
RTL8814A_TRANS_ACT_TO_CARDEMU
RTL8814A_TRANS_END
};
//3Card Disable Array
WLAN_PWR_CFG rtl8814A_card_disable_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8814A_TRANS_END_STEPS]=
{
RTL8814A_TRANS_ACT_TO_CARDEMU
RTL8814A_TRANS_CARDEMU_TO_CARDDIS
RTL8814A_TRANS_END
};
//3 Card Enable Array
WLAN_PWR_CFG rtl8814A_card_enable_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8814A_TRANS_END_STEPS]=
{
RTL8814A_TRANS_CARDDIS_TO_CARDEMU
RTL8814A_TRANS_CARDEMU_TO_ACT
RTL8814A_TRANS_END
};
//3Suspend Array
WLAN_PWR_CFG rtl8814A_suspend_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8814A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8814A_TRANS_END_STEPS]=
{
RTL8814A_TRANS_ACT_TO_CARDEMU
RTL8814A_TRANS_CARDEMU_TO_SUS
RTL8814A_TRANS_END
};
//3 Resume Array
WLAN_PWR_CFG rtl8814A_resume_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8814A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8814A_TRANS_END_STEPS]=
{
RTL8814A_TRANS_SUS_TO_CARDEMU
RTL8814A_TRANS_CARDEMU_TO_ACT
RTL8814A_TRANS_END
};
//3HWPDN Array
WLAN_PWR_CFG rtl8814A_hwpdn_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8814A_TRANS_END_STEPS]=
{
RTL8814A_TRANS_ACT_TO_CARDEMU
RTL8814A_TRANS_CARDEMU_TO_PDN
RTL8814A_TRANS_END
};
//3 Enter LPS
WLAN_PWR_CFG rtl8814A_enter_lps_flow[RTL8814A_TRANS_ACT_TO_LPS_STEPS+RTL8814A_TRANS_END_STEPS]=
{
//FW behavior
RTL8814A_TRANS_ACT_TO_LPS
RTL8814A_TRANS_END
};
//3 Leave LPS
WLAN_PWR_CFG rtl8814A_leave_lps_flow[RTL8814A_TRANS_LPS_TO_ACT_STEPS+RTL8814A_TRANS_END_STEPS]=
{
//FW behavior
RTL8814A_TRANS_LPS_TO_ACT
RTL8814A_TRANS_END
};

7741
hal/rtl8814a/hal8814a_fw.c 100644
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1233
hal/rtl8814a/rtl8814a_cmd.c 100644
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417
hal/rtl8814a/rtl8814a_dm.c 100644
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@ -0,0 +1,417 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//============================================================
// Description:
//
// This file is for 92CE/92CU dynamic mechanism only
//
//
//============================================================
#define _RTL8814A_DM_C_
//============================================================
// include files
//============================================================
//#include <drv_types.h>
#include <rtl8814a_hal.h>
//============================================================
// Global var
//============================================================
static VOID
dm_CheckProtection(
IN PADAPTER Adapter
)
{
#if 0
PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
u1Byte CurRate, RateThreshold;
if(pMgntInfo->pHTInfo->bCurBW40MHz)
RateThreshold = MGN_MCS1;
else
RateThreshold = MGN_MCS3;
if(Adapter->TxStats.CurrentInitTxRate <= RateThreshold)
{
pMgntInfo->bDmDisableProtect = TRUE;
DbgPrint("Forced disable protect: %x\n", Adapter->TxStats.CurrentInitTxRate);
}
else
{
pMgntInfo->bDmDisableProtect = FALSE;
DbgPrint("Enable protect: %x\n", Adapter->TxStats.CurrentInitTxRate);
}
#endif
}
#ifdef CONFIG_SUPPORT_HW_WPS_PBC
static void dm_CheckPbcGPIO(_adapter *padapter)
{
u8 tmp1byte;
u8 bPbcPressed = _FALSE;
if(!padapter->registrypriv.hw_wps_pbc)
return;
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
tmp1byte = rtw_read8(padapter, REG_GPIO_EXT_CTRL_8814A);
//DBG_871X("CheckPbcGPIO - %x\n", tmp1byte);
if (tmp1byte == 0xff)
return ;
else if (tmp1byte & BIT3)
{
// Here we only set bPbcPressed to TRUE. After trigger PBC, the variable will be set to FALSE
DBG_871X("CheckPbcGPIO - PBC is pressed\n");
bPbcPressed = _TRUE;
}
#endif
if (_TRUE == bPbcPressed) {
/* Here we only set bPbcPressed to true */
/* After trigger PBC, the variable will be set to false */
RTW_INFO("CheckPbcGPIO - PBC is pressed\n");
rtw_request_wps_pbc_event(padapter);
}
}
#endif /* #ifdef CONFIG_SUPPORT_HW_WPS_PBC */
#ifdef CONFIG_PCI_HCI
/*
* Description:
* Perform interrupt migration dynamically to reduce CPU utilization.
*
* Assumption:
* 1. Do not enable migration under WIFI test.
*
* Created by Roger, 2010.03.05.
* */
VOID
dm_InterruptMigration(
IN PADAPTER Adapter
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv);
BOOLEAN bCurrentIntMt, bCurrentACIntDisable;
BOOLEAN IntMtToSet = _FALSE;
BOOLEAN ACIntToSet = _FALSE;
/* Retrieve current interrupt migration and Tx four ACs IMR settings first. */
bCurrentIntMt = pHalData->bInterruptMigration;
bCurrentACIntDisable = pHalData->bDisableTxInt;
/* */
/* <Roger_Notes> Currently we use busy traffic for reference instead of RxIntOK counts to prevent non-linear Rx statistics */
/* when interrupt migration is set before. 2010.03.05. */
/* */
if (!Adapter->registrypriv.wifi_spec &&
(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) &&
pmlmepriv->LinkDetectInfo.bHigherBusyTraffic) {
IntMtToSet = _TRUE;
/* To check whether we should disable Tx interrupt or not. */
if (pmlmepriv->LinkDetectInfo.bHigherBusyRxTraffic)
ACIntToSet = _TRUE;
}
/* Update current settings. */
if (bCurrentIntMt != IntMtToSet) {
RTW_INFO("%s(): Update interrrupt migration(%d)\n", __FUNCTION__, IntMtToSet);
if (IntMtToSet) {
/* */
/* <Roger_Notes> Set interrrupt migration timer and corresponging Tx/Rx counter. */
/* timer 25ns*0xfa0=100us for 0xf packets. */
/* 2010.03.05. */
/* */
rtw_write32(Adapter, REG_INT_MIG, 0xff000fa0);/* 0x306:Rx, 0x307:Tx */
pHalData->bInterruptMigration = IntMtToSet;
} else {
/* Reset all interrupt migration settings. */
rtw_write32(Adapter, REG_INT_MIG, 0);
pHalData->bInterruptMigration = IntMtToSet;
}
}
#if 0
if (bCurrentACIntDisable != ACIntToSet) {
RTW_INFO("%s(): Update AC interrrupt(%d)\n", __FUNCTION__, ACIntToSet);
if (ACIntToSet) { /* Disable four ACs interrupts. */
/* */
/* <Roger_Notes> Disable VO, VI, BE and BK four AC interrupts to gain more efficient CPU utilization. */
/* When extremely highly Rx OK occurs, we will disable Tx interrupts. */
/* 2010.03.05. */
/* */
UpdateInterruptMask8192CE(Adapter, 0, RT_AC_INT_MASKS);
pHalData->bDisableTxInt = ACIntToSet;
} else { /* Enable four ACs interrupts. */
UpdateInterruptMask8192CE(Adapter, RT_AC_INT_MASKS, 0);
pHalData->bDisableTxInt = ACIntToSet;
}
}
#endif
}
#endif
/*
* Initialize GPIO setting registers
* */
static void
dm_InitGPIOSetting(
IN PADAPTER Adapter
)
{
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
u8 tmp1byte;
tmp1byte = rtw_read8(Adapter, REG_GPIO_MUXCFG);
tmp1byte &= (GPIOSEL_GPIO | ~GPIOSEL_ENBT);
rtw_write8(Adapter, REG_GPIO_MUXCFG, tmp1byte);
}
/* ************************************************************
* functions
* ************************************************************ */
static void Init_ODM_ComInfo_8814(PADAPTER Adapter)
{
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
struct dm_struct *pDM_Odm = &(pHalData->odmpriv);
u8 cut_ver, fab_ver;
Init_ODM_ComInfo(Adapter);
odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_IC_TYPE, ODM_RTL8814A);
fab_ver = ODM_TSMC;
if(IS_A_CUT(pHalData->version_id))
cut_ver = ODM_CUT_A;
else if(IS_B_CUT(pHalData->version_id))
cut_ver = ODM_CUT_B;
else if(IS_C_CUT(pHalData->version_id))
cut_ver = ODM_CUT_C;
else if(IS_D_CUT(pHalData->version_id))
cut_ver = ODM_CUT_D;
else if(IS_E_CUT(pHalData->version_id))
cut_ver = ODM_CUT_E;
else
cut_ver = ODM_CUT_A;
odm_cmn_info_init(pDM_Odm,ODM_CMNINFO_FAB_VER,fab_ver);
odm_cmn_info_init(pDM_Odm,ODM_CMNINFO_CUT_VER,cut_ver);
odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_ANTENNA_TYPE, pHalData->TRxAntDivType);
//odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_IQKFWOFFLOAD, pHalData->RegIQKFWOffload);
}
void
rtl8814_InitHalDm(
IN PADAPTER Adapter
)
{
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
struct dm_struct * pDM_Odm = &(pHalData->odmpriv);
u8 i;
#ifdef CONFIG_USB_HCI
dm_InitGPIOSetting(Adapter);
#endif //CONFIG_USB_HCI
odm_dm_init(pDM_Odm);
//Adapter->fix_rate = 0xFF;
}
VOID
rtl8814_HalDmWatchDog(
IN PADAPTER Adapter
)
{
BOOLEAN bFwCurrentInPSMode = _FALSE;
BOOLEAN bFwPSAwake = _TRUE;
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
struct dm_struct *pDM_Odm = &(pHalData->odmpriv);
struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(Adapter);
u8 in_lps = _FALSE;
if (!rtw_is_hw_init_completed(Adapter))
goto skip_dm;
#ifdef CONFIG_LPS
bFwCurrentInPSMode = pwrpriv->bFwCurrentInPSMode;
rtw_hal_get_hwreg(Adapter, HW_VAR_FWLPS_RF_ON, &bFwPSAwake);
#endif
#ifdef CONFIG_P2P_PS
/* Fw is under p2p powersaving mode, driver should stop dynamic mechanism. */
/* modifed by thomas. 2011.06.11. */
if (Adapter->wdinfo.p2p_ps_mode)
bFwPSAwake = _FALSE;
#endif /* CONFIG_P2P_PS */
if ((rtw_is_hw_init_completed(Adapter))
&& ((!bFwCurrentInPSMode) && bFwPSAwake)) {
rtw_hal_check_rxfifo_full(Adapter);
/* */
/* Dynamically switch RTS/CTS protection. */
/* */
/* dm_CheckProtection(Adapter); */
#ifdef CONFIG_PCI_HCI
/* 20100630 Joseph: Disable Interrupt Migration mechanism temporarily because it degrades Rx throughput. */
/* Tx Migration settings. */
/* dm_InterruptMigration(Adapter); */
/* if(Adapter->HalFunc.TxCheckStuckHandler(Adapter)) */
/* PlatformScheduleWorkItem(&(GET_HAL_DATA(Adapter)->HalResetWorkItem)); */
#endif
}
#ifdef CONFIG_DISABLE_ODM
goto skip_dm;
#endif
#ifdef CONFIG_LPS
if (pwrpriv->bLeisurePs && bFwCurrentInPSMode && pwrpriv->pwr_mode != PS_MODE_ACTIVE)
in_lps = _TRUE;
#endif
rtw_phydm_watchdog(Adapter, in_lps);
skip_dm:
#ifdef CONFIG_SUPPORT_HW_WPS_PBC
/* Check GPIO to determine current Pbc status. */
dm_CheckPbcGPIO(Adapter);
#endif
return;
}
void rtl8814_init_dm_priv(IN PADAPTER Adapter)
{
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
struct dm_struct *podmpriv = &pHalData->odmpriv;
/* _rtw_spinlock_init(&(pHalData->odm_stainfo_lock)); */
#ifndef CONFIG_IQK_PA_OFF /* FW has no IQK PA OFF option yet, don't offload */
#ifdef CONFIG_BT_COEXIST
/* firmware size issue, btcoex fw doesn't support IQK offload */
if (pHalData->EEPROMBluetoothCoexist == _FALSE)
#endif
{
if (IS_HARDWARE_TYPE_8814A(Adapter))
pHalData->RegIQKFWOffload = 1;
}
#endif
Init_ODM_ComInfo_8814(Adapter);
odm_init_all_timers(podmpriv);
}
void rtl8814_deinit_dm_priv(IN PADAPTER Adapter)
{
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
struct dm_struct *podmpriv = &pHalData->odmpriv;
/* _rtw_spinlock_free(&pHalData->odm_stainfo_lock); */
odm_cancel_all_timers(podmpriv);
}
#ifdef CONFIG_ANTENNA_DIVERSITY
// Add new function to reset the state of antenna diversity before link.
//
// Compare RSSI for deciding antenna
void AntDivCompare8814(PADAPTER Adapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src)
{
//PADAPTER Adapter = pDM_Odm->Adapter ;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
if(0 != pHalData->AntDivCfg )
{
//DBG_8192C("update_network=> orgRSSI(%d)(%d),newRSSI(%d)(%d)\n",dst->Rssi,query_rx_pwr_percentage(dst->Rssi),
// src->Rssi,query_rx_pwr_percentage(src->Rssi));
//select optimum_antenna for before linked =>For antenna diversity
if(dst->Rssi >= src->Rssi )//keep org parameter
{
src->Rssi = dst->Rssi;
src->PhyInfo.Optimum_antenna = dst->PhyInfo.Optimum_antenna;
}
}
}
// Add new function to reset the state of antenna diversity before link.
u8 AntDivBeforeLink8814(PADAPTER Adapter )
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
struct dm_struct * pDM_Odm =&pHalData->odmpriv;
SWAT_T *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv);
// Condition that does not need to use antenna diversity.
if(pHalData->AntDivCfg==0)
{
//DBG_8192C("odm_AntDivBeforeLink8192C(): No AntDiv Mechanism.\n");
return _FALSE;
}
if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
{
return _FALSE;
}
if(pDM_SWAT_Table->SWAS_NoLink_State == 0){
//switch channel
pDM_SWAT_Table->SWAS_NoLink_State = 1;
pDM_SWAT_Table->CurAntenna = (pDM_SWAT_Table->CurAntenna==MAIN_ANT)?AUX_ANT:MAIN_ANT;
//PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, pDM_SWAT_Table->CurAntenna);
rtw_antenna_select_cmd(Adapter, pDM_SWAT_Table->CurAntenna, _FALSE);
//DBG_8192C("%s change antenna to ANT_( %s ).....\n",__FUNCTION__, (pDM_SWAT_Table->CurAntenna==MAIN_ANT)?"MAIN":"AUX");
return _TRUE;
}
else
{
pDM_SWAT_Table->SWAS_NoLink_State = 0;
return _FALSE;
}
}
#endif //CONFIG_ANTENNA_DIVERSITY

5620
hal/rtl8814a/rtl8814a_hal_init.c 100644
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3008
hal/rtl8814a/rtl8814a_phycfg.c 100644
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210
hal/rtl8814a/rtl8814a_rf6052.c 100644
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@ -0,0 +1,210 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#define _RTL8814A_RF6052_C_
//#include <drv_types.h>
#include <rtl8814a_hal.h>
/*-----------------------------------------------------------------------------
* Function: PHY_RF6052SetBandwidth()
*
* Overview: This function is called by SetBWModeCallback8190Pci() only
*
* Input: PADAPTER Adapter
* WIRELESS_BANDWIDTH_E Bandwidth //20M or 40M
*
* Output: NONE
*
* Return: NONE
*
* Note: For RF type 0222D
*---------------------------------------------------------------------------*/
VOID
PHY_RF6052SetBandwidth8814A(
IN PADAPTER Adapter,
IN enum channel_width Bandwidth) //20M or 40M
{
switch(Bandwidth)
{
case CHANNEL_WIDTH_20:
/*RTW_INFO("PHY_RF6052SetBandwidth8814A(), set 20MHz\n");*/
phy_set_rf_reg(Adapter, RF_PATH_A, RF_CHNLBW_Jaguar, BIT11|BIT10, 3);
phy_set_rf_reg(Adapter, RF_PATH_B, RF_CHNLBW_Jaguar, BIT11|BIT10, 3);
phy_set_rf_reg(Adapter, RF_PATH_C, RF_CHNLBW_Jaguar, BIT11|BIT10, 3);
phy_set_rf_reg(Adapter, RF_PATH_D, RF_CHNLBW_Jaguar, BIT11|BIT10, 3);
break;
case CHANNEL_WIDTH_40:
/*RTW_INFO("PHY_RF6052SetBandwidth8814A(), set 40MHz\n");*/
phy_set_rf_reg(Adapter, RF_PATH_A, RF_CHNLBW_Jaguar, BIT11|BIT10, 1);
phy_set_rf_reg(Adapter, RF_PATH_B, RF_CHNLBW_Jaguar, BIT11|BIT10, 1);
phy_set_rf_reg(Adapter, RF_PATH_C, RF_CHNLBW_Jaguar, BIT11|BIT10, 1);
phy_set_rf_reg(Adapter, RF_PATH_D, RF_CHNLBW_Jaguar, BIT11|BIT10, 1);
break;
case CHANNEL_WIDTH_80:
/*RTW_INFO("PHY_RF6052SetBandwidth8814A(), set 80MHz\n");*/
phy_set_rf_reg(Adapter, RF_PATH_A, RF_CHNLBW_Jaguar, BIT11|BIT10, 0);
phy_set_rf_reg(Adapter, RF_PATH_B, RF_CHNLBW_Jaguar, BIT11|BIT10, 0);
phy_set_rf_reg(Adapter, RF_PATH_C, RF_CHNLBW_Jaguar, BIT11|BIT10, 0);
phy_set_rf_reg(Adapter, RF_PATH_D, RF_CHNLBW_Jaguar, BIT11|BIT10, 0);
break;
default:
RTW_INFO("PHY_RF6052SetBandwidth8814A(): unknown Bandwidth: %#X\n",Bandwidth );
break;
}
}
static int
phy_RF6052_Config_ParaFile_8814A(
IN PADAPTER Adapter
)
{
u32 u4RegValue=0;
u8 eRFPath;
int rtStatus = _SUCCESS;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
static char sz8814RadioAFile[] = PHY_FILE_RADIO_A;
static char sz8814RadioBFile[] = PHY_FILE_RADIO_B;
static char sz8814RadioCFile[] = PHY_FILE_RADIO_C;
static char sz8814RadioDFile[] = PHY_FILE_RADIO_D;
static char sz8814TxPwrTrack[] = PHY_FILE_TXPWR_TRACK;
char *pszRadioAFile = NULL, *pszRadioBFile = NULL, *pszRadioCFile = NULL, *pszRadioDFile = NULL, *pszTxPwrTrack = NULL;
pszRadioAFile = sz8814RadioAFile;
pszRadioBFile = sz8814RadioBFile;
pszRadioCFile = sz8814RadioCFile;
pszRadioDFile = sz8814RadioDFile;
pszTxPwrTrack = sz8814TxPwrTrack;
//3//-----------------------------------------------------------------
//3// <2> Initialize RF
//3//-----------------------------------------------------------------
//for(eRFPath = RF_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
{
/*----Initialize RF fom connfiguration file----*/
switch(eRFPath)
{
case RF_PATH_A:
#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
if (PHY_ConfigRFWithParaFile(Adapter, pszRadioAFile, eRFPath) == _FAIL)
#endif //CONFIG_LOAD_PHY_PARA_FROM_FILE
{
#ifdef CONFIG_EMBEDDED_FWIMG
if(HAL_STATUS_FAILURE ==odm_config_rf_with_header_file(&pHalData->odmpriv,CONFIG_RF_RADIO, (enum rf_path)eRFPath))
rtStatus = _FAIL;
#endif //CONFIG_EMBEDDED_FWIMG
}
break;
case RF_PATH_B:
#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
if (PHY_ConfigRFWithParaFile(Adapter, pszRadioBFile, eRFPath) == _FAIL)
#endif //CONFIG_LOAD_PHY_PARA_FROM_FILE
{
#ifdef CONFIG_EMBEDDED_FWIMG
if(HAL_STATUS_FAILURE ==odm_config_rf_with_header_file(&pHalData->odmpriv,CONFIG_RF_RADIO, (enum rf_path)eRFPath))
rtStatus = _FAIL;
#endif //CONFIG_EMBEDDED_FWIMG
}
break;
case RF_PATH_C:
#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
if (PHY_ConfigRFWithParaFile(Adapter, pszRadioCFile, eRFPath) == _FAIL)
#endif //CONFIG_LOAD_PHY_PARA_FROM_FILE
{
#ifdef CONFIG_EMBEDDED_FWIMG
if(HAL_STATUS_FAILURE ==odm_config_rf_with_header_file(&pHalData->odmpriv,CONFIG_RF_RADIO, (enum rf_path)eRFPath))
rtStatus = _FAIL;
#endif //CONFIG_EMBEDDED_FWIMG
}
break;
case RF_PATH_D:
#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
if (PHY_ConfigRFWithParaFile(Adapter, pszRadioDFile, eRFPath) == _FAIL)
#endif //CONFIG_LOAD_PHY_PARA_FROM_FILE
{
#ifdef CONFIG_EMBEDDED_FWIMG
if(HAL_STATUS_FAILURE ==odm_config_rf_with_header_file(&pHalData->odmpriv,CONFIG_RF_RADIO, (enum rf_path)eRFPath))
rtStatus = _FAIL;
#endif //CONFIG_EMBEDDED_FWIMG
}
break;
default:
break;
}
if(rtStatus != _SUCCESS){
RTW_INFO("%s():Radio[%d] Fail!!", __FUNCTION__, eRFPath);
goto phy_RF6052_Config_ParaFile_Fail;
}
}
u4RegValue = phy_query_rf_reg(Adapter, RF_PATH_A, RF_RCK1_Jaguar, bRFRegOffsetMask);
phy_set_rf_reg(Adapter, RF_PATH_B, RF_RCK1_Jaguar, bRFRegOffsetMask, u4RegValue);
phy_set_rf_reg(Adapter, RF_PATH_C, RF_RCK1_Jaguar, bRFRegOffsetMask, u4RegValue);
phy_set_rf_reg(Adapter, RF_PATH_D, RF_RCK1_Jaguar, bRFRegOffsetMask, u4RegValue);
//3 -----------------------------------------------------------------
//3 Configuration of Tx Power Tracking
//3 -----------------------------------------------------------------
#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
if (PHY_ConfigRFWithTxPwrTrackParaFile(Adapter, pszTxPwrTrack) == _FAIL)
#endif //CONFIG_LOAD_PHY_PARA_FROM_FILE
{
#ifdef CONFIG_EMBEDDED_FWIMG
odm_config_rf_with_tx_pwr_track_header_file(&pHalData->odmpriv);
#endif
}
//RT_TRACE(COMP_INIT, DBG_LOUD, ("<---phy_RF6052_Config_ParaFile_8812()\n"));
phy_RF6052_Config_ParaFile_Fail:
return rtStatus;
}
int
PHY_RF6052_Config_8814A(
IN PADAPTER Adapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
int rtStatus = _SUCCESS;
// Initialize general global value
pHalData->NumTotalRFPath = 4;
//
// Config BB and RF
//
rtStatus = phy_RF6052_Config_ParaFile_8814A(Adapter);
return rtStatus;
}
/* End of HalRf6052.c */

68
hal/rtl8814a/rtl8814a_rxdesc.c 100644
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@ -0,0 +1,68 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#define _RTL8814A_RXDESC_C_
//#include <drv_types.h>
#include <rtl8814a_hal.h>
void rtl8814_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc)
{
struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib;
_rtw_memset(pattrib, 0, sizeof(struct rx_pkt_attrib));
#ifdef CONFIG_RADIOTAP_WITH_RXDESC
_rtw_memcpy(pattrib->rxdesc, pdesc, RXDESC_SIZE);
#endif
//Offset 0
pattrib->pkt_len = (u16)GET_RX_STATUS_DESC_PKT_LEN_8814A(pdesc);//(le32_to_cpu(pdesc->rxdw0)&0x00003fff)
pattrib->crc_err = (u8)GET_RX_STATUS_DESC_CRC32_8814A(pdesc);//((le32_to_cpu(pdesc->rxdw0) >> 14) & 0x1);
pattrib->icv_err = (u8)GET_RX_STATUS_DESC_ICV_8814A(pdesc);//((le32_to_cpu(pdesc->rxdw0) >> 15) & 0x1);
pattrib->drvinfo_sz = (u8)GET_RX_STATUS_DESC_DRVINFO_SIZE_8814A(pdesc) * 8;//((le32_to_cpu(pdesc->rxdw0) >> 16) & 0xf) * 8;//uint 2^3 = 8 bytes
pattrib->encrypt = (u8)GET_RX_STATUS_DESC_SECURITY_8814A(pdesc);//((le32_to_cpu(pdesc->rxdw0) >> 20) & 0x7);
pattrib->qos = (u8)GET_RX_STATUS_DESC_QOS_8814A(pdesc);//(( le32_to_cpu( pdesc->rxdw0 ) >> 23) & 0x1);// Qos data, wireless lan header length is 26
pattrib->shift_sz = (u8)GET_RX_STATUS_DESC_SHIFT_8814A(pdesc);//((le32_to_cpu(pdesc->rxdw0) >> 24) & 0x3);
pattrib->physt = (u8)GET_RX_STATUS_DESC_PHY_STATUS_8814A(pdesc);//((le32_to_cpu(pdesc->rxdw0) >> 26) & 0x1);
pattrib->bdecrypted = !GET_RX_STATUS_DESC_SWDEC_8814A(pdesc);//(le32_to_cpu(pdesc->rxdw0) & BIT(27))? 0:1;
//Offset 4
pattrib->priority = (u8)GET_RX_STATUS_DESC_TID_8814A(pdesc);//((le32_to_cpu(pdesc->rxdw1) >> 8) & 0xf);
pattrib->mdata = (u8)GET_RX_STATUS_DESC_MORE_DATA_8814A(pdesc);//((le32_to_cpu(pdesc->rxdw1) >> 26) & 0x1);
pattrib->mfrag = (u8)GET_RX_STATUS_DESC_MORE_FRAG_8814A(pdesc);//((le32_to_cpu(pdesc->rxdw1) >> 27) & 0x1);//more fragment bit
//Offset 8
pattrib->seq_num = (u16)GET_RX_STATUS_DESC_SEQ_8814A(pdesc);//(le32_to_cpu(pdesc->rxdw2) & 0x00000fff);
pattrib->frag_num = (u8)GET_RX_STATUS_DESC_FRAG_8814A(pdesc);//((le32_to_cpu(pdesc->rxdw2) >> 12) & 0xf);//fragmentation number
if (GET_RX_STATUS_DESC_RPT_SEL_8814A(pdesc))
pattrib->pkt_rpt_type = C2H_PACKET;
else
pattrib->pkt_rpt_type = NORMAL_RX;
//Offset 12
pattrib->data_rate=(u8)GET_RX_STATUS_DESC_RX_RATE_8814A(pdesc);//((le32_to_cpu(pdesc->rxdw3))&0x7f);
//Offset 16
//Offset 20
}

114
hal/rtl8814a/rtl8814a_sreset.c 100644
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@ -0,0 +1,114 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#define _RTL8814A_SRESET_C_
//#include <drv_types.h>
#include <rtl8814a_hal.h>
#ifdef DBG_CONFIG_ERROR_DETECT
void rtl8814_sreset_xmit_status_check(_adapter *padapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
struct sreset_priv *psrtpriv = &pHalData->srestpriv;
unsigned long current_time;
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
unsigned int diff_time;
u32 txdma_status;
if( (txdma_status=rtw_read32(padapter, REG_TXDMA_STATUS)) !=0x00){
RTW_INFO("%s REG_TXDMA_STATUS:0x%08x\n", __FUNCTION__, txdma_status);
rtw_hal_sreset_reset(padapter);
}
#ifdef CONFIG_USB_HCI
//total xmit irp = 4
//DBG_8192C("==>%s free_xmitbuf_cnt(%d),txirp_cnt(%d)\n",__FUNCTION__,pxmitpriv->free_xmitbuf_cnt,pxmitpriv->txirp_cnt);
//if(pxmitpriv->txirp_cnt == NR_XMITBUFF+1)
current_time = rtw_get_current_time();
if (0 == pxmitpriv->free_xmitbuf_cnt || 0 == pxmitpriv->free_xmit_extbuf_cnt) {
diff_time = rtw_get_passing_time_ms(psrtpriv->last_tx_time);
if (diff_time > 2000) {
if (psrtpriv->last_tx_complete_time == 0) {
psrtpriv->last_tx_complete_time = current_time;
}
else{
diff_time = rtw_get_passing_time_ms(psrtpriv->last_tx_complete_time);
if (diff_time > 4000) {
u32 ability = 0;
//padapter->Wifi_Error_Status = WIFI_TX_HANG;
ability = rtw_phydm_ability_get(padapter);
RTW_INFO("%s tx hang %s\n", __FUNCTION__,
(ability & ODM_BB_ADAPTIVITY)? "ODM_BB_ADAPTIVITY" : "");
if (!(ability & ODM_BB_ADAPTIVITY))
rtw_hal_sreset_reset(padapter);
}
}
}
}
#endif //CONFIG_USB_HCI
if (psrtpriv->dbg_trigger_point == SRESET_TGP_XMIT_STATUS) {
psrtpriv->dbg_trigger_point = SRESET_TGP_NULL;
rtw_hal_sreset_reset(padapter);
return;
}
}
void rtl8814_sreset_linked_status_check(_adapter *padapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
struct sreset_priv *psrtpriv = &pHalData->srestpriv;
u32 rx_dma_status = 0;
rx_dma_status = rtw_read32(padapter,REG_RXDMA_STATUS);
if(rx_dma_status!= 0x00){
RTW_INFO("%s REG_RXDMA_STATUS:0x%08x\n",__FUNCTION__,rx_dma_status);
}
#if 0
u32 regc50,regc58,reg824,reg800;
regc50 = rtw_read32(padapter,0xc50);
regc58 = rtw_read32(padapter,0xc58);
reg824 = rtw_read32(padapter,0x824);
reg800 = rtw_read32(padapter,0x800);
if( ((regc50&0xFFFFFF00)!= 0x69543400)||
((regc58&0xFFFFFF00)!= 0x69543400)||
(((reg824&0xFFFFFF00)!= 0x00390000)&&(((reg824&0xFFFFFF00)!= 0x80390000)))||
( ((reg800&0xFFFFFF00)!= 0x03040000)&&((reg800&0xFFFFFF00)!= 0x83040000)))
{
DBG_8192C("%s regc50:0x%08x, regc58:0x%08x, reg824:0x%08x, reg800:0x%08x,\n", __FUNCTION__,
regc50, regc58, reg824, reg800);
rtw_hal_sreset_reset(padapter);
}
#endif
if (psrtpriv->dbg_trigger_point == SRESET_TGP_LINK_STATUS) {
psrtpriv->dbg_trigger_point = SRESET_TGP_NULL;
rtw_hal_sreset_reset(padapter);
return;
}
}
#endif

515
hal/rtl8814a/rtl8814a_xmit.c 100644
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@ -0,0 +1,515 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#define _RTL8814A_XMIT_C_
//#include <drv_types.h>
#include <rtl8814a_hal.h>
/*
* Description:
* Aggregation packets and send to hardware
*
* Return:
* 0 Success
* -1 Hardware resource(TX FIFO) not ready
* -2 Software resource(xmitbuf) not ready
*/
#ifdef CONFIG_TX_EARLY_MODE
//#define DBG_EMINFO
#if RTL8188E_EARLY_MODE_PKT_NUM_10 == 1
#define EARLY_MODE_MAX_PKT_NUM 10
#else
#define EARLY_MODE_MAX_PKT_NUM 5
#endif
struct EMInfo{
u8 EMPktNum;
u16 EMPktLen[EARLY_MODE_MAX_PKT_NUM];
};
void
InsertEMContent_8814(
struct EMInfo *pEMInfo,
IN pu1Byte VirtualAddress)
{
#if RTL8188E_EARLY_MODE_PKT_NUM_10 == 1
u1Byte index=0;
u4Byte dwtmp=0;
#endif
_rtw_memset(VirtualAddress, 0, EARLY_MODE_INFO_SIZE);
if(pEMInfo->EMPktNum==0)
return;
#ifdef DBG_EMINFO
{
int i;
RTW_INFO("\n%s ==> pEMInfo->EMPktNum =%d\n",__FUNCTION__,pEMInfo->EMPktNum);
for(i=0;i< EARLY_MODE_MAX_PKT_NUM;i++){
RTW_INFO("%s ==> pEMInfo->EMPktLen[%d] =%d\n",__FUNCTION__,i,pEMInfo->EMPktLen[i]);
}
}
#endif
#if RTL8188E_EARLY_MODE_PKT_NUM_10 == 1
SET_EARLYMODE_PKTNUM(VirtualAddress, pEMInfo->EMPktNum);
if(pEMInfo->EMPktNum == 1){
dwtmp = pEMInfo->EMPktLen[0];
}else{
dwtmp = pEMInfo->EMPktLen[0];
dwtmp += ((dwtmp%4)?(4-dwtmp%4):0)+4;
dwtmp += pEMInfo->EMPktLen[1];
}
SET_EARLYMODE_LEN0(VirtualAddress, dwtmp);
if(pEMInfo->EMPktNum <= 3){
dwtmp = pEMInfo->EMPktLen[2];
}else{
dwtmp = pEMInfo->EMPktLen[2];
dwtmp += ((dwtmp%4)?(4-dwtmp%4):0)+4;
dwtmp += pEMInfo->EMPktLen[3];
}
SET_EARLYMODE_LEN1(VirtualAddress, dwtmp);
if(pEMInfo->EMPktNum <= 5){
dwtmp = pEMInfo->EMPktLen[4];
}else{
dwtmp = pEMInfo->EMPktLen[4];
dwtmp += ((dwtmp%4)?(4-dwtmp%4):0)+4;
dwtmp += pEMInfo->EMPktLen[5];
}
SET_EARLYMODE_LEN2_1(VirtualAddress, dwtmp&0xF);
SET_EARLYMODE_LEN2_2(VirtualAddress, dwtmp>>4);
if(pEMInfo->EMPktNum <= 7){
dwtmp = pEMInfo->EMPktLen[6];
}else{
dwtmp = pEMInfo->EMPktLen[6];
dwtmp += ((dwtmp%4)?(4-dwtmp%4):0)+4;
dwtmp += pEMInfo->EMPktLen[7];
}
SET_EARLYMODE_LEN3(VirtualAddress, dwtmp);
if(pEMInfo->EMPktNum <= 9){
dwtmp = pEMInfo->EMPktLen[8];
}else{
dwtmp = pEMInfo->EMPktLen[8];
dwtmp += ((dwtmp%4)?(4-dwtmp%4):0)+4;
dwtmp += pEMInfo->EMPktLen[9];
}
SET_EARLYMODE_LEN4(VirtualAddress, dwtmp);
#else
SET_EARLYMODE_PKTNUM(VirtualAddress, pEMInfo->EMPktNum);
SET_EARLYMODE_LEN0(VirtualAddress, pEMInfo->EMPktLen[0]);
SET_EARLYMODE_LEN1(VirtualAddress, pEMInfo->EMPktLen[1]);
SET_EARLYMODE_LEN2_1(VirtualAddress, pEMInfo->EMPktLen[2]&0xF);
SET_EARLYMODE_LEN2_2(VirtualAddress, pEMInfo->EMPktLen[2]>>4);
SET_EARLYMODE_LEN3(VirtualAddress, pEMInfo->EMPktLen[3]);
SET_EARLYMODE_LEN4(VirtualAddress, pEMInfo->EMPktLen[4]);
#endif
//RT_PRINT_DATA(COMP_SEND, DBG_LOUD, "EMHdr:", VirtualAddress, 8);
}
void UpdateEarlyModeInfo8814(struct xmit_priv *pxmitpriv,struct xmit_buf *pxmitbuf )
{
//_adapter *padapter, struct xmit_frame *pxmitframe,struct tx_servq *ptxservq
int index,j;
u16 offset,pktlen;
PTXDESC_8814 ptxdesc;
u8 *pmem,*pEMInfo_mem;
s8 node_num_0=0,node_num_1=0;
struct EMInfo eminfo;
struct agg_pkt_info *paggpkt;
struct xmit_frame *pframe = (struct xmit_frame*)pxmitbuf->priv_data;
pmem= pframe->buf_addr;
#ifdef DBG_EMINFO
RTW_INFO("\n%s ==> agg_num:%d\n",__FUNCTION__, pframe->agg_num);
for(index=0;index<pframe->agg_num;index++){
offset = pxmitpriv->agg_pkt[index].offset;
pktlen = pxmitpriv->agg_pkt[index].pkt_len;
RTW_INFO("%s ==> agg_pkt[%d].offset=%d\n",__FUNCTION__,index,offset);
RTW_INFO("%s ==> agg_pkt[%d].pkt_len=%d\n",__FUNCTION__,index,pktlen);
}
#endif
if( pframe->agg_num > EARLY_MODE_MAX_PKT_NUM)
{
node_num_0 = pframe->agg_num;
node_num_1= EARLY_MODE_MAX_PKT_NUM-1;
}
for(index=0;index<pframe->agg_num;index++){
offset = pxmitpriv->agg_pkt[index].offset;
pktlen = pxmitpriv->agg_pkt[index].pkt_len;
_rtw_memset(&eminfo,0,sizeof(struct EMInfo));
if( pframe->agg_num > EARLY_MODE_MAX_PKT_NUM){
if(node_num_0 > EARLY_MODE_MAX_PKT_NUM){
eminfo.EMPktNum = EARLY_MODE_MAX_PKT_NUM;
node_num_0--;
}
else{
eminfo.EMPktNum = node_num_1;
node_num_1--;
}
}
else{
eminfo.EMPktNum = pframe->agg_num-(index+1);
}
for(j=0;j< eminfo.EMPktNum ;j++){
eminfo.EMPktLen[j] = pxmitpriv->agg_pkt[index+1+j].pkt_len+4;// 4 bytes CRC
}
if(pmem){
if(index==0){
ptxdesc = (PTXDESC_8814)(pmem);
pEMInfo_mem = ((u8 *)ptxdesc)+TXDESC_SIZE;
}
else{
pmem = pmem + pxmitpriv->agg_pkt[index-1].offset;
ptxdesc = (PTXDESC_8814)(pmem);
pEMInfo_mem = ((u8 *)ptxdesc)+TXDESC_SIZE;
}
#ifdef DBG_EMINFO
RTW_INFO("%s ==> desc.pkt_len=%d\n",__FUNCTION__,ptxdesc->pktlen);
#endif
InsertEMContent_8814(&eminfo,pEMInfo_mem);
}
}
_rtw_memset(pxmitpriv->agg_pkt,0,sizeof(struct agg_pkt_info)*MAX_AGG_PKT_NUM);
}
#endif
#if ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
void rtl8814a_cal_txdesc_chksum(u8 *ptxdesc)
{
u16 *usPtr;
u32 count;
u32 index;
u16 checksum = 0;
usPtr = (u16*)ptxdesc;
// checksume is always calculated by first 32 bytes,
// and it doesn't depend on TX DESC length.
// Thomas,Lucas@SD4,20130515
count = 16;
// Clear first
SET_TX_DESC_TX_DESC_CHECKSUM_8814A(ptxdesc, 0);
for(index = 0 ; index < count ; index++){
checksum = checksum ^ le16_to_cpu(*(usPtr + index));
}
SET_TX_DESC_TX_DESC_CHECKSUM_8814A(ptxdesc, checksum);
}
#endif
//
// Description: In normal chip, we should send some packet to Hw which will be used by Fw
// in FW LPS mode. The function is to fill the Tx descriptor of this packets, then
// Fw can tell Hw to send these packet derectly.
//
void rtl8814a_fill_fake_txdesc(
PADAPTER padapter,
u8* pDesc,
u32 BufferLen,
u8 IsPsPoll,
u8 IsBTQosNull,
u8 bDataFrame)
{
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
// Clear all status
_rtw_memset(pDesc, 0, TXDESC_SIZE);
SET_TX_DESC_LAST_SEG_8814A(pDesc, 1);
SET_TX_DESC_OFFSET_8814A(pDesc, TXDESC_SIZE);
SET_TX_DESC_PKT_SIZE_8814A(pDesc, BufferLen);
SET_TX_DESC_QUEUE_SEL_8814A(pDesc, QSLT_MGNT);
if (pmlmeext->cur_wireless_mode & WIRELESS_11B) {
SET_TX_DESC_RATE_ID_8814A(pDesc, RATEID_IDX_B);
} else {
SET_TX_DESC_RATE_ID_8814A(pDesc, RATEID_IDX_G);
}
//Set NAVUSEHDR to prevent Ps-poll AId filed to be changed to error vlaue by Hw.
if (IsPsPoll)
{
SET_TX_DESC_NAV_USE_HDR_8814A(pDesc, 1);
}
else
{
SET_TX_DESC_HWSEQ_EN_8814A(pDesc, 1); // Hw set sequence number
}
#if 0 //todo
if(IsBTQosNull)
{
SET_TX_DESC_BT_INT_8812(pDesc, 1);
}
#endif //0
SET_TX_DESC_USE_RATE_8814A(pDesc, 1);
//8814 no OWN bit?
//SET_TX_DESC_OWN_8812(pDesc, 1);
//
// Encrypt the data frame if under security mode excepct null data. Suggested by CCW.
//
if (_TRUE ==bDataFrame)
{
u32 EncAlg;
EncAlg = padapter->securitypriv.dot11PrivacyAlgrthm;
switch (EncAlg)
{
case _NO_PRIVACY_:
SET_TX_DESC_SEC_TYPE_8814A(pDesc, 0x0);
break;
case _WEP40_:
case _WEP104_:
case _TKIP_:
SET_TX_DESC_SEC_TYPE_8814A(pDesc, 0x1);
break;
case _SMS4_:
SET_TX_DESC_SEC_TYPE_8814A(pDesc, 0x2);
break;
case _AES_:
SET_TX_DESC_SEC_TYPE_8814A(pDesc, 0x3);
break;
default:
SET_TX_DESC_SEC_TYPE_8814A(pDesc, 0x0);
break;
}
}
SET_TX_DESC_TX_RATE_8814A(pDesc, MRateToHwRate(pmlmeext->tx_rate));
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
// USB interface drop packet if the checksum of descriptor isn't correct.
// Using this checksum can let hardware recovery from packet bulk out error (e.g. Cancel URC, Bulk out error.).
rtl8814a_cal_txdesc_chksum(pDesc);
#endif
}
void rtl8814a_fill_txdesc_sectype(struct pkt_attrib *pattrib, u8 *ptxdesc)
{
if ((pattrib->encrypt > 0) && !pattrib->bswenc)
{
switch (pattrib->encrypt)
{
//SEC_TYPE : 0:NO_ENC,1:WEP40/TKIP,2:WAPI,3:AES
case _WEP40_:
case _WEP104_:
case _TKIP_:
case _TKIP_WTMIC_:
SET_TX_DESC_SEC_TYPE_8814A(ptxdesc, 0x1);
break;
#ifdef CONFIG_WAPI_SUPPORT
case _SMS4_:
SET_TX_DESC_SEC_TYPE_8814A(ptxdesc, 0x2);
break;
#endif
case _AES_:
SET_TX_DESC_SEC_TYPE_8814A(ptxdesc, 0x3);
break;
case _NO_PRIVACY_:
default:
SET_TX_DESC_SEC_TYPE_8814A(ptxdesc, 0x0);
break;
}
}
}
void rtl8814a_fill_txdesc_vcs(PADAPTER padapter, struct pkt_attrib *pattrib, u8 *ptxdesc)
{
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
//RTW_INFO("vcs_mode=%d\n", pattrib->vcs_mode);
if (pattrib->vcs_mode) {
switch(pattrib->vcs_mode)
{
case RTS_CTS:
SET_TX_DESC_RTS_ENABLE_8814A(ptxdesc, 1);
break;
case CTS_TO_SELF:
SET_TX_DESC_CTS2SELF_8814A(ptxdesc, 1);
break;
case NONE_VCS:
default:
break;
}
if (pmlmeinfo->preamble_mode == PREAMBLE_SHORT)
SET_TX_DESC_RTS_SHORT_8814A(ptxdesc, 1);
SET_TX_DESC_RTS_RATE_8814A(ptxdesc, 0x8);//RTS Rate=24M
SET_TX_DESC_RTS_RATE_FB_LIMIT_8814A(ptxdesc, 0xf);
}
}
u8
BWMapping_8814(
IN PADAPTER Adapter,
IN struct pkt_attrib *pattrib
)
{
u8 BWSettingOfDesc = 0;
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
//RTW_INFO("BWMapping pHalData->current_channel_bw %d, pattrib->bwmode %d \n",pHalData->current_channel_bw,pattrib->bwmode);
if(pHalData->current_channel_bw== CHANNEL_WIDTH_80)
{
if(pattrib->bwmode == CHANNEL_WIDTH_80)
BWSettingOfDesc= 2;
else if(pattrib->bwmode == CHANNEL_WIDTH_40)
BWSettingOfDesc = 1;
else
BWSettingOfDesc = 0;
}
else if(pHalData->current_channel_bw== CHANNEL_WIDTH_40)
{
if((pattrib->bwmode == CHANNEL_WIDTH_40) || (pattrib->bwmode == CHANNEL_WIDTH_80))
BWSettingOfDesc = 1;
else
BWSettingOfDesc = 0;
}
else
BWSettingOfDesc = 0;
return BWSettingOfDesc;
}
u8
SCMapping_8814(
IN PADAPTER Adapter,
IN struct pkt_attrib *pattrib
)
{
u8 SCSettingOfDesc = 0;
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
//RTW_INFO("SCMapping: pHalData->current_channel_bw %d, pHalData->nCur80MhzPrimeSC %d, pHalData->nCur40MhzPrimeSC %d \n",pHalData->current_channel_bw,pHalData->nCur80MhzPrimeSC,pHalData->nCur40MhzPrimeSC);
if(pHalData->current_channel_bw == CHANNEL_WIDTH_80)
{
if(pattrib->bwmode == CHANNEL_WIDTH_80)
{
SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
}
else if(pattrib->bwmode == CHANNEL_WIDTH_40)
{
if(pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
SCSettingOfDesc = VHT_DATA_SC_40_LOWER_OF_80MHZ;
else if(pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
SCSettingOfDesc = VHT_DATA_SC_40_UPPER_OF_80MHZ;
else
RTW_INFO("SCMapping: DONOT CARE Mode Setting\n");
}
else
{
if((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
SCSettingOfDesc = VHT_DATA_SC_20_LOWEST_OF_80MHZ;
else if((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
SCSettingOfDesc = VHT_DATA_SC_20_LOWER_OF_80MHZ;
else if((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
SCSettingOfDesc = VHT_DATA_SC_20_UPPER_OF_80MHZ;
else if((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
SCSettingOfDesc = VHT_DATA_SC_20_UPPERST_OF_80MHZ;
else
RTW_INFO("SCMapping: DONOT CARE Mode Setting\n");
}
}
else if(pHalData->current_channel_bw== CHANNEL_WIDTH_40)
{
//RTW_INFO("SCMapping: HT Case: pHalData->current_channel_bw %d, pHalData->nCur40MhzPrimeSC %d \n",pHalData->current_channel_bw,pHalData->nCur40MhzPrimeSC);
if(pattrib->bwmode == CHANNEL_WIDTH_40)
{
SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
}
else if(pattrib->bwmode == CHANNEL_WIDTH_20)
{
if(pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
{
SCSettingOfDesc = VHT_DATA_SC_20_UPPER_OF_80MHZ;
}
else if(pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
{
SCSettingOfDesc = VHT_DATA_SC_20_LOWER_OF_80MHZ;
}
else
{
SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
}
}
}
else
{
SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
}
return SCSettingOfDesc;
}
void rtl8814a_fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, u8 *ptxdesc)
{
//RTW_INFO("bwmode=%d, ch_off=%d\n", pattrib->bwmode, pattrib->ch_offset);
if(pattrib->ht_en)
{
// Set Bandwidth and sub-channel settings.
SET_TX_DESC_DATA_BW_8814A(ptxdesc, BWMapping_8814(padapter,pattrib));
SET_TX_DESC_DATA_SC_8814A(ptxdesc, SCMapping_8814(padapter,pattrib));
}
}

147
hal/rtl8814a/usb/rtl8814au_led.c 100644
View File

@ -0,0 +1,147 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#define _RTL8814AU_LED_C_
//#include <drv_types.h>
#include <rtl8814a_hal.h>
#ifdef CONFIG_RTW_SW_LED
//================================================================================
// LED object.
//================================================================================
//================================================================================
// Prototype of protected function.
//================================================================================
//================================================================================
// LED_819xUsb routines.
//================================================================================
//
// Description:
// Turn on LED according to LedPin specified.
//
static void
SwLedOn_8814AU(
PADAPTER padapter,
PLED_USB pLed
)
{
u32 LedGpioCfg;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
if (RTW_CANNOT_RUN(padapter))
return;
LedGpioCfg = rtw_read32(padapter , REG_GPIO_PIN_CTRL_2); /* 0x60. In 8814AU, the name should be REG_GPIO_EXT_CTRL */
switch (pLed->LedPin) {
case LED_PIN_LED0:
LedGpioCfg |= (BIT16 | BIT17 | BIT21 | BIT22); /* config as gpo */
LedGpioCfg &= ~(BIT8 | BIT9 | BIT13 | BIT14); /* set gpo value */
LedGpioCfg &= ~(BIT0 | BIT1 | BIT5 | BIT6); /* set gpi value. TBD: may not need this */
rtw_write32(padapter , REG_GPIO_PIN_CTRL_2 , LedGpioCfg);
break;
default:
break;
}
pLed->bLedOn = _TRUE;
}
//
// Description:
// Turn off LED according to LedPin specified.
//
static void
SwLedOff_8814AU(
PADAPTER padapter,
PLED_USB pLed
)
{
u32 LedGpioCfg;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
if (RTW_CANNOT_RUN(padapter))
return;
LedGpioCfg = rtw_read32(padapter , REG_GPIO_PIN_CTRL_2); /* 0x60. In 8814AU, the name should be REG_GPIO_EXT_CTRL */
switch (pLed->LedPin) {
case LED_PIN_LED0:
LedGpioCfg |= (BIT16 | BIT17 | BIT21 | BIT22); /* config as gpo */
LedGpioCfg |= (BIT8 | BIT9 | BIT13 | BIT14); /* set gpo output value */
rtw_write32(padapter , REG_GPIO_PIN_CTRL_2 , LedGpioCfg);
break;
default:
break;
}
pLed->bLedOn = _FALSE;
}
//================================================================================
// Interface to manipulate LED objects.
//================================================================================
//================================================================================
// Default LED behavior.
//================================================================================
//
// Description:
// Initialize all LED_871x objects.
//
void
rtl8814au_InitSwLeds(
_adapter *padapter
)
{
struct led_priv *pledpriv = adapter_to_led(padapter);
pledpriv->LedControlHandler = LedControlUSB;
pledpriv->SwLedOn = SwLedOn_8814AU;
pledpriv->SwLedOff = SwLedOff_8814AU;
InitLed(padapter, &(pledpriv->SwLed0), LED_PIN_LED0);
InitLed(padapter, &(pledpriv->SwLed1), LED_PIN_LED1);
InitLed(padapter, &(pledpriv->SwLed2), LED_PIN_LED2);
}
//
// Description:
// DeInitialize all LED_819xUsb objects.
//
void
rtl8814au_DeInitSwLeds(
_adapter *padapter
)
{
struct led_priv *ledpriv = adapter_to_led(padapter);
DeInitLed( &(ledpriv->SwLed0) );
DeInitLed( &(ledpriv->SwLed1) );
DeInitLed( &(ledpriv->SwLed2) );
}
#endif

34
hal/rtl8814a/usb/rtl8814au_recv.c 100644
View File

@ -0,0 +1,34 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#define _RTL8814AU_RECV_C_
//#include <drv_types.h>
#include <rtl8814a_hal.h>
int rtl8814au_init_recv_priv(_adapter *padapter)
{
return usb_init_recv_priv(padapter, INTERRUPT_MSG_FORMAT_LEN);
}
void rtl8814au_free_recv_priv(_adapter *padapter)
{
usb_free_recv_priv(padapter, INTERRUPT_MSG_FORMAT_LEN);
}

1155
hal/rtl8814a/usb/rtl8814au_xmit.c 100644
View File

File diff suppressed because it is too large Load Diff

2415
hal/rtl8814a/usb/usb_halinit.c 100644
View File

File diff suppressed because it is too large Load Diff

314
hal/rtl8814a/usb/usb_ops_linux.c 100644
View File

@ -0,0 +1,314 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HCI_OPS_OS_C_
/* #include <drv_types.h> */
#include <rtl8814a_hal.h>
#ifdef CONFIG_SUPPORT_USB_INT
void interrupt_handler_8814au(_adapter *padapter, u16 pkt_len, u8 *pbuf)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
struct reportpwrstate_parm pwr_rpt;
if (pkt_len != INTERRUPT_MSG_FORMAT_LEN) {
RTW_INFO("%s Invalid interrupt content length (%d)!\n", __FUNCTION__, pkt_len);
return ;
}
/* HISR */
_rtw_memcpy(&(pHalData->IntArray[0]), &(pbuf[USB_INTR_CONTENT_HISR_OFFSET]), 4);
_rtw_memcpy(&(pHalData->IntArray[1]), &(pbuf[USB_INTR_CONTENT_HISRE_OFFSET]), 4);
#if 0 /*DBG*/
{
u32 hisr = 0 , hisr_ex = 0;
_rtw_memcpy(&hisr, &(pHalData->IntArray[0]), 4);
hisr = le32_to_cpu(hisr);
_rtw_memcpy(&hisr_ex, &(pHalData->IntArray[1]), 4);
hisr_ex = le32_to_cpu(hisr_ex);
if ((hisr != 0) || (hisr_ex != 0))
RTW_INFO("===> %s hisr:0x%08x ,hisr_ex:0x%08x\n", __FUNCTION__, hisr, hisr_ex);
}
#endif
#ifdef CONFIG_LPS_LCLK
if (pHalData->IntArray[0] & IMR_CPWM_88E) {
_rtw_memcpy(&pwr_rpt.state, &(pbuf[USB_INTR_CONTENT_CPWM1_OFFSET]), 1);
/* _rtw_memcpy(&pwr_rpt.state2, &(pbuf[USB_INTR_CONTENT_CPWM2_OFFSET]), 1); */
/* 88e's cpwm value only change BIT0, so driver need to add PS_STATE_S2 for LPS flow. */
pwr_rpt.state |= PS_STATE_S2;
_set_workitem(&(adapter_to_pwrctl(padapter)->cpwm_event));
}
#endif/* CONFIG_LPS_LCLK */
#ifdef CONFIG_INTERRUPT_BASED_TXBCN
#ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
if (pHalData->IntArray[0] & IMR_BCNDMAINT0_88E)
#endif
#ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
if (pHalData->IntArray[0] & (IMR_TBDER_88E | IMR_TBDOK_88E))
#endif
{
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
#if 0
if (pHalData->IntArray[0] & IMR_BCNDMAINT0_88E)
RTW_INFO("%s: HISR_BCNERLY_INT\n", __func__);
if (pHalData->IntArray[0] & IMR_TBDOK_88E)
RTW_INFO("%s: HISR_TXBCNOK\n", __func__);
if (pHalData->IntArray[0] & IMR_TBDER_88E)
RTW_INFO("%s: HISR_TXBCNERR\n", __func__);
#endif /* 0 */
if(check_fwstate(pmlmepriv, WIFI_AP_STATE))
{
//send_beacon(padapter);
if(pmlmepriv->update_bcn == _TRUE)
{
//tx_beacon_hdl(padapter, NULL);
set_tx_beacon_cmd(padapter);
}
}
#ifdef CONFIG_CONCURRENT_MODE
if(check_buddy_fwstate(padapter, WIFI_AP_STATE))
{
//send_beacon(padapter);
if(padapter->pbuddy_adapter->mlmepriv.update_bcn == _TRUE)
{
//tx_beacon_hdl(padapter, NULL);
set_tx_beacon_cmd(padapter->pbuddy_adapter);
}
}
#endif
}
#endif /* CONFIG_INTERRUPT_BASED_TXBCN */
#ifdef DBG_CONFIG_ERROR_DETECT_INT
if (pHalData->IntArray[1] & IMR_TXERR_88E)
RTW_INFO("===> %s Tx Error Flag Interrupt Status\n", __FUNCTION__);
if (pHalData->IntArray[1] & IMR_RXERR_88E)
RTW_INFO("===> %s Rx Error Flag INT Status\n", __FUNCTION__);
if (pHalData->IntArray[1] & IMR_TXFOVW_88E)
RTW_INFO("===> %s Transmit FIFO Overflow\n", __FUNCTION__);
if (pHalData->IntArray[1] & IMR_RXFOVW_88E)
RTW_INFO("===> %s Receive FIFO Overflow\n", __FUNCTION__);
#endif/* DBG_CONFIG_ERROR_DETECT_INT */
#ifdef CONFIG_FW_C2H_REG
/* C2H Event */
if (pbuf[0] != 0)
usb_c2h_hisr_hdl(padapter, pbuf);
#endif
}
#endif /* CONFIG_SUPPORT_USB_INT */
#if 0
int recvbuf2recvframe(PADAPTER padapter, void *ptr)
{
u8 *pbuf;
u8 pkt_cnt = 0;
u32 pkt_offset;
s32 transfer_len;
u8 *pphy_status = NULL;
union recv_frame *precvframe = NULL;
struct rx_pkt_attrib *pattrib = NULL;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
struct recv_priv *precvpriv = &padapter->recvpriv;
_queue *pfree_recv_queue = &precvpriv->free_recv_queue;
_pkt *pskb;
#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX
pskb = NULL;
transfer_len = (s32)((struct recv_buf *)ptr)->transfer_len;
pbuf = ((struct recv_buf *)ptr)->pbuf;
#else
pskb = (_pkt *)ptr;
transfer_len = (s32)pskb->len;
pbuf = pskb->data;
#endif/* CONFIG_USE_USB_BUFFER_ALLOC_RX */
#ifdef CONFIG_USB_RX_AGGREGATION
pkt_cnt = GET_RX_STATUS_DESC_DMA_AGG_NUM_8814A(pbuf);
#endif
do {
precvframe = rtw_alloc_recvframe(pfree_recv_queue);
if (precvframe == NULL) {
RTW_INFO("%s()-%d: rtw_alloc_recvframe() failed! RX Drop!\n", __FUNCTION__, __LINE__);
goto _exit_recvbuf2recvframe;
}
_rtw_init_listhead(&precvframe->u.hdr.list);
precvframe->u.hdr.precvbuf = NULL; /* can't access the precvbuf for new arch. */
precvframe->u.hdr.len = 0;
rtl8814_query_rx_desc_status(precvframe, pbuf);
pattrib = &precvframe->u.hdr.attrib;
if ((padapter->registrypriv.mp_mode == 0) && ((pattrib->crc_err) || (pattrib->icv_err))) {
RTW_INFO("%s: RX Warning! crc_err=%d icv_err=%d, skip!\n", __FUNCTION__, pattrib->crc_err, pattrib->icv_err);
rtw_free_recvframe(precvframe, pfree_recv_queue);
goto _exit_recvbuf2recvframe;
}
pkt_offset = RXDESC_SIZE + pattrib->drvinfo_sz + pattrib->shift_sz + pattrib->pkt_len;
if ((pattrib->pkt_len <= 0) || (pkt_offset > transfer_len)) {
RTW_INFO("%s()-%d: RX Warning!,pkt_len<=0 or pkt_offset> transfer_len\n", __FUNCTION__, __LINE__);
rtw_free_recvframe(precvframe, pfree_recv_queue);
goto _exit_recvbuf2recvframe;
}
#ifdef CONFIG_RX_PACKET_APPEND_FCS
if(pattrib->pkt_rpt_type == NORMAL_RX)
pattrib->pkt_len -= IEEE80211_FCS_LEN;
#endif
if (rtw_os_alloc_recvframe(padapter, precvframe,
(pbuf + pattrib->shift_sz + pattrib->drvinfo_sz + RXDESC_SIZE), pskb) == _FAIL) {
rtw_free_recvframe(precvframe, pfree_recv_queue);
goto _exit_recvbuf2recvframe;
}
recvframe_put(precvframe, pattrib->pkt_len);
/* recvframe_pull(precvframe, drvinfo_sz + RXDESC_SIZE); */
if(pattrib->pkt_rpt_type == NORMAL_RX)//Normal rx packet
{
if(pattrib->physt)
pphy_status = (pbuf + RXDESC_OFFSET);
#ifdef CONFIG_CONCURRENT_MODE
if(rtw_buddy_adapter_up(padapter))
{
if(pre_recv_entry(precvframe, pphy_status) != _SUCCESS)
{
RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,
("recvbuf2recvframe: recv_entry(precvframe) != _SUCCESS\n"));
}
}
#endif //CONFIG_CONCURRENT_MODE
if(pattrib->physt && pphy_status)
rx_query_phy_status(precvframe, pphy_status);
if(rtw_recv_entry(precvframe) != _SUCCESS)
{
RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,
("recvbuf2recvframe: rtw_recv_entry(precvframe) != _SUCCESS\n"));
}
}
else{ // pkt_rpt_type == TX_REPORT1-CCX, TX_REPORT2-TX RTP,HIS_REPORT-USB HISR RTP
if (pattrib->pkt_rpt_type == C2H_PACKET) {
//RTW_INFO("rx C2H_PACKET \n");
rtw_hal_c2h_pkt_pre_hdl(padapter,precvframe->u.hdr.rx_data,pattrib->pkt_len);
}
rtw_free_recvframe(precvframe, pfree_recv_queue);
}
#ifdef CONFIG_USB_RX_AGGREGATION
/* jaguar 8-byte alignment */
pkt_offset = (u16)_RND8(pkt_offset);
pkt_cnt--;
pbuf += pkt_offset;
#endif
transfer_len -= pkt_offset;
precvframe = NULL;
} while (transfer_len > 0);
_exit_recvbuf2recvframe:
return _SUCCESS;
}
#endif
void rtl8814au_xmit_tasklet(void *priv)
{
int ret = _FALSE;
_adapter *padapter = (_adapter*)priv;
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
while(1)
{
if (RTW_CANNOT_TX(padapter))
{
RTW_INFO("xmit_tasklet => bDriverStopped or bSurpriseRemoved or bWritePortCancel\n");
break;
}
if (rtw_xmit_ac_blocked(padapter) == _TRUE)
break;
ret = rtl8814au_xmitframe_complete(padapter, pxmitpriv, NULL);
if(ret==_FALSE)
break;
}
}
void rtl8814au_set_intf_ops(struct _io_ops *pops)
{
_rtw_memset((u8 *)pops, 0, sizeof(struct _io_ops));
pops->_read8 = &usb_read8;
pops->_read16 = &usb_read16;
pops->_read32 = &usb_read32;
pops->_read_mem = &usb_read_mem;
pops->_read_port = &usb_read_port;
pops->_write8 = &usb_write8;
pops->_write16 = &usb_write16;
pops->_write32 = &usb_write32;
pops->_writeN = &usb_writeN;
#ifdef CONFIG_USB_SUPPORT_ASYNC_VDN_REQ
pops->_write8_async= &usb_async_write8;
pops->_write16_async = &usb_async_write16;
pops->_write32_async = &usb_async_write32;
#endif
pops->_write_mem = &usb_write_mem;
pops->_write_port = &usb_write_port;
pops->_read_port_cancel = &usb_read_port_cancel;
pops->_write_port_cancel = &usb_write_port_cancel;
#ifdef CONFIG_USB_INTERRUPT_IN_PIPE
pops->_read_interrupt = &usb_read_interrupt;
#endif
}
void rtl8814au_set_hw_type(struct dvobj_priv *pdvobj)
{
pdvobj->HardwareType = HARDWARE_TYPE_RTL8814AU;
RTW_INFO("CHIP TYPE: RTL8814\n");
}

6
include/Hal8814PhyCfg.h
View File

@ -132,7 +132,7 @@ phy_get_tx_power_index_8814a(
);
u8
PHY_GetTxPowerIndex8814A(
PHY_GetTxPowerIndex_8814A(
IN PADAPTER Adapter,
IN enum rf_path RFPath,
IN u8 Rate,
@ -206,8 +206,8 @@ PHY_HandleSwChnlAndSetBW8814A(
);
BOOLEAN
PHY_QueryRFPathSwitch_8814A(IN PADAPTER pAdapter);
/* BOOLEAN */
/* PHY_QueryRFPathSwitch_8814A(IN PADAPTER pAdapter); */

14
include/Hal8814PwrSeq.h
View File

@ -76,9 +76,9 @@
{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /* 0x2[0] = 0 RESET BB, CLOSE RF */ \
{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, /*Delay 1us*/ \
{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \
{0x1002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /* 0x2[0] = 0 RESET BB, CLOSE RF */ \
{0x0002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, /*Delay 1us*/ \
{0x1002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \
{0x1002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, /* 0x2[0] = 0 RESET BB, CLOSE RF */ \
{0x0002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, /*Delay 1us*/ \
{0x1002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \
{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*0x1F[7:0] = 0 turn off RF*/ \
/*{0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},*/ /*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x28}, /* 0x07[7:0] = 0x28 sps pwm mode 0x2a for BT coex*/ \
@ -188,9 +188,9 @@
{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated, and RF closed*/ \
{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \
{0x1002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated, and RF closed*/ \
{0x0002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
{0x1002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \
{0x1002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled, and clock are gated, and RF closed*/ \
{0x0002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
{0x1002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0}, /* Whole BB is reset*/ \
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
{0x05F1, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*Respond TxOK to scheduler*/
@ -209,7 +209,7 @@
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/ \
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/ \
{0x0002, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/ \
{0x1002, ~PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*. 0x1002[1:0] = 2b'11 enable BB macro*/ \
{0x1002, (u8)(~PWR_CUT_TESTCHIP_MSK), PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1 | BIT0, BIT1 | BIT0}, /*. 0x1002[1:0] = 2b'11 enable BB macro*/ \
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
#define RTL8814A_TRANS_END \

6
include/rtl8814a_hal.h
View File

@ -33,10 +33,6 @@
#include "rtl8814a_sreset.h"
#endif /* DBG_CONFIG_ERROR_DETECT */
enum {
VOLTAGE_V25 = 0x03,
LDOE25_SHIFT = 28 ,
};
/* max. iram is 64k , max dmen is 32k. Total = 96k = 0x18000*/
#define FW_SIZE 0x18000
#define FW_START_ADDRESS 0x1000
@ -175,8 +171,6 @@ typedef struct _RT_FIRMWARE_8814 {
#define BCN_DMA_ATIME_INT_TIME_8814 0x02
#define MAX_PAGE_SIZE 4096 /* @ page : 4k bytes */
#define EFUSE_MAX_SECTION_JAGUAR 64
#define HWSET_MAX_SIZE_8814A 512

6
include/rtl8814a_spec.h
View File

@ -645,4 +645,10 @@ So the following defines for 92C is not entire!!!!!!
#define LAST_ENTRY_OF_TX_PKT_BUFFER_8814A (2048-1) /* 20130415 KaiYuan add for 8814 */
#define MACID_NUM_8814A 128
#define SEC_CAM_ENT_NUM_8814A 64
#define BAND_CAP_8814A (BAND_CAP_2G | BAND_CAP_5G)
#define BW_CAP_8814A (BW_CAP_20M | BW_CAP_40M | BW_CAP_80M)
#define PROTO_CAP_8814A (PROTO_CAP_11B | PROTO_CAP_11G | PROTO_CAP_11N | PROTO_CAP_11AC)
#endif /* __RTL8814A_SPEC_H__ */

6
include/rtl8814a_xmit.h
View File

@ -125,10 +125,10 @@ typedef struct txdescriptor_8814 {
#define SET_TX_DESC_HTC_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)
#define SET_TX_DESC_LAST_SEG_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 26, 1, __Value)
#define SET_TX_DESC_LINIP_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 28, 1, __Value)
#define SET_TX_DESC_AMSDU_PAD_EN_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)
#define SET_TX_DESC_FIRST_SEG_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)
#define SET_TX_DESC_NO_ACM_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)
#define SET_TX_DESC_GF_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)
#define SET_TX_DESC_DISQSELSEQ_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
#define SET_TX_DESC_OWN_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
/* Dword 1 */
#define SET_TX_DESC_MACID_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)
@ -152,7 +152,7 @@ typedef struct txdescriptor_8814 {
#define SET_TX_DESC_RDG_ENABLE_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)
#define SET_TX_DESC_NULL_0_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 14, 1, __Value)
#define SET_TX_DESC_NULL_1_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 15, 1, __Value)
#define SET_TX_DESC_BK_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)
#define SET_TX_DESC_AGG_BREAK_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)
#define SET_TX_DESC_MORE_FRAG_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)
#define GET_TX_DESC_MORE_FRAG_8814A(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+8, 17, 1)
#define SET_TX_DESC_RAW_8814A(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)