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rtl8812au
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Merge pull request #145 from kimocoder/v5.2.9 

Uploading the v5.2.9.3 driver with 8821 support
v5.2.9
Christian B 2018-07-02 15:05:54 +02:00 committed by GitHub
parent 68fdb1e22c 2c65ba23dc
commit c0d04c740e
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
86 changed files with 32692 additions and 15609 deletions
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15
Makefile
View File

@ -1,5 +1,5 @@
EXTRA_CFLAGS += $(USER_EXTRA_CFLAGS)
EXTRA_CFLAGS += -O3
EXTRA_CFLAGS += -O1
#EXTRA_CFLAGS += -O3
#EXTRA_CFLAGS += -Wall
#EXTRA_CFLAGS += -Wextra
@ -13,8 +13,7 @@ EXTRA_CFLAGS += -Wno-unused-label
EXTRA_CFLAGS += -Wno-unused-parameter
EXTRA_CFLAGS += -Wno-unused-function
EXTRA_CFLAGS += -Wno-unused
EXTRA_CFLAGS += -Wno-uninitialized
EXTRA_CFLAGS += -Wno-array-bounds
#EXTRA_CFLAGS += -Wno-uninitialized
GCC_VER_49 := $(shell echo `$(CC) -dumpversion | cut -f1-2 -d.` \>= 4.9 | bc )
ifeq ($(GCC_VER_49),1)
@ -31,7 +30,7 @@ CONFIG_AUTOCFG_CP = n
CONFIG_MULTIDRV = n
CONFIG_RTL8188E = n
CONFIG_RTL8812A = y
CONFIG_RTL8821A = n
CONFIG_RTL8821A = y
CONFIG_RTL8192E = n
CONFIG_RTL8723B = n
CONFIG_RTL8814A = n
@ -58,8 +57,9 @@ CONFIG_EFUSE_CONFIG_FILE = y
CONFIG_EXT_CLK = n
CONFIG_TRAFFIC_PROTECT = y
CONFIG_LOAD_PHY_PARA_FROM_FILE = y
CONFIG_TXPWR_BY_RATE_EN = n
CONFIG_TXPWR_BY_RATE_EN = y
CONFIG_TXPWR_LIMIT_EN = n
CONFIG_CALIBRATE_TX_POWER_TO_MAX = y
CONFIG_RTW_ADAPTIVITY_EN = disable
CONFIG_RTW_ADAPTIVITY_MODE = normal
CONFIG_SIGNAL_SCALE_MAPPING = n
@ -967,7 +967,8 @@ EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT
SUBARCH := $(shell uname -m | sed -e s/i.86/i386/)
ARCH ?= $(SUBARCH)
CROSS_COMPILE ?=
KVER := $(shell uname -r)
#KVER := $(shell uname -r)
KVER := $(shell make -C /usr/src/linux -s kernelversion)
KSRC := /lib/modules/$(KVER)/build
MODDESTDIR := /lib/modules/$(KVER)/kernel/drivers/net/wireless/
INSTALL_PREFIX :=
@ -1863,6 +1864,6 @@ clean:
cd platform ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko
rm -fr Module.symvers ; rm -fr Module.markers ; rm -fr modules.order
rm -fr *.mod.c *.mod *.o .*.cmd *.ko *~
rm -fr .tmp_versions
rm -fr .tmp_versions .cache.mk
endif

63
README.md
View File

@ -1,61 +1,6 @@
# RTL8812AU/21AU and RTL8814AU drivers
# with monitor mode and frame injection
# currently ONLY supports RTL8812AU, NOT the RTL8814AU. SEE TODO
# rtl8812AU
Realtek 8812AU USB WiFi driver
## TODO
* Support for RTL8814AU (adding HAL) should be added, a patch on the v5.1.5 branch could be modified and used
see https://github.com/aircrack-ng/rtl8812au/commit/55e81afe4f9fa556cafe6e789b91043535d85b3a
It needs some modifications in order to "fit", both in Makefile and other files. Some work is currently ongoing, but
feel free to team up on it here with us. Check .rej files after patching and see what needs to be modified.
This is a fork, with various patches to compile against latest kernels (tested up to 4.17.3)
## DKMS
This driver can be installed using [DKMS]. This is a system which will automatically recompile and install a kernel module when a new kernel gets installed or updated. To make use of DKMS, install the `dkms` package, which on Debian (based) systems is done like this:
```
sudo apt install dkms
```
## Installation of Driver
In order to install the driver open a terminal in the directory with the source code and execute the following command:
```
sudo ./dkms-install.sh
```
## Removal of Driver
In order to remove the driver from your system open a terminal in the directory with the source code and execute the following command:
```
sudo ./dkms-remove.sh
```
## Make
For building & installing the RTL8812AU driver with 'make' use
```
make
make install
```
## Notes
For Ubuntu 17.04 add the following lines
```
[device]
wifi.scan-rand-mac-address=no
```
at the end of file /etc/NetworkManager/NetworkManager.conf and restart NetworkManager with the command:
```
sudo service NetworkManager restart
```
## Credits
```
astsam - for the main work + monitor/injection support - https://github.com/astsam
```
## Other Sources
```
astsam - https://github.com/astsam/rtl8812au
gnab - https://github.com/gnab/rtl8812au
zebulon2 - https://github.com/zebulon2/rtl8812au
paspro - https://github.com/paspro/rtl8812au
ulli-kroll - https://github.com/ulli-kroll/rtl8821au
```
branch 5.2.9 is using driver 5.2.9.3 + patch to add support of 8821au

108
Realtek_Changelog.txt 100644
View File

@ -0,0 +1,108 @@
Product: RTL8812A USB Software Package - Linux Driver
Version: v5.2.9.3_24903.20171101
Release History:
v5.2.9.3_24903.20171101
1. Fixed WPA2 vulnerability - key reinstallation attacks(KRACKs)
v5.2.9.2_24491.20171027
1. Remove test code
2. Fix crash for BF function
3. Fix wrong memory accesse
4. Fix encrypt broadcast packet fail
5. Fix crash for TDLS
v5.2.9.1_24461.20171018
1. (Do not use)
v5.2.9_22809.20170621
Update FW to v52.2
Update PHYDM setting
Support PNO
Fix WOW issue
Fix efuse issue
Sync channel plan document
Fix DFS issue
Support NAPI & GRO
Enable Power by rate
Fix MP power tracking issue
Fix potential memory out of range
Support CE-RED. 2G: ETSI v2.1.1 / 5G: ETSI v2.1.0
v5.1.5_19247.20160830
Update FW to v49
Update PHY parameters v57
Support TDLS
Enable GTK offload under WOW
Fix no scan results after resume
Fix NDPA issue under scan
Fix dynamic watchdog don't work
v4.3.20_16317.20160108
Disable CONFIG_WIFI_TEST & CONFIG_WOWLAN in Makefile default
v4.3.20_16317.20151231
Fix STBC issue
Fix NDPA sounding issue
Fix r/w rf register racing issue
Fix kernel panic for BT & timer
Fix memory leak for cmd thread
Fix ADDBA flow
Support Power limit
Support USB mode switch
Support Linux Kernel 4.2
Update FW to v41
Update PHY parameters to v55
v4.3.13_14061.20150505
Update FW
Update Phy parameters
Support WOWLAN GTK offload
Support Adaptivity
Support 1T2R
Support 8812AU-VN
Fix scan timeout issue
Fix RFE type error
Fix Spur Calibration flow
Fix some 802.11 logo issue
Fix some crash issues
v4.3.8_12175.20140912
Update PHY parameters to improve throughput
Update FW
Support PMF
Support WoWLAN
Modify channel plan
Fix MP issue
v4.3.2_11100.20140411
Fix p2p issues
Improve throughput
Update FW
v4.2.3_8123.20130705
Update PHY parameters to improve throughput
v4.2.2_7502.20130517
Support 11AC for STA
v4.2.0_7054.20130328
Fix LED behavior
v4.2.0_6952.20130315
First release

5
clean
View File

@ -1,5 +0,0 @@
#!/bin/bash
rmmod 8192cu
rmmod 8192ce
rmmod 8192du
rmmod 8192de

20
core/rtw_ap.c
View File

@ -3593,6 +3593,25 @@ void start_ap_mode(_adapter *padapter)
}
void rtw_ap_bcmc_sta_flush(_adapter *padapter)
{
#ifdef CONFIG_CONCURRENT_MODE
int cam_id = -1;
u8 *addr = adapter_mac_addr(padapter);
cam_id = rtw_iface_bcmc_id_get(padapter);
if (cam_id != INVALID_SEC_MAC_CAM_ID) {
RTW_PRINT("clear group key for "ADPT_FMT" addr:"MAC_FMT", camid:%d\n",
ADPT_ARG(padapter), MAC_ARG(addr), cam_id);
clear_cam_entry(padapter, cam_id);
rtw_camid_free(padapter, cam_id);
rtw_iface_bcmc_id_set(padapter, INVALID_SEC_MAC_CAM_ID); /*init default value*/
}
#else
invalidate_cam_all(padapter);
#endif
}
void stop_ap_mode(_adapter *padapter)
{
_irqL irqL;
@ -3625,6 +3644,7 @@ void stop_ap_mode(_adapter *padapter)
#endif
rtw_sta_flush(padapter, _TRUE);
rtw_ap_bcmc_sta_flush(padapter);
/* free_assoc_sta_resources */
rtw_free_all_stainfo(padapter);

61
core/rtw_cmd.c
View File

@ -1734,6 +1734,10 @@ u8 rtw_clearstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 enqueue)
s16 cam_id = 0;
u8 res = _SUCCESS;
if (!sta) {
RTW_ERR("%s sta == NULL\n", __func__);
goto exit;
}
if (!enqueue) {
while ((cam_id = rtw_camid_search(padapter, sta->hwaddr, -1, -1)) >= 0) {
@ -2007,6 +2011,53 @@ exit:
}
u8 rtw_set_securitypriv_cmd(_adapter *padapter, u8 *sme)
{
struct cmd_obj *cmdobj;
struct drvextra_cmd_parm *pdrvextra_cmd_parm;
struct cmd_priv *pcmdpriv = &padapter->cmdpriv;
struct submit_ctx sctx;
u8 res = _SUCCESS;
cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj));
if (cmdobj == NULL) {
res = _FAIL;
goto exit;
}
pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm));
if (pdrvextra_cmd_parm == NULL) {
rtw_mfree((unsigned char *)cmdobj, sizeof(struct cmd_obj));
res = _FAIL;
goto exit;
}
pdrvextra_cmd_parm->ec_id = SET_SECURITYPRIV;
pdrvextra_cmd_parm->type = 0;
pdrvextra_cmd_parm->size = 0;
pdrvextra_cmd_parm->pbuf = sme;
init_h2fwcmd_w_parm_no_rsp(cmdobj, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra));
cmdobj->sctx = &sctx;
rtw_sctx_init(&sctx, 2000);
/* rtw_enqueue_cmd(pcmdpriv, ph2c); */
res = rtw_enqueue_cmd(pcmdpriv, cmdobj);
if (res == _SUCCESS) {
rtw_sctx_wait(&sctx, __func__);
_enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
if (sctx.status == RTW_SCTX_SUBMITTED)
cmdobj->sctx = NULL;
_exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL);
}
exit:
return res;
}
u8 rtw_free_assoc_resources_cmd(_adapter *padapter)
{
struct cmd_obj *ph2c;
@ -3117,6 +3168,13 @@ void reset_securitypriv_hdl(_adapter *padapter)
rtw_reset_securitypriv(padapter);
}
void set_securitypriv_hdl(_adapter *padapter, u8 *buf)
{
#ifdef CONFIG_IOCTL_CFG80211
rtw_cfg80211_set_securitypriv(padapter, buf);
#endif
}
void free_assoc_resources_hdl(_adapter *padapter)
{
rtw_free_assoc_resources(padapter, 1);
@ -4577,6 +4635,9 @@ u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf)
case RESET_SECURITYPRIV:
reset_securitypriv_hdl(padapter);
break;
case SET_SECURITYPRIV:
set_securitypriv_hdl(padapter, pdrvextra_cmd->pbuf);
break;
case FREE_ASSOC_RESOURCES:
free_assoc_resources_hdl(padapter);
break;

18
core/rtw_mlme.c
View File

@ -1478,17 +1478,13 @@ void rtw_free_assoc_resources(_adapter *adapter, int lock_scanned_queue)
psta = rtw_get_stainfo(&adapter->stapriv, tgt_network->network.MacAddress);
#ifdef CONFIG_TDLS
if (ptdlsinfo->link_established == _TRUE) {
rtw_tdls_cmd(adapter, NULL, TDLS_RS_RCR);
rtw_reset_tdls_info(adapter);
rtw_free_all_stainfo(adapter);
/* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */
} else
rtw_free_all_tdls_sta(adapter, _TRUE);
rtw_tdls_cmd(adapter, NULL, TDLS_RS_RCR);
rtw_reset_tdls_info(adapter);
#endif /* CONFIG_TDLS */
{
/* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */
rtw_free_stainfo(adapter, psta);
}
/* _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */
rtw_free_stainfo(adapter, psta);
/* _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); */
@ -1648,7 +1644,7 @@ void rtw_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally_generate
/* set ips_deny_time to avoid enter IPS before LPS leave */
rtw_set_ips_deny(padapter, 3000);
_clr_fwstate_(pmlmepriv, _FW_LINKED);
_clr_fwstate_(pmlmepriv, _FW_LINKED | WIFI_UNDER_DISCONNTING);
rtw_led_control(padapter, LED_CTL_NO_LINK);

13
core/rtw_mlme_ext.c
View File

@ -11154,8 +11154,13 @@ unsigned int receive_disconnect(_adapter *padapter, unsigned char *MacAddr, unsi
if ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) {
if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) {
if (report_del_sta_event(padapter, MacAddr, reason, _TRUE, locally_generated) != _FAIL)
pmlmeinfo->state = WIFI_FW_NULL_STATE;
if (check_fwstate(&(padapter->mlmepriv), WIFI_UNDER_DISCONNTING) == _FALSE) {
set_fwstate(&(padapter->mlmepriv), WIFI_UNDER_DISCONNTING);
if (report_del_sta_event(padapter, MacAddr, reason, _TRUE, locally_generated) != _FAIL)
pmlmeinfo->state = WIFI_FW_NULL_STATE;
} else {
RTW_INFO(FUNC_ADPT_FMT" WIFI_UNDER_DISCONNTING exit\n", FUNC_ADPT_ARG(padapter));
}
} else if (pmlmeinfo->state & WIFI_FW_LINKING_STATE) {
if (report_join_res(padapter, -2) != _FAIL)
pmlmeinfo->state = WIFI_FW_NULL_STATE;
@ -15788,6 +15793,10 @@ u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf)
#endif
rtw_sta_media_status_rpt(padapter, ptdls_sta, 0);
free_tdls_sta(padapter, ptdls_sta);
if (ptdlsinfo->tdls_sctx != NULL)
rtw_sctx_done(&(ptdlsinfo->tdls_sctx));
break;
}

105
core/rtw_recv.c
View File

@ -804,6 +804,92 @@ sint recv_decache(union recv_frame *precv_frame, u8 bretry, struct stainfo_rxcac
}
#define PN_LESS_CHK(a, b) (((a-b) & 0x800000000000) != 0)
#define PN_EQUAL_CHK(a, b) (a == b)
sint recv_ucast_pn_decache(union recv_frame *precv_frame, struct stainfo_rxcache *prxcache);
sint recv_ucast_pn_decache(union recv_frame *precv_frame, struct stainfo_rxcache *prxcache)
{
_adapter *padapter = precv_frame->u.hdr.adapter;
struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
u8 *pdata = precv_frame->u.hdr.rx_data;
u32 data_len = precv_frame->u.hdr.len;
sint tid = precv_frame->u.hdr.attrib.priority;
u64 tmp_iv_hdr = 0;
u64 curr_pn = 0, pkt_pn = 0;
if (tid > 15)
return _FAIL;
if (pattrib->encrypt == _AES_) {
_rtw_memcpy(&tmp_iv_hdr, (pdata + pattrib->hdrlen), 8);
tmp_iv_hdr = le64_to_cpu(tmp_iv_hdr);
pkt_pn = (tmp_iv_hdr & 0x000000000000ffff) |
((tmp_iv_hdr & 0xffffffff00000000) >> 16);
_rtw_memcpy(&tmp_iv_hdr, prxcache->iv[tid], 8);
tmp_iv_hdr = le64_to_cpu(tmp_iv_hdr);
curr_pn = (tmp_iv_hdr & 0x000000000000ffff) |
((tmp_iv_hdr & 0xffffffff00000000) >> 16);
if (curr_pn == 0) {
_rtw_memcpy(prxcache->iv[tid], (pdata + pattrib->hdrlen), sizeof(prxcache->iv[tid]));
goto exit;
}
if (PN_LESS_CHK(pkt_pn, curr_pn) || PN_EQUAL_CHK(pkt_pn, curr_pn)) {
/* return _FAIL; */
} else
_rtw_memcpy(prxcache->iv[tid], (pdata + pattrib->hdrlen), sizeof(prxcache->iv[tid]));
}
exit:
return _SUCCESS;
}
sint recv_bcast_pn_decache(union recv_frame *precv_frame);
sint recv_bcast_pn_decache(union recv_frame *precv_frame)
{
_adapter *padapter = precv_frame->u.hdr.adapter;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct security_priv *psecuritypriv = &padapter->securitypriv;
struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
u8 *pdata = precv_frame->u.hdr.rx_data;
u32 data_len = precv_frame->u.hdr.len;
u64 tmp_iv_hdr = 0;
u64 curr_pn = 0, pkt_pn = 0;
u8 key_id;
if ((pattrib->encrypt == _AES_) &&
(check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)) {
_rtw_memcpy(&tmp_iv_hdr, (pdata + pattrib->hdrlen), 8);
tmp_iv_hdr = le64_to_cpu(tmp_iv_hdr);
key_id = ((tmp_iv_hdr & 0x00000000c0000000) >> 30);
pkt_pn = (tmp_iv_hdr & 0x000000000000ffff) |
((tmp_iv_hdr & 0xffffffff00000000) >> 16);
if (key_id >= 4 )
return _FAIL;
_rtw_memcpy(&tmp_iv_hdr, psecuritypriv->iv_seq[key_id], 8);
tmp_iv_hdr = le64_to_cpu(tmp_iv_hdr);
curr_pn = (tmp_iv_hdr & 0x0000ffffffffffff);
if ((curr_pn == 0) && (pkt_pn >= 0)) {
_rtw_memcpy(psecuritypriv->iv_seq[key_id], &pkt_pn, 8);
goto exit;
}
if (PN_LESS_CHK(pkt_pn, curr_pn) || PN_EQUAL_CHK(pkt_pn, curr_pn)) {
return _FAIL;
} else
_rtw_memcpy(psecuritypriv->iv_seq[key_id], &pkt_pn, 8);
}
exit:
return _SUCCESS;
}
void process_pwrbit_data(_adapter *padapter, union recv_frame *precv_frame);
void process_pwrbit_data(_adapter *padapter, union recv_frame *precv_frame)
{
@ -1861,6 +1947,25 @@ sint validate_recv_data_frame(_adapter *adapter, union recv_frame *precv_frame)
goto exit;
}
if (!IS_MCAST(pattrib->ra)) {
if (recv_ucast_pn_decache(precv_frame, &psta->sta_recvpriv.rxcache) == _FAIL) {
#ifdef DBG_RX_DROP_FRAME
RTW_INFO("DBG_RX_DROP_FRAME %s recv_decache return _FAIL\n", __func__);
#endif
ret = _FAIL;
goto exit;
}
} else {
if (recv_bcast_pn_decache(precv_frame) == _FAIL) {
#ifdef DBG_RX_DROP_FRAME
RTW_INFO("DBG_RX_DROP_FRAME "FUNC_ADPT_FMT" recv_bcast_pn_decache _FAIL for invalid PN!\n"
, FUNC_ADPT_ARG(adapter));
#endif
ret = _FAIL;
goto exit;
}
}
if (pattrib->privacy) {

4
core/rtw_sta_mgt.c
View File

@ -513,8 +513,10 @@ struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, u8 *hwaddr)
* In this case, this packet will be dropped by recv_decache function if we use the 0x00 as the default value for tid_rxseq variable.
* So, we initialize the tid_rxseq variable as the 0xffff. */
for (i = 0; i < 16; i++)
for (i = 0; i < 16; i++) {
_rtw_memcpy(&psta->sta_recvpriv.rxcache.tid_rxseq[i], &wRxSeqInitialValue, 2);
_rtw_memset(&psta->sta_recvpriv.rxcache.iv[i], 0, sizeof(psta->sta_recvpriv.rxcache.iv[i]));
}
rtw_init_timer(&psta->addba_retry_timer, psta->padapter, addba_timer_hdl, psta);
#ifdef CONFIG_IEEE80211W

61
core/rtw_tdls.c
View File

@ -62,6 +62,8 @@ void rtw_reset_tdls_info(_adapter *padapter)
#ifdef CONFIG_WFD
ptdlsinfo->wfd_info = &padapter->wfd_info;
#endif
ptdlsinfo->tdls_sctx = NULL;
}
int rtw_init_tdls_info(_adapter *padapter)
@ -94,6 +96,62 @@ void rtw_free_tdls_info(struct tdls_info *ptdlsinfo)
}
void rtw_free_all_tdls_sta(_adapter *padapter, u8 from_cmd_thread)
{
struct sta_priv *pstapriv = &padapter->stapriv;
struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
_irqL irqL;
_list *plist, *phead;
s32 index;
struct sta_info *psta = NULL;
u8 tdls_sta[NUM_STA][ETH_ALEN];
u8 empty_hwaddr[ETH_ALEN] = { 0x00 };
struct submit_ctx sctx;
_rtw_memset(tdls_sta, 0x00, sizeof(tdls_sta));
_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
for (index = 0; index < NUM_STA; index++) {
phead = &(pstapriv->sta_hash[index]);
plist = get_next(phead);
while (rtw_end_of_queue_search(phead, plist) == _FALSE) {
psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
plist = get_next(plist);
if (psta->tdls_sta_state != TDLS_STATE_NONE)
_rtw_memcpy(tdls_sta[index], psta->hwaddr, ETH_ALEN);
}
}
_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
for (index = 0; index < NUM_STA; index++) {
if (!_rtw_memcmp(tdls_sta[index], empty_hwaddr, ETH_ALEN)) {
RTW_INFO("issue tear down to "MAC_FMT" by from_cmd_thread = %d\n", MAC_ARG(tdls_sta[index]), from_cmd_thread);
if (from_cmd_thread == _TRUE) {
struct TDLSoption_param tdls_param;
_rtw_memcpy(&(tdls_param.addr), tdls_sta[index], ETH_ALEN);
tdls_param.option = TDLS_TEARDOWN_STA;
tdls_hdl(padapter, (unsigned char *)&(tdls_param));
tdls_param.option = TDLS_TEARDOWN_STA_LOCALLY;
tdls_hdl(padapter, (unsigned char *)&(tdls_param));
} else {
if (rtw_tdls_cmd(padapter, tdls_sta[index], TDLS_TEARDOWN_STA) == _SUCCESS) {
ptdlsinfo->tdls_sctx = &sctx;
rtw_sctx_init(ptdlsinfo->tdls_sctx, 1000);
rtw_sctx_wait(ptdlsinfo->tdls_sctx, __func__);
ptdlsinfo->tdls_sctx = NULL;
}
}
}
}
}
int check_ap_tdls_prohibited(u8 *pframe, u8 pkt_len)
{
u8 tdls_prohibited_bit = 0x40; /* bit(38); TDLS_prohibited */
@ -126,6 +184,9 @@ u8 rtw_tdls_is_setup_allowed(_adapter *padapter)
{
struct tdls_info *ptdlsinfo = &padapter->tdlsinfo;
if (is_client_associated_to_ap(padapter) == _FALSE)
return _FALSE;
if (ptdlsinfo->ap_prohibited == _TRUE)
return _FALSE;

4
core/rtw_wlan_util.c
View File

@ -4512,7 +4512,11 @@ int rtw_dev_nlo_info_set(struct pno_nlo_info *nlo_info, pno_ssid_t *ssid,
source = rtw_zmalloc(2048);
if (source != NULL) {
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0))
len = kernel_read(fp, source, len, &pos);
#else
len = vfs_read(fp, source, len, &pos);
#endif
rtw_parse_cipher_list(nlo_info, source);
rtw_mfree(source, 2048);
}

24
dkms-install.sh
View File

@ -1,24 +0,0 @@
#!/bin/bash
if [[ $EUID -ne 0 ]]; then
echo "You must run this with superuser priviliges. Try \"sudo ./dkms-install.sh\"" 2>&1
exit 1
else
echo "About to run dkms install steps..."
fi
DRV_DIR=rtl8812au
DRV_NAME=rtl8812au
DRV_VERSION=5.2.9
cp -r ../${DRV_DIR} /usr/src/${DRV_NAME}-${DRV_VERSION}
dkms add -m ${DRV_NAME} -v ${DRV_VERSION}
dkms build -m ${DRV_NAME} -v ${DRV_VERSION}
dkms install -m ${DRV_NAME} -v ${DRV_VERSION}
RESULT=$?
echo "Finished running dkms install steps."
exit $RESULT

25
dkms-remove.sh
View File

@ -1,25 +0,0 @@
#!/bin/bash
if [[ $EUID -ne 0 ]]; then
echo "You must run this with superuser priviliges. Try \"sudo ./dkms-remove.sh\"" 2>&1
exit 1
else
echo "About to run dkms removal steps..."
fi
DRV_DIR=rtl8812au
DRV_NAME=rtl8812au
DRV_VERSION=5.2.9
dkms remove ${DRV_NAME}/${DRV_VERSION} --all
rm -rf /usr/src/${DRV_NAME}-${DRV_VERSION}
RESULT=$?
if [[ "$RESULT" != "0" ]]; then
echo "Error occurred while running dkms remove." 2>&1
else
echo "Finished running dkms removal steps."
fi
exit $RESULT

11
dkms.conf
View File

@ -1,7 +1,10 @@
PACKAGE_NAME="rtl8812au"
PACKAGE_VERSION="#MODULE_VERSION#"
PACKAGE_NAME="@PKGBASE@"
PACKAGE_VERSION="@PKGVER@"
BUILT_MODULE_NAME[0]="8812au"
MAKE="'make' -j4"
PROCS_NUM=`nproc`
[ $PROCS_NUM -gt 16 ] && PROCS_NUM=16
MAKE="'make' -j$PROCS_NUM KVER=${kernelver} KSRC=/lib/modules/${kernelver}/build"
CLEAN="'make' clean"
DEST_MODULE_LOCATION[0]="/updates/dkms"
AUTOINSTALL="YES"
AUTOINSTALL="yes"
REMAKE_INITRD=no

32
hal/hal_com.c
View File

@ -3850,7 +3850,7 @@ static void rtw_hal_update_gtk_offload_info(_adapter *adapter)
struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl;
_irqL irqL;
u8 get_key[16];
u8 gtk_id = 0, offset = 0;
u8 gtk_id = 0, offset = 0, i = 0, sz = 0;
u64 replay_count = 0;
if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)
@ -3904,6 +3904,12 @@ static void rtw_hal_update_gtk_offload_info(_adapter *adapter)
&(paoac_rpt->group_key[offset]),
RTW_TKIP_MIC_LEN);
}
/* Update broadcast RX IV */
if (psecuritypriv->dot118021XGrpPrivacy == _AES_) {
sz = sizeof(psecuritypriv->iv_seq[0]);
for (i = 0 ; i < 4 ; i++)
_rtw_memset(psecuritypriv->iv_seq[i], 0, sz);
}
RTW_PRINT("GTK (%d) "KEY_FMT"\n", gtk_id,
KEY_ARG(psecuritypriv->dot118021XGrpKey[gtk_id].skey));
@ -10499,13 +10505,22 @@ void rtw_set_usb_agg_by_mode_normal(_adapter *padapter, u8 cur_wireless_mode)
pHalData->rxagg_usb_timeout = 0x10;
}
}
rtw_write16(padapter, REG_RXDMA_AGG_PG_TH,
pHalData->rxagg_usb_size | (pHalData->rxagg_usb_timeout << 8));
#else /* !CONFIG_PREALLOC_RX_SKB_BUFFER */
if (0x6 != pHalData->rxagg_usb_size || 0x10 != pHalData->rxagg_usb_timeout) {
pHalData->rxagg_usb_size = 0x6;
pHalData->rxagg_usb_timeout = 0x10;
#if defined(CONFIG_PLATFORM_HISILICON)
pHalData->rxagg_usb_size = 3;
pHalData->rxagg_usb_timeout = 8;
rtw_write16(padapter, REG_RXDMA_AGG_PG_TH,
pHalData->rxagg_usb_size | (pHalData->rxagg_usb_timeout << 8));
#else
if ((0x5 != pHalData->rxagg_usb_size) || (0x20 != pHalData->rxagg_usb_timeout)) {
pHalData->rxagg_usb_size = 0x5;
pHalData->rxagg_usb_timeout = 0x20;
rtw_write16(padapter, REG_RXDMA_AGG_PG_TH,
pHalData->rxagg_usb_size | (pHalData->rxagg_usb_timeout << 8));
}
#endif
#endif /* CONFIG_PREALLOC_RX_SKB_BUFFER */
} else if (cur_wireless_mode >= WIRELESS_11_24N
@ -10529,13 +10544,22 @@ void rtw_set_usb_agg_by_mode_normal(_adapter *padapter, u8 cur_wireless_mode)
pHalData->rxagg_usb_timeout = 0x10;
}
}
rtw_write16(padapter, REG_RXDMA_AGG_PG_TH,
pHalData->rxagg_usb_size | (pHalData->rxagg_usb_timeout << 8));
#else /* !CONFIG_PREALLOC_RX_SKB_BUFFER */
#if defined(CONFIG_PLATFORM_HISILICON)
pHalData->rxagg_usb_size = 3;
pHalData->rxagg_usb_timeout = 8;
rtw_write16(padapter, REG_RXDMA_AGG_PG_TH,
pHalData->rxagg_usb_size | (pHalData->rxagg_usb_timeout << 8));
#else
if ((0x5 != pHalData->rxagg_usb_size) || (0x20 != pHalData->rxagg_usb_timeout)) {
pHalData->rxagg_usb_size = 0x5;
pHalData->rxagg_usb_timeout = 0x20;
rtw_write16(padapter, REG_RXDMA_AGG_PG_TH,
pHalData->rxagg_usb_size | (pHalData->rxagg_usb_timeout << 8));
}
#endif
#endif /* CONFIG_PREALLOC_RX_SKB_BUFFER */
} else {

2
hal/hal_mp.c
View File

@ -988,7 +988,7 @@ void mpt_SetRFPath_8812A(PADAPTER pAdapter)
}
switch (ulAntennaRx) {
u32 reg0xC50 = 0;
u32 reg0xC50;
case ANTENNA_A:
phy_set_bb_reg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11);
phy_set_rf_reg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/

18
hal/led/hal_usb_led.c
View File

@ -1749,24 +1749,6 @@ void BlinkHandler(PLED_USB pLed)
return;
}
#ifdef CONFIG_SW_LED
/* led_enable 1 is normal blinking so don't cause always on/off */
if (padapter->registrypriv.led_ctrl != 1) {
if (padapter->registrypriv.led_ctrl == 0)
{
/* Cause LED to be always off */
pLed->BlinkingLedState = RTW_LED_OFF;
/* RTW_INFO("Led off\n"); */
} else {
/* Cause LED to be always on for led_ctrl 2 or greater */
pLed->BlinkingLedState = RTW_LED_ON;
/* RTW_INFO("Led on\n"); */
}
/* Skip various switch cases where SwLedBlink*() called below */
pLed->CurrLedState = LED_UNKNOWN;
}
#endif
switch (ledpriv->LedStrategy) {
case SW_LED_MODE0:
SwLedBlink(pLed);

112
hal/phydm/phydm.c
View File

@ -225,6 +225,11 @@ phydm_traffic_load_decision(
#endif
p_dm_odm->total_tp = p_dm_odm->tx_tp + p_dm_odm->rx_tp;
if (p_dm_odm->total_tp == 0)
p_dm_odm->consecutive_idlel_time += PHYDM_WATCH_DOG_PERIOD;
else
p_dm_odm->consecutive_idlel_time = 0;
/*
ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("cur_tx_ok_cnt = %d, cur_rx_ok_cnt = %d, last_tx_ok_cnt = %d, last_rx_ok_cnt = %d\n",
p_dm_odm->cur_tx_ok_cnt, p_dm_odm->cur_rx_ok_cnt, p_dm_odm->last_tx_ok_cnt, p_dm_odm->last_rx_ok_cnt));
@ -784,8 +789,8 @@ phydm_get_structure(
case PHYDM_ADAPTIVITY:
p_struct = &(p_dm_odm->adaptivity);
break;
break;
default:
break;
}
@ -804,6 +809,10 @@ phydm_get_structure(
p_struct = &(p_dm_odm->adaptivity);
break;
case PHYDM_DFS:
p_struct = &(p_dm_odm->dfs);
break;
default:
break;
}
@ -1585,6 +1594,63 @@ phydm_supportability_init_iot(
}
#endif
void
phydm_fwoffload_ability_init(
struct PHY_DM_STRUCT *p_dm_odm,
enum phydm_offload_ability offload_ability
)
{
switch (offload_ability) {
case PHYDM_PHY_PARAM_OFFLOAD:
if (p_dm_odm->support_ic_type & ODM_RTL8822B)
p_dm_odm->fw_offload_ability |= PHYDM_PHY_PARAM_OFFLOAD;
break;
case PHYDM_RF_IQK_OFFLOAD:
p_dm_odm->fw_offload_ability |= PHYDM_RF_IQK_OFFLOAD;
break;
default:
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("fwofflad, wrong init type!!\n"));
break;
}
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD,
("fw_offload_ability = %x\n", p_dm_odm->fw_offload_ability));
}
void
phydm_fwoffload_ability_clear(
struct PHY_DM_STRUCT *p_dm_odm,
enum phydm_offload_ability offload_ability
)
{
switch (offload_ability) {
case PHYDM_PHY_PARAM_OFFLOAD:
if (p_dm_odm->support_ic_type & ODM_RTL8822B)
p_dm_odm->fw_offload_ability &= (~PHYDM_PHY_PARAM_OFFLOAD);
break;
case PHYDM_RF_IQK_OFFLOAD:
p_dm_odm->fw_offload_ability &= (~PHYDM_RF_IQK_OFFLOAD);
break;
default:
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("fwofflad, wrong init type!!\n"));
break;
}
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD,
("fw_offload_ability = %x\n", p_dm_odm->fw_offload_ability));
}
void
phydm_supportability_init(
void *p_dm_void
@ -1847,6 +1913,7 @@ odm_dm_watchdog(
{
odm_common_info_self_update(p_dm_odm);
phydm_basic_dbg_message(p_dm_odm);
phydm_receiver_blocking(p_dm_odm);
odm_hw_setting(p_dm_odm);
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
@ -4099,3 +4166,44 @@ phydm_dc_cancellation(
}
#endif
}
void
phydm_receiver_blocking(
void *p_dm_void
)
{
#ifdef CONFIG_RECEIVER_BLOCKING
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
u32 channel = *p_dm_odm->p_channel;
u8 bw = *p_dm_odm->p_band_width;
u8 set_result = 0;
if (!(p_dm_odm->support_ic_type & ODM_RECEIVER_BLOCKING_SUPPORT))
return;
if (p_dm_odm->consecutive_idlel_time > 10 && *p_dm_odm->p_mp_mode == false && p_dm_odm->adaptivity_enable == true) {
if ((bw == ODM_BW20M) && (channel == 1)) {
set_result = phydm_nbi_setting(p_dm_odm, NBI_ENABLE, channel, 20, 2410, PHYDM_DONT_CARE);
p_dm_odm->is_receiver_blocking_en = true;
} else if ((bw == ODM_BW20M) && (channel == 13)) {
set_result = phydm_nbi_setting(p_dm_odm, NBI_ENABLE, channel, 20, 2473, PHYDM_DONT_CARE);
p_dm_odm->is_receiver_blocking_en = true;
} else if (*(p_dm_odm->p_is_scan_in_process) == false) {
if (p_dm_odm->is_receiver_blocking_en && channel != 1 && channel != 13) {
phydm_nbi_enable(p_dm_odm, NBI_DISABLE);
odm_set_bb_reg(p_dm_odm, 0xc40, 0x1f000000, 0x1f);
p_dm_odm->is_receiver_blocking_en = false;
}
}
} else {
if (p_dm_odm->is_receiver_blocking_en) {
phydm_nbi_enable(p_dm_odm, NBI_DISABLE);
odm_set_bb_reg(p_dm_odm, 0xc40, 0x1f000000, 0x1f);
p_dm_odm->is_receiver_blocking_en = false;
}
}
ODM_RT_TRACE(p_dm_odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD,
("[NBI set result: %s]\n", (set_result == SET_SUCCESS ? "Success" : (set_result == SET_NO_NEED ? "No need" : "Error"))));
#endif
}

36
hal/phydm/phydm.h
View File

@ -108,6 +108,8 @@ extern const u16 phy_rate_table[28];
#define FREQ_POSITIVE 1
#define FREQ_NEGATIVE 2
#define MAX_2(_x_, _y_) (((_x_)>(_y_))? (_x_) : (_y_))
#define MIN_2(_x_, _y_) (((_x_)<(_y_))? (_x_) : (_y_))
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#define PHYDM_WATCH_DOG_PERIOD 1
@ -567,7 +569,11 @@ enum odm_cca_path_e {
enum cca_pathdiv_en_e {
CCA_PATHDIV_DISABLE = 0,
CCA_PATHDIV_ENABLE = 1,
};
enum phydm_offload_ability {
PHYDM_PHY_PARAM_OFFLOAD = BIT(0),
PHYDM_RF_IQK_OFFLOAD = BIT(1),
};
@ -684,8 +690,9 @@ enum phy_reg_pg_type {
u32 soft_ap_special_setting;
u8 rfe_hwsetting_band;
u8 p_advance_ota;
u16 fw_offload_ability;
boolean hp_hw_id;
u8 is_receiver_blocking_en;
/*-----------HOOK BEFORE REG INIT-----------*/
/*Dynamic value*/
@ -816,6 +823,7 @@ enum phy_reg_pg_type {
u64 cur_rx_ok_cnt;
u64 last_tx_ok_cnt;
u64 last_rx_ok_cnt;
u16 consecutive_idlel_time; /*unit: second*/
u32 bb_swing_offset_a;
boolean is_bb_swing_offset_positive_a;
u32 bb_swing_offset_b;
@ -856,6 +864,7 @@ enum phy_reg_pg_type {
u8 default_rf_set_8821c;
u8 current_ant_num_8821c;
u8 default_ant_num_8821c;
u8 rfe_type_21c;
/*For Adaptivtiy*/
u16 nhm_cnt_0;
u16 nhm_cnt_1;
@ -893,6 +902,7 @@ enum phy_reg_pg_type {
boolean pre_b_noisy;
u32 noisy_decision_smooth;
boolean is_disable_dym_ecs;
boolean bhtstfdisabled; /* for dynamic HTSTF gain control */
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_WIN))
struct _ODM_NOISE_MONITOR_ noise_level;
@ -921,6 +931,7 @@ enum phy_reg_pg_type {
struct _odm_phy_dbg_info_ phy_dbg_info;
/*ODM Structure*/
struct _DFS_STATISTICS dfs;
#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
struct _BF_DIV_COEX_ dm_bdc_table;
@ -1077,6 +1088,7 @@ enum phydm_structure_type {
PHYDM_FALSEALMCNT,
PHYDM_CFOTRACK,
PHYDM_ADAPTIVITY,
PHYDM_DFS,
PHYDM_ROMINFO,
};
@ -1131,10 +1143,6 @@ enum rt_status {
};
#endif /*end of enum rt_status definition*/
#ifdef REMOVE_PACK
#pragma pack()
#endif
/*===========================================================*/
/*AGC RX High Power mode*/
/*===========================================================*/
@ -1234,6 +1242,19 @@ odm_dm_reset(
struct PHY_DM_STRUCT *p_dm_odm
);
void
phydm_fwoffload_ability_init(
struct PHY_DM_STRUCT *p_dm_odm,
enum phydm_offload_ability offload_ability
);
void
phydm_fwoffload_ability_clear(
struct PHY_DM_STRUCT *p_dm_odm,
enum phydm_offload_ability offload_ability
);
void
phydm_support_ability_debug(
void *p_dm_void,
@ -1470,4 +1491,9 @@ phydm_dc_cancellation(
struct PHY_DM_STRUCT *p_dm_odm
);
void
phydm_receiver_blocking(
void *p_dm_void
);
#endif

2
hal/phydm/phydm_adaptivity.c
View File

@ -788,7 +788,7 @@ phydm_adaptivity(
struct _ADAPTIVITY_STATISTICS *adaptivity = (struct _ADAPTIVITY_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_ADAPTIVITY);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
struct _ADAPTER *p_adapter = p_dm_odm->adapter;
boolean is_fw_current_in_ps_mode = false;
u32 is_fw_current_in_ps_mode = false;
u8 disable_ap_adapt_setting;
p_adapter->HalFunc.GetHwRegHandler(p_adapter, HW_VAR_FW_PSMODE_STATUS, (u8 *)(&is_fw_current_in_ps_mode));

52
hal/phydm/phydm_antdiv.c
View File

@ -140,11 +140,15 @@ odm_ant_div_on_off(
odm_set_bb_reg(p_dm_odm, 0xa00, BIT(15), swch);
#if (RTL8723D_SUPPORT == 1)
/*Mingzhi 2017-05-08*/
if (p_dm_odm->support_ic_type == ODM_RTL8723D) {
if (swch == ANTDIV_ON)
if (swch == ANTDIV_ON) {
odm_set_bb_reg(p_dm_odm, 0xce0, BIT(1), 1);
else
odm_set_bb_reg(p_dm_odm, 0x948, BIT(6), 1); /*1:HW ctrl 0:SW ctrl*/
} else {
odm_set_bb_reg(p_dm_odm, 0xce0, BIT(1), 0);
odm_set_bb_reg(p_dm_odm, 0x948, BIT(6), 0); /*1:HW ctrl 0:SW ctrl*/
}
}
#endif
@ -291,17 +295,16 @@ odm_update_rx_idle_ant(
ODM_RT_TRACE(p_dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to 0x948 = 0x280\n"));
}
#endif
#if (RTL8723D_SUPPORT == 1) /*Mingzhi 2017-05-08*/
else if (p_dm_odm->support_ic_type == ODM_RTL8723D) {
phydm_set_tx_ant_pwr_8723d(p_dm_odm, ant);
odm_update_rx_idle_ant_8723d(p_dm_odm, ant, default_ant, optional_ant);
}
#endif
else { /*8188E & 8188F*/
if (p_dm_odm->support_ic_type == ODM_RTL8723D) {
#if (RTL8723D_SUPPORT == 1)
phydm_set_tx_ant_pwr_8723d(p_dm_odm, ant);
#endif
}
#if (RTL8188F_SUPPORT == 1)
else if (p_dm_odm->support_ic_type == ODM_RTL8188F) {
if (p_dm_odm->support_ic_type == ODM_RTL8188F) {
phydm_update_rx_idle_antenna_8188F(p_dm_odm, default_ant);
/**/
}
#endif
@ -1158,6 +1161,32 @@ odm_trx_hw_ant_div_init_8723d(
}
/*Mingzhi 2017-05-08*/
void
odm_update_rx_idle_ant_8723d(
void *p_dm_void,
u8 ant,
u32 default_ant,
u32 optional_ant
)
{
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
struct _FAST_ANTENNA_TRAINNING_ *p_dm_fat_table = &p_dm_odm->dm_fat_table;
struct _ADAPTER *p_adapter = p_dm_odm->adapter;
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter);
u8 count = 0;
u8 u1_temp;
u8 h2c_parameter;
/* odm_set_bb_reg(p_dm_odm, 0x948, BIT(6), 0x1); */
odm_set_bb_reg(p_dm_odm, 0x948, BIT(7), default_ant);
odm_set_bb_reg(p_dm_odm, 0x864, BIT(5) | BIT(4) | BIT(3), default_ant); /*Default RX*/
odm_set_bb_reg(p_dm_odm, 0x864, BIT(8) | BIT(7) | BIT(6), optional_ant); /*Optional RX*/
odm_set_bb_reg(p_dm_odm, 0x860, BIT(14) | BIT(13) | BIT(12), default_ant); /*Default TX*/
p_dm_fat_table->rx_idle_ant = ant;
}
void
phydm_set_tx_ant_pwr_8723d(
void *p_dm_void,
@ -1486,7 +1515,6 @@ odm_trx_hw_ant_div_init_8821a(
odm_set_mac_reg(p_dm_odm, 0x64, BIT(29), 1); /* PAPE by WLAN control */
odm_set_mac_reg(p_dm_odm, 0x64, BIT(28), 1); /* LNAON by WLAN control */
odm_set_bb_reg(p_dm_odm, 0xCB0, MASKDWORD, 0x77775745);
odm_set_bb_reg(p_dm_odm, 0xCB8, BIT(16), 0);
odm_set_mac_reg(p_dm_odm, 0x4C, BIT(23), 0); /* select DPDT_P and DPDT_N as output pin */
@ -1538,7 +1566,6 @@ odm_s0s1_sw_ant_div_init_8821a(
odm_set_mac_reg(p_dm_odm, 0x64, BIT(29), 1); /* PAPE by WLAN control */
odm_set_mac_reg(p_dm_odm, 0x64, BIT(28), 1); /* LNAON by WLAN control */
odm_set_bb_reg(p_dm_odm, 0xCB0, MASKDWORD, 0x77775745);
odm_set_bb_reg(p_dm_odm, 0xCB8, BIT(16), 0);
odm_set_mac_reg(p_dm_odm, 0x4C, BIT(23), 0); /* select DPDT_P and DPDT_N as output pin */
@ -1736,7 +1763,6 @@ odm_trx_hw_ant_div_init_8821c(
odm_set_mac_reg(p_dm_odm, 0x64, BIT(29), 1); /* PAPE by WLAN control */
odm_set_mac_reg(p_dm_odm, 0x64, BIT(28), 1); /* LNAON by WLAN control */
odm_set_bb_reg(p_dm_odm, 0xCB0, MASKDWORD, 0x77775745);
odm_set_bb_reg(p_dm_odm, 0xCB8, BIT(16), 0);
odm_set_mac_reg(p_dm_odm, 0x4C, BIT(23), 0); /* select DPDT_P and DPDT_N as output pin */

8
hal/phydm/phydm_antdiv.h
View File

@ -472,6 +472,14 @@ phydm_set_tx_ant_pwr_8723d(
u8 ant
);
void
odm_update_rx_idle_ant_8723d(
void *p_dm_void,
u8 ant,
u32 default_ant,
u32 optional_ant
);
#endif
#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY

20
hal/phydm/phydm_beamforming.h
View File

@ -1,3 +1,18 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __INC_PHYDM_BEAMFORMING_H
#define __INC_PHYDM_BEAMFORMING_H
@ -181,8 +196,13 @@ struct _RT_BEAMFORMING_INFO {
struct _RT_BEAMFORMER_ENTRY beamformer_entry[BEAMFORMER_ENTRY_NUM];
struct _RT_BEAMFORM_STAINFO beamform_sta_info;
u8 beamformee_cur_idx;
#if defined (LINUX_VERSION_CODE) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
struct legacy_timer_emu beamforming_timer;
struct legacy_timer_emu mu_timer;
#else
struct timer_list beamforming_timer;
struct timer_list mu_timer;
#endif //defined (LINUX_VERSION_CODE) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
struct _RT_SOUNDING_INFO sounding_info;
struct _RT_BEAMFORMING_OID_INFO beamforming_oid_info;
struct _HAL_TXBF_INFO txbf_info;

32
hal/phydm/phydm_debug.c
View File

@ -1560,6 +1560,7 @@ void phydm_basic_profile(
PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "path Diversity", PATHDIV_VERSION));
PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "LA mode", DYNAMIC_LA_MODE));
PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Dynamic RX path", DYNAMIC_RX_PATH_VERSION));
PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "DFS", DFS_VERSION));
#if (RTL8822B_SUPPORT == 1)
if (p_dm_odm->support_ic_type & ODM_RTL8822B)
@ -2223,7 +2224,7 @@ enum PHYDM_CMD_ID {
PHYDM_SHOW_RXRATE,
PHYDM_NBI_EN,
PHYDM_CSI_MASK_EN,
PHYDM_DFS,
PHYDM_DFS_DEBUG,
PHYDM_IQK,
PHYDM_NHM,
PHYDM_CLM,
@ -2235,7 +2236,7 @@ enum PHYDM_CMD_ID {
PHYDM_DYNAMIC_RA_PATH,
PHYDM_PSD,
PHYDM_DEBUG_PORT,
PHYDM_HTSTF_CONTROL,
PHYDM_DIS_HTSTF_CONTROL,
PHYDM_TUNE_PARAMETER,
PHYDM_ADAPTIVITY_DEBUG
};
@ -2263,7 +2264,7 @@ struct _PHYDM_COMMAND phy_dm_ary[] = {
{"rxrate", PHYDM_SHOW_RXRATE},
{"nbi", PHYDM_NBI_EN},
{"csi_mask", PHYDM_CSI_MASK_EN},
{"dfs", PHYDM_DFS},
{"dfs", PHYDM_DFS_DEBUG},
{"iqk", PHYDM_IQK},
{"nhm", PHYDM_NHM},
{"clm", PHYDM_CLM},
@ -2275,7 +2276,7 @@ struct _PHYDM_COMMAND phy_dm_ary[] = {
{"drp", PHYDM_DYNAMIC_RA_PATH},
{"psd", PHYDM_PSD},
{"dbgport", PHYDM_DEBUG_PORT},
{"htstf", PHYDM_HTSTF_CONTROL},
{"dis_htstf", PHYDM_DIS_HTSTF_CONTROL},
{"tune_para", PHYDM_TUNE_PARAMETER},
{"adapt_debug", PHYDM_ADAPTIVITY_DEBUG}
};
@ -2702,12 +2703,12 @@ phydm_cmd_parser(
break;
case PHYDM_DFS:
#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
case PHYDM_DFS_DEBUG:
#ifdef CONFIG_PHYDM_DFS_MASTER
{
u32 var[6] = {0};
u32 var[4] = {0};
for (i = 0; i < 6; i++) {
for (i = 0; i < 4; i++) {
if (input[i + 1]) {
PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var[i]);
input_idx++;
@ -3021,19 +3022,22 @@ phydm_cmd_parser(
}
break;
case PHYDM_HTSTF_CONTROL:
case PHYDM_DIS_HTSTF_CONTROL:
{
if (input[1])
PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
if (var1[0] == 1) {
/* phydm_dynamic_switch_htstf_mumimo_8822b(p_dm_odm);*/
p_dm_odm->bhtstfenabled = TRUE;
PHYDM_SNPRINTF((output + used, out_len - used, "Dynamic HT-STF Gain Control is Enable\n"));
/* setting being false is for debug */
p_dm_odm->bhtstfdisabled = true;
PHYDM_SNPRINTF((output + used, out_len - used, "Dynamic HT-STF Gain Control is Disable\n"));
}
else {
p_dm_odm->bhtstfenabled = FALSE;
PHYDM_SNPRINTF((output + used, out_len - used, "Dynamic HT-STF Gain Control is Disable\n"));
/* default setting should be true, always be dynamic control*/
p_dm_odm->bhtstfdisabled = false;
PHYDM_SNPRINTF((output + used, out_len - used, "Dynamic HT-STF Gain Control is Enable\n"));
}
}
break;

10
hal/phydm/phydm_debug.h
View File

@ -156,6 +156,15 @@
#endif
#if DBG
#define PHYDM_DBG(p_dm, comp, fmt) \
do { \
if ((comp) & (p_dm->debug_components)) { \
\
dbg_print("[PHYDM] "); \
RT_PRINTK fmt; \
} \
} while (0)
#define ODM_RT_TRACE(p_dm_odm, comp, level, fmt) \
do { \
if (((comp) & p_dm_odm->debug_components) && (level <= p_dm_odm->debug_level || level == ODM_DBG_SERIOUS)) { \
@ -216,6 +225,7 @@
} while (0)
#else
#define PHYDM_DBG(p_dm, comp, fmt)
#define ODM_RT_TRACE(p_dm_odm, comp, level, fmt)
#define ODM_RT_TRACE_F(p_dm_odm, comp, level, fmt)
#define ODM_RT_ASSERT(p_dm_odm, expr, fmt)

462
hal/phydm/phydm_dfs.c
View File

@ -28,6 +28,18 @@
#include "phydm_precomp.h"
#if defined(CONFIG_PHYDM_DFS_MASTER)
boolean phydm_dfs_is_meteorology_channel(void *p_dm_void){
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
u8 c_channel = *(p_dm_odm->p_channel);
u8 band_width = *(p_dm_odm->p_band_width);
return ( (band_width == CHANNEL_WIDTH_80 && (c_channel) >= 116 && (c_channel) <= 128) ||
(band_width == CHANNEL_WIDTH_40 && (c_channel) >= 116 && (c_channel) <= 128) ||
(band_width == CHANNEL_WIDTH_20 && (c_channel) >= 120 && (c_channel) <= 128) );
}
void phydm_radar_detect_reset(void *p_dm_void)
{
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
@ -58,11 +70,13 @@ static void phydm_radar_detect_with_dbg_parm(void *p_dm_void)
void phydm_radar_detect_enable(void *p_dm_void)
{
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
struct _DFS_STATISTICS *p_dfs = (struct _DFS_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_DFS);
u8 region_domain = p_dm_odm->dfs_region_domain;
u8 c_channel = *(p_dm_odm->p_channel);
u8 band_width = *(p_dm_odm->p_band_width);
u8 enable = 0;
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("test, region_domain = %d\n", region_domain));
if (region_domain == PHYDM_DFS_DOMAIN_UNKNOWN) {
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("PHYDM_DFS_DOMAIN_UNKNOWN\n"));
goto exit;
@ -176,6 +190,16 @@ void phydm_radar_detect_enable(void *p_dm_void)
}
enable = 1;
p_dfs->st_l2h_cur = (u8)odm_get_bb_reg(p_dm_odm, 0x91c, 0x000000ff);
p_dfs->pwdb_th = (u8)odm_get_bb_reg(p_dm_odm, 0x918, 0x00001f00);
p_dfs->peak_th = (u8)odm_get_bb_reg(p_dm_odm, 0x918, 0x00030000);
p_dfs->short_pulse_cnt_th = (u8)odm_get_bb_reg(p_dm_odm, 0x920, 0x000f0000);
p_dfs->long_pulse_cnt_th = (u8)odm_get_bb_reg(p_dm_odm, 0x920, 0x00f00000);
p_dfs->peak_window = (u8)odm_get_bb_reg(p_dm_odm, 0x920, 0x00000300);
p_dfs->nb2wb_th = (u8)odm_get_bb_reg(p_dm_odm, 0x920, 0x0000e000);
phydm_dfs_parameter_init(p_dm_odm);
exit:
if (enable) {
@ -185,51 +209,399 @@ exit:
phydm_radar_detect_disable(p_dm_odm);
}
void phydm_dfs_parameter_init(void *p_dm_void)
{
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
struct _DFS_STATISTICS *p_dfs = (struct _DFS_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_DFS);
u8 i;
p_dfs->fa_mask_th = 30;
p_dfs->det_print = 1;
p_dfs->det_print2 = 0;
p_dfs->st_l2h_min = 0x20;
p_dfs->st_l2h_max = 0x4e;
p_dfs->pwdb_scalar_factor = 12;
p_dfs->pwdb_th = 8;
for(i=0; i<5;i++){
p_dfs->pulse_flag_hist[i] = 0;
p_dfs->radar_det_mask_hist[i] = 0;
p_dfs->fa_inc_hist[i] = 0;
}
}
void phydm_dfs_dynamic_setting(
void *p_dm_void
){
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
struct _DFS_STATISTICS *p_dfs = (struct _DFS_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_DFS);
u8 peak_th_cur=0, short_pulse_cnt_th_cur=0, long_pulse_cnt_th_cur=0, three_peak_opt_cur=0, three_peak_th2_cur=0;
u8 peak_window_cur=0, nb2wb_th_cur=0;
u8 region_domain = p_dm_odm->dfs_region_domain;
u8 c_channel = *(p_dm_odm->p_channel);
if (p_dm_odm->rx_tp <= 2) {
p_dfs->idle_mode = 1;
if(p_dfs->force_TP_mode)
p_dfs->idle_mode = 0;
}
else{
p_dfs->idle_mode = 0;
}
if ((p_dfs->idle_mode == 1)) { /*idle (no traffic)*/
peak_th_cur = 3;
short_pulse_cnt_th_cur = 6;
long_pulse_cnt_th_cur = 13;
peak_window_cur = 2;
nb2wb_th_cur = 6;
three_peak_opt_cur = 1;
three_peak_th2_cur = 2;
if(region_domain == PHYDM_DFS_DOMAIN_MKK){
if ((c_channel >= 52) && (c_channel <= 64)) {
short_pulse_cnt_th_cur = 14;
long_pulse_cnt_th_cur = 15;
nb2wb_th_cur = 3;
three_peak_th2_cur = 0;
}
else {
short_pulse_cnt_th_cur = 6;
nb2wb_th_cur = 3;
three_peak_th2_cur = 0;
long_pulse_cnt_th_cur = 10;
}
}
else if(region_domain == PHYDM_DFS_DOMAIN_FCC){
three_peak_th2_cur = 0;
}
else if(region_domain == PHYDM_DFS_DOMAIN_ETSI){
long_pulse_cnt_th_cur = 15;
if(phydm_dfs_is_meteorology_channel(p_dm_odm)){/*need to add check cac end condition*/
peak_th_cur = 2;
nb2wb_th_cur = 3;
three_peak_opt_cur = 1;
three_peak_th2_cur = 0;
short_pulse_cnt_th_cur = 7;
}
else{
three_peak_opt_cur = 1;
three_peak_th2_cur = 0;
short_pulse_cnt_th_cur = 7;
nb2wb_th_cur = 3;
}
}
else{ /*default: FCC*/
three_peak_th2_cur = 0;
}
}
else{ /*in service (with TP)*/
peak_th_cur = 2;
short_pulse_cnt_th_cur = 6;
long_pulse_cnt_th_cur = 9;
peak_window_cur = 2;
nb2wb_th_cur = 3;
three_peak_opt_cur = 1;
three_peak_th2_cur = 2;
if(region_domain == PHYDM_DFS_DOMAIN_MKK){
if ((c_channel >= 52) && (c_channel <= 64)) {
long_pulse_cnt_th_cur = 15;
short_pulse_cnt_th_cur = 5; /*for high duty cycle*/
three_peak_th2_cur = 0;
}
else {
three_peak_opt_cur = 0;
three_peak_th2_cur = 0;
long_pulse_cnt_th_cur = 8;
}
}
else if(region_domain == PHYDM_DFS_DOMAIN_FCC){
}
else if(region_domain == PHYDM_DFS_DOMAIN_ETSI){
long_pulse_cnt_th_cur = 15;
short_pulse_cnt_th_cur = 5;
three_peak_opt_cur = 0;
}
else{
}
}
}
boolean
phydm_radar_detect_dm_check(
void *p_dm_void
){
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
struct _DFS_STATISTICS *p_dfs = (struct _DFS_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_DFS);
u8 region_domain = p_dm_odm->dfs_region_domain, index=0;
u16 i=0, k=0, fa_count_cur=0, fa_count_inc=0, total_fa_in_hist=0, pre_post_now_acc_fa_in_hist=0, max_fa_in_hist=0, vht_crc_ok_cnt_cur=0;
u16 vht_crc_ok_cnt_inc=0, ht_crc_ok_cnt_cur=0, ht_crc_ok_cnt_inc=0, leg_crc_ok_cnt_cur=0, leg_crc_ok_cnt_inc=0;
u16 total_crc_ok_cnt_inc=0, short_pulse_cnt_cur=0, short_pulse_cnt_inc=0, long_pulse_cnt_cur=0, long_pulse_cnt_inc=0, total_pulse_count_inc=0;
u32 regf98_value=0, reg918_value=0, reg91c_value=0, reg920_value=0, reg924_value=0;
boolean tri_short_pulse=0, tri_long_pulse=0, radar_type=0, fault_flag_det=0, fault_flag_psd=0, fa_flag=0, radar_detected=0;
u8 st_l2h_new=0, fa_mask_th=0, sum=0;
u8 c_channel = *(p_dm_odm->p_channel);
/*Get FA count during past 100ms*/
fa_count_cur = (u16)odm_get_bb_reg(p_dm_odm, 0xf48, 0x0000ffff);
if (p_dfs->fa_count_pre == 0)
fa_count_inc = 0;
else if (fa_count_cur >= p_dfs->fa_count_pre)
fa_count_inc = fa_count_cur - p_dfs->fa_count_pre;
else
fa_count_inc = fa_count_cur;
p_dfs->fa_count_pre = fa_count_cur;
p_dfs->fa_inc_hist[p_dfs->mask_idx] = fa_count_inc;
for (i=0; i<5; i++) {
total_fa_in_hist = total_fa_in_hist + p_dfs->fa_inc_hist[i];
if (p_dfs->fa_inc_hist[i] > max_fa_in_hist)
max_fa_in_hist = p_dfs->fa_inc_hist[i];
}
if (p_dfs->mask_idx >= 2)
index = p_dfs->mask_idx - 2;
else
index = 5 + p_dfs->mask_idx - 2;
if (index == 0)
pre_post_now_acc_fa_in_hist = p_dfs->fa_inc_hist[index] + p_dfs->fa_inc_hist[index+1] + p_dfs->fa_inc_hist[4];
else if (index == 4)
pre_post_now_acc_fa_in_hist = p_dfs->fa_inc_hist[index] + p_dfs->fa_inc_hist[0] + p_dfs->fa_inc_hist[index-1];
else
pre_post_now_acc_fa_in_hist = p_dfs->fa_inc_hist[index] + p_dfs->fa_inc_hist[index+1] + p_dfs->fa_inc_hist[index-1];
/*Get VHT CRC32 ok count during past 100ms*/
vht_crc_ok_cnt_cur = (u16)odm_get_bb_reg(p_dm_odm, 0xf0c, 0x00003fff);
if (vht_crc_ok_cnt_cur >= p_dfs->vht_crc_ok_cnt_pre)
vht_crc_ok_cnt_inc = vht_crc_ok_cnt_cur - p_dfs->vht_crc_ok_cnt_pre;
else
vht_crc_ok_cnt_inc = vht_crc_ok_cnt_cur;
p_dfs->vht_crc_ok_cnt_pre = vht_crc_ok_cnt_cur;
/*Get HT CRC32 ok count during past 100ms*/
ht_crc_ok_cnt_cur = (u16)odm_get_bb_reg(p_dm_odm, 0xf10, 0x00003fff);
if (ht_crc_ok_cnt_cur >= p_dfs->ht_crc_ok_cnt_pre)
ht_crc_ok_cnt_inc = ht_crc_ok_cnt_cur - p_dfs->ht_crc_ok_cnt_pre;
else
ht_crc_ok_cnt_inc = ht_crc_ok_cnt_cur;
p_dfs->ht_crc_ok_cnt_pre = ht_crc_ok_cnt_cur;
/*Get Legacy CRC32 ok count during past 100ms*/
leg_crc_ok_cnt_cur = (u16)odm_get_bb_reg(p_dm_odm, 0xf14, 0x00003fff);
if (leg_crc_ok_cnt_cur >= p_dfs->leg_crc_ok_cnt_pre)
leg_crc_ok_cnt_inc = leg_crc_ok_cnt_cur - p_dfs->leg_crc_ok_cnt_pre;
else
leg_crc_ok_cnt_inc = leg_crc_ok_cnt_cur;
p_dfs->leg_crc_ok_cnt_pre = leg_crc_ok_cnt_cur;
if ((vht_crc_ok_cnt_cur == 0x3fff) ||
(ht_crc_ok_cnt_cur == 0x3fff) ||
(leg_crc_ok_cnt_cur == 0x3fff)) {
odm_set_bb_reg(p_dm_odm, 0xb58, BIT(0), 1);
odm_set_bb_reg(p_dm_odm, 0xb58, BIT(0), 0);
}
total_crc_ok_cnt_inc = vht_crc_ok_cnt_inc + ht_crc_ok_cnt_inc + leg_crc_ok_cnt_inc;
/*Get short pulse count, need carefully handle the counter overflow*/
regf98_value = odm_get_bb_reg(p_dm_odm, 0xf98, 0xffffffff);
short_pulse_cnt_cur = (u16)regf98_value & 0x000000ff;
if (short_pulse_cnt_cur >= p_dfs->short_pulse_cnt_pre)
short_pulse_cnt_inc = short_pulse_cnt_cur - p_dfs->short_pulse_cnt_pre;
else
short_pulse_cnt_inc = short_pulse_cnt_cur;
p_dfs->short_pulse_cnt_pre = short_pulse_cnt_cur;
/*Get long pulse count, need carefully handle the counter overflow*/
long_pulse_cnt_cur = (u16)((regf98_value & 0x0000ff00) >> 8);
if (long_pulse_cnt_cur >= p_dfs->long_pulse_cnt_pre)
long_pulse_cnt_inc = long_pulse_cnt_cur - p_dfs->long_pulse_cnt_pre;
else
long_pulse_cnt_inc = long_pulse_cnt_cur;
p_dfs->long_pulse_cnt_pre = long_pulse_cnt_cur;
total_pulse_count_inc = short_pulse_cnt_inc + long_pulse_cnt_inc;
if (p_dfs->det_print){
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("=====================================================================\n"));
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("Total_CRC_OK_cnt_inc[%d] VHT_CRC_ok_cnt_inc[%d] HT_CRC_ok_cnt_inc[%d] LEG_CRC_ok_cnt_inc[%d] FA_count_inc[%d]\n",
total_crc_ok_cnt_inc, vht_crc_ok_cnt_inc, ht_crc_ok_cnt_inc, leg_crc_ok_cnt_inc, fa_count_inc));
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("Init_Gain[%x] 0x91c[%x] 0xf98[%08x] short_pulse_cnt_inc[%d] long_pulse_cnt_inc[%d]\n",
p_dfs->igi_cur, p_dfs->st_l2h_cur, regf98_value, short_pulse_cnt_inc, long_pulse_cnt_inc));
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("Throughput: %dMbps\n", p_dm_odm->rx_tp));
reg918_value = odm_get_bb_reg(p_dm_odm, 0x918, 0xffffffff);
reg91c_value = odm_get_bb_reg(p_dm_odm, 0x91c, 0xffffffff);
reg920_value = odm_get_bb_reg(p_dm_odm, 0x920, 0xffffffff);
reg924_value = odm_get_bb_reg(p_dm_odm, 0x924, 0xffffffff);
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("0x918[%08x] 0x91c[%08x] 0x920[%08x] 0x924[%08x]\n", reg918_value, reg91c_value, reg920_value, reg924_value));
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("dfs_regdomain = %d, dbg_mode = %d, idle_mode = %d\n", region_domain, p_dfs->dbg_mode, p_dfs->idle_mode));
}
tri_short_pulse = (regf98_value & BIT(17))? 1 : 0;
tri_long_pulse = (regf98_value & BIT(19))? 1 : 0;
if(tri_short_pulse)
radar_type = 0;
else if(tri_long_pulse)
radar_type = 1;
if (tri_short_pulse) {
odm_set_bb_reg(p_dm_odm, 0x924, BIT(15), 0);
odm_set_bb_reg(p_dm_odm, 0x924, BIT(15), 1);
}
if (tri_long_pulse) {
odm_set_bb_reg(p_dm_odm, 0x924, BIT(15), 0);
odm_set_bb_reg(p_dm_odm, 0x924, BIT(15), 1);
if (region_domain == PHYDM_DFS_DOMAIN_MKK) {
if ((c_channel >= 52) && (c_channel <= 64)) {
tri_long_pulse = 0;
}
}
if (region_domain == PHYDM_DFS_DOMAIN_ETSI) {
tri_long_pulse = 0;
}
}
st_l2h_new = p_dfs->st_l2h_cur;
p_dfs->pulse_flag_hist[p_dfs->mask_idx] = tri_short_pulse | tri_long_pulse;
/* PSD(not ready) */
fault_flag_det = 0;
fault_flag_psd = 0;
fa_flag = 0;
if(region_domain == PHYDM_DFS_DOMAIN_ETSI){
fa_mask_th = p_dfs->fa_mask_th + 20;
}
else{
fa_mask_th = p_dfs->fa_mask_th;
}
if (max_fa_in_hist >= fa_mask_th || total_fa_in_hist >= fa_mask_th || pre_post_now_acc_fa_in_hist >= fa_mask_th || (p_dfs->igi_cur >= 0x30)){
st_l2h_new = p_dfs->st_l2h_max;
p_dfs->radar_det_mask_hist[index] = 1;
if (p_dfs->pulse_flag_hist[index] == 1){
p_dfs->pulse_flag_hist[index] = 0;
if (p_dfs->det_print2){
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("Radar is masked : FA mask\n"));
}
}
fa_flag = 1;
}
if (p_dfs->det_print) {
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("mask_idx: %d\n", p_dfs->mask_idx));
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("radar_det_mask_hist: "));
for (i=0; i<5; i++)
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("%d ", p_dfs->radar_det_mask_hist[i]));
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("pulse_flag_hist: "));
for (i=0; i<5; i++)
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("%d ", p_dfs->pulse_flag_hist[i]));
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("fa_inc_hist: "));
for (i=0; i<5; i++)
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("%d ", p_dfs->fa_inc_hist[i]));
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("\nmax_fa_in_hist: %d pre_post_now_acc_fa_in_hist: %d ",max_fa_in_hist,pre_post_now_acc_fa_in_hist));
}
sum = 0;
for (k=0; k<5; k++) {
if (p_dfs->radar_det_mask_hist[k] == 1)
sum++;
}
if (p_dfs->mask_hist_checked <= 5)
p_dfs->mask_hist_checked++;
if ((p_dfs->mask_hist_checked >= 5) && p_dfs->pulse_flag_hist[index])
{
if (sum <= 2)
{
radar_detected = 1 ;
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("Detected type %d radar signal!\n", radar_type));
}
else {
fault_flag_det = 1;
if (p_dfs->det_print2){
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("Radar is masked : mask_hist large than thd\n"));
}
}
}
p_dfs->mask_idx++;
if (p_dfs->mask_idx == 5)
p_dfs->mask_idx = 0;
if ((fault_flag_det == 0) && (fault_flag_psd == 0) && (fa_flag ==0)) {
if (p_dfs->igi_cur < 0x30) {
st_l2h_new = p_dfs->st_l2h_min;
}
}
if ((st_l2h_new != p_dfs->st_l2h_cur)) {
if (st_l2h_new < p_dfs->st_l2h_min) {
p_dfs->st_l2h_cur = p_dfs->st_l2h_min;
}
else if (st_l2h_new > p_dfs->st_l2h_max)
p_dfs->st_l2h_cur = p_dfs->st_l2h_max;
else
p_dfs->st_l2h_cur = st_l2h_new;
odm_set_bb_reg(p_dm_odm, 0x91c, 0xff, p_dfs->st_l2h_cur);
p_dfs->pwdb_th = ((int)p_dfs->st_l2h_cur - (int)p_dfs->igi_cur)/2 + p_dfs->pwdb_scalar_factor;
p_dfs->pwdb_th = MAX_2(p_dfs->pwdb_th, (int)p_dfs->pwdb_th); /*limit the pwdb value to absoulte lower bound 8*/
p_dfs->pwdb_th = MIN_2(p_dfs->pwdb_th, 0x1f); /*limit the pwdb value to absoulte upper bound 0x1f*/
odm_set_bb_reg(p_dm_odm, 0x918, 0x00001f00, p_dfs->pwdb_th);
}
if (p_dfs->det_print2) {
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("fault_flag_det[%d], fault_flag_psd[%d], DFS_detected [%d]\n",fault_flag_det, fault_flag_psd, radar_detected));
}
return radar_detected;
}
boolean phydm_radar_detect(void *p_dm_void)
{
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
struct _DFS_STATISTICS *p_dfs = (struct _DFS_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_DFS);
boolean enable_DFS = false;
boolean radar_detected = false;
u8 region_domain = p_dm_odm->dfs_region_domain;
p_dfs->igi_cur = (u8)odm_get_bb_reg(p_dm_odm, 0xc50, 0x0000007f);
if (region_domain == PHYDM_DFS_DOMAIN_UNKNOWN) {
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("PHYDM_DFS_DOMAIN_UNKNOWN\n"));
return false;
p_dfs->st_l2h_cur = (u8)odm_get_bb_reg(p_dm_odm, 0x91c, 0x000000ff);
/* dynamic pwdb calibration */
if (p_dfs->igi_pre != p_dfs->igi_cur) {
p_dfs->pwdb_th = ((int)p_dfs->st_l2h_cur - (int)p_dfs->igi_cur)/2 + p_dfs->pwdb_scalar_factor;
p_dfs->pwdb_th = MAX_2(p_dfs->pwdb_th_cur, (int)p_dfs->pwdb_th); /* limit the pwdb value to absoulte lower bound 0xa */
p_dfs->pwdb_th = MIN_2(p_dfs->pwdb_th_cur, 0x1f); /* limit the pwdb value to absoulte upper bound 0x1f */
odm_set_bb_reg(p_dm_odm, 0x918, 0x00001f00, p_dfs->pwdb_th);
}
p_dfs->igi_pre = p_dfs->igi_cur;
phydm_dfs_dynamic_setting(p_dm_odm);
radar_detected = phydm_radar_detect_dm_check(p_dm_odm);
if (odm_get_bb_reg(p_dm_odm, 0x924, BIT(15)))
enable_DFS = true;
if ((odm_get_bb_reg(p_dm_odm, 0xf98, BIT(17)))
|| (!(region_domain == PHYDM_DFS_DOMAIN_ETSI) && (odm_get_bb_reg(p_dm_odm, 0xf98, BIT(19)))))
radar_detected = true;
if (enable_DFS && radar_detected) {
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD
, ("Radar detect: enable_DFS:%d, radar_detected:%d\n"
, enable_DFS, radar_detected));
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("Radar detect: enable_DFS:%d, radar_detected:%d\n", enable_DFS, radar_detected));
phydm_radar_detect_reset(p_dm_odm);
}
if (p_dfs->dbg_mode == 1){
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DFS, ODM_DBG_LOUD, ("Radar is detected in DFS dbg mode.\n"));
radar_detected = 0;
}
}
exit:
return enable_DFS && radar_detected;
}
#endif /* defined(CONFIG_PHYDM_DFS_MASTER) */
boolean
phydm_dfs_master_enabled(
void *p_dm_void
)
{
#ifdef CONFIG_PHYDM_DFS_MASTER
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
return *p_dm_odm->dfs_master_enabled ? true : false;
#else
return false;
#endif
}
void
phydm_dfs_debug(
@ -240,14 +612,22 @@ phydm_dfs_debug(
u32 *_out_len
)
{
#if defined(CONFIG_PHYDM_DFS_MASTER)
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
struct _DFS_STATISTICS *p_dfs = (struct _DFS_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_DFS);
u32 used = *_used;
u32 out_len = *_out_len;
switch (argv[0]) {
p_dfs->dbg_mode = (boolean)argv[0];
p_dfs->force_TP_mode = (boolean)argv[1];
p_dfs->det_print = (boolean)argv[2];
p_dfs->det_print2 = (boolean)argv[3];
PHYDM_SNPRINTF((output + used, out_len - used, "dbg_mode: %d, force_TP_mode: %d, det_print: %d, det_print2: %d\n", p_dfs->dbg_mode, p_dfs->force_TP_mode, p_dfs->det_print, p_dfs->det_print2));
/*switch (argv[0]) {
case 1:
/* set dbg parameters for radar detection instead of the default value */
#if defined(CONFIG_PHYDM_DFS_MASTER)
set dbg parameters for radar detection instead of the default value
if (argv[1] == 1) {
p_dm_odm->radar_detect_reg_918 = argv[2];
p_dm_odm->radar_detect_reg_91c = argv[3];
@ -265,10 +645,26 @@ phydm_dfs_debug(
PHYDM_SNPRINTF((output + used, out_len - used, "Radar detection with default parameter\n"));
}
phydm_radar_detect_enable(p_dm_odm);
#endif defined(CONFIG_PHYDM_DFS_MASTER)
break;
default:
break;
}*/
}
#endif /* defined(CONFIG_PHYDM_DFS_MASTER) */
}
boolean
phydm_dfs_master_enabled(
void *p_dm_void
)
{
#ifdef CONFIG_PHYDM_DFS_MASTER
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
return *p_dm_odm->dfs_master_enabled ? true : false;
#else
return false;
#endif
}

49
hal/phydm/phydm_dfs.h
View File

@ -21,7 +21,7 @@
#ifndef __PHYDM_DFS_H__
#define __PHYDM_DFS_H__
#define DFS_VERSION "0.0"
#define DFS_VERSION "1.1"
/* ============================================================
Definition
@ -34,6 +34,40 @@
============================================================
*/
struct _DFS_STATISTICS {
u8 mask_idx;
u8 igi_cur;
u8 igi_pre;
u8 st_l2h_cur;
u16 fa_count_pre;
u16 fa_inc_hist[5];
u16 vht_crc_ok_cnt_pre;
u16 ht_crc_ok_cnt_pre;
u16 leg_crc_ok_cnt_pre;
u16 short_pulse_cnt_pre;
u16 long_pulse_cnt_pre;
u8 pwdb_th;
u8 pwdb_th_cur;
u8 pwdb_scalar_factor;
u8 peak_th;
u8 short_pulse_cnt_th;
u8 long_pulse_cnt_th;
u8 peak_window;
u8 nb2wb_th;
u8 fa_mask_th;
u8 det_flag_offset;
u8 st_l2h_max;
u8 st_l2h_min;
u8 mask_hist_checked;
boolean pulse_flag_hist[5];
boolean radar_det_mask_hist[5];
boolean idle_mode;
boolean force_TP_mode;
boolean dbg_mode;
boolean det_print;
boolean det_print2;
};
/* ============================================================
enumeration
============================================================
@ -56,20 +90,15 @@ enum phydm_dfs_region_domain {
void phydm_radar_detect_disable(void *p_dm_void);
void phydm_radar_detect_enable(void *p_dm_void);
boolean phydm_radar_detect(void *p_dm_void);
void phydm_dfs_parameter_init(void *p_dm_void);
void phydm_dfs_debug(void *p_dm_void, u32 *const argv, u32 *_used, char *output, u32 *_out_len);
#endif /* defined(CONFIG_PHYDM_DFS_MASTER) */
boolean phydm_dfs_is_meteorology_channel(void *p_dm_void);
boolean
phydm_dfs_master_enabled(
void *p_dm_void
);
void
phydm_dfs_debug(
void *p_dm_void,
u32 *const argv,
u32 *_used,
char *output,
u32 *_out_len
);
#endif /*#ifndef __PHYDM_DFS_H__ */

43
hal/phydm/phydm_dig.c
View File

@ -1172,11 +1172,15 @@ odm_DIG(
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
if (p_dm_odm->is_linked && !first_connect) {
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Beacon Num (%d)\n", p_dm_odm->phy_dbg_info.num_qry_beacon_pkt));
if ((p_dm_odm->phy_dbg_info.num_qry_beacon_pkt < 5) && (p_dm_odm->bsta_state)) {
p_dm_dig_table->rx_gain_range_min = 0x1c;
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: Abnrormal #beacon (%d) case in STA mode: Force lower bound to 0x%x\n",
p_dm_odm->phy_dbg_info.num_qry_beacon_pkt, p_dm_dig_table->rx_gain_range_min));
#if (RTL8723D_SUPPORT == 1)
if (p_dm_odm->support_ic_type != ODM_RTL8723D) {
if ((p_dm_odm->phy_dbg_info.num_qry_beacon_pkt < 5) && (p_dm_odm->bsta_state)) {
p_dm_dig_table->rx_gain_range_min = 0x1c;
ODM_RT_TRACE(p_dm_odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: Abnrormal #beacon (%d) case in STA mode: Force lower bound to 0x%x\n",
p_dm_odm->phy_dbg_info.num_qry_beacon_pkt, p_dm_dig_table->rx_gain_range_min));
}
}
#endif
}
#endif
@ -1611,15 +1615,17 @@ odm_false_alarm_counter_statistics(
}
}
#endif
if (p_dm_odm->support_ic_type != ODM_RTL8723D) {
if (phydm_set_bb_dbg_port(p_dm_odm, BB_DBGPORT_PRIORITY_1, 0x0)) {/*set debug port to 0x0*/
false_alm_cnt->dbg_port0 = phydm_get_bb_dbg_port_value(p_dm_odm);
phydm_release_bb_dbg_port(p_dm_odm);
}
if (phydm_set_bb_dbg_port(p_dm_odm, BB_DBGPORT_PRIORITY_1, 0x0)) {/*set debug port to 0x0*/
false_alm_cnt->dbg_port0 = phydm_get_bb_dbg_port_value(p_dm_odm);
phydm_release_bb_dbg_port(p_dm_odm);
}
if (phydm_set_bb_dbg_port(p_dm_odm, BB_DBGPORT_PRIORITY_1, adaptivity->adaptivity_dbg_port)) {
false_alm_cnt->edcca_flag = (boolean)((phydm_get_bb_dbg_port_value(p_dm_odm) & BIT(30))>>30);
phydm_release_bb_dbg_port(p_dm_odm);
if (phydm_set_bb_dbg_port(p_dm_odm, BB_DBGPORT_PRIORITY_1, adaptivity->adaptivity_dbg_port)) {
false_alm_cnt->edcca_flag = (boolean)((phydm_get_bb_dbg_port_value(p_dm_odm) & BIT(30))>>30);
phydm_release_bb_dbg_port(p_dm_odm);
}
}
false_alm_cnt->cnt_crc32_error_all = false_alm_cnt->cnt_vht_crc32_error + false_alm_cnt->cnt_ht_crc32_error + false_alm_cnt->cnt_ofdm_crc32_error + false_alm_cnt->cnt_cck_crc32_error;
@ -1940,6 +1946,15 @@ odm_write_cck_cca_thres(
if (p_dm_dig_table->cur_cck_cca_thres != cur_cck_cca_thres) { /* modify by Guo.Mingzhi 2012-01-03 */
odm_write_1byte(p_dm_odm, ODM_REG(CCK_CCA, p_dm_odm), cur_cck_cca_thres);
p_dm_dig_table->cck_fa_ma = 0xffffffff;
#if (RTL8723D_SUPPORT == 1)
if (p_dm_odm->support_ic_type & ODM_RTL8723D) { /* modify by David_Ding for 8723D no Beacon issue */
if (cur_cck_cca_thres == 0x40)
odm_write_1byte(p_dm_odm, 0xAAA, 0x0C);
else
odm_write_1byte(p_dm_odm, 0xAAA, 0x10);
}
#endif
}
p_dm_dig_table->pre_cck_cca_thres = p_dm_dig_table->cur_cck_cca_thres;
p_dm_dig_table->cur_cck_cca_thres = cur_cck_cca_thres;
@ -2061,7 +2076,7 @@ phydm_dynamic_ant_weighting(
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
struct _CCX_INFO *ccx_info = &p_dm_odm->dm_ccx_info;
struct _dynamic_initial_gain_threshold_ *p_dm_dig_table = &p_dm_odm->dm_dig_table;
// struct _FALSE_ALARM_STATISTICS *p_false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT);
/* struct _FALSE_ALARM_STATISTICS *p_false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT); */
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
prtl8192cd_priv priv = p_dm_odm->priv;
@ -2108,7 +2123,7 @@ phydm_dynamic_ant_weighting(
} else {
return;
}
#endif // #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
#endif /* #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) */
#endif
}

14
hal/phydm/phydm_features.h
View File

@ -21,7 +21,8 @@
#ifndef __PHYDM_FEATURES_H__
#define __PHYDM_FEATURES
#define ODM_DC_CANCELLATION_SUPPORT (ODM_RTL8188F | ODM_RTL8710B | ODM_RTL8821C)
#define ODM_RECEIVER_BLOCKING_SUPPORT (ODM_RTL8188E | ODM_RTL8192E)
#define ODM_DC_CANCELLATION_SUPPORT (ODM_RTL8188F | ODM_RTL8710B)
#if ((RTL8814A_SUPPORT == 1) || (RTL8821C_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) || (RTL8197F_SUPPORT == 1))
#define PHYDM_LA_MODE_SUPPORT 1
@ -38,7 +39,7 @@
#endif
#if (RTL8188F_SUPPORT == 1 || RTL8710B_SUPPORT == 1 || RTL8821C_SUPPORT == 1)
#if (RTL8188F_SUPPORT == 1 || RTL8710B_SUPPORT == 1)
#define PHYDM_DC_CANCELLATION 1
#else
#define PHYDM_DC_CANCELLATION 0
@ -72,6 +73,10 @@
#else
#define CONFIG_DYNAMIC_RX_PATH 0
#endif
#if (RTL8188E_SUPPORT == 1 || RTL8192E_SUPPORT == 1)
#define CONFIG_RECEIVER_BLOCKING
#endif
#define PHYDM_SUPPORT_CCKPD 1
#define RA_MASK_PHYDMLIZE_WIN 1
/*#define CONFIG_PATH_DIVERSITY*/
@ -82,6 +87,7 @@
/*#define CONFIG_PHYDM_RX_SNIFFER_PARSING*/
#define CONFIG_BB_POWER_SAVING
#define CONFIG_BB_TXBF_API
#define CONFIG_PHYDM_DFS_MASTER
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
@ -178,6 +184,10 @@
#define CONFIG_DYNAMIC_RX_PATH 0
#endif
#if (RTL8188E_SUPPORT == 1 || RTL8192E_SUPPORT == 1)
#define CONFIG_RECEIVER_BLOCKING
#endif
#define PHYDM_SUPPORT_CCKPD 1
#define RA_MASK_PHYDMLIZE_CE 1

112
hal/phydm/phydm_hwconfig.c
View File

@ -93,17 +93,20 @@ phydm_rx_statistic_cal(
if ((p_phy_sta_rpt->gid != 0) && (p_phy_sta_rpt->gid != 63) && (p_phydm->support_ic_type & ODM_IC_PHY_STATUE_NEW_TYPE)) {
p_phydm->phy_dbg_info.num_qry_mu_vht_pkt[date_rate - ODM_RATEVHTSS1MCS0]++;
p_phydm->phy_dbg_info.num_of_ppdu[p_pktinfo->ppdu_cnt] = date_rate | BIT(7);
p_phydm->phy_dbg_info.gid_num[p_pktinfo->ppdu_cnt] = p_phy_sta_rpt->gid;
if (p_pktinfo->ppdu_cnt < 4) {
p_phydm->phy_dbg_info.num_of_ppdu[p_pktinfo->ppdu_cnt] = date_rate | BIT(7);
p_phydm->phy_dbg_info.gid_num[p_pktinfo->ppdu_cnt] = p_phy_sta_rpt->gid;
}
} else
#endif
{
p_phydm->phy_dbg_info.num_qry_vht_pkt[date_rate - ODM_RATEVHTSS1MCS0]++;
p_phydm->phy_dbg_info.vht_pkt_not_zero = true;
#if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
p_phydm->phy_dbg_info.num_of_ppdu[p_pktinfo->ppdu_cnt] = date_rate;
p_phydm->phy_dbg_info.gid_num[p_pktinfo->ppdu_cnt] = p_phy_sta_rpt->gid;
if (p_pktinfo->ppdu_cnt < 4) {
p_phydm->phy_dbg_info.num_of_ppdu[p_pktinfo->ppdu_cnt] = date_rate;
p_phydm->phy_dbg_info.gid_num[p_pktinfo->ppdu_cnt] = p_phy_sta_rpt->gid;
}
#endif
}
}
@ -2145,11 +2148,12 @@ odm_config_rf_with_header_file(
struct _ADAPTER *adapter = p_dm_odm->adapter;
PMGNT_INFO p_mgnt_info = &(adapter->MgntInfo);
#endif
enum hal_status result = HAL_STATUS_SUCCESS;
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD,
("===>odm_config_rf_with_header_file (%s)\n", (p_dm_odm->is_mp_chip) ? "MPChip" : "TestChip"));
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD,
("p_dm_odm->support_platform: 0x%X, p_dm_odm->support_interface: 0x%X, p_dm_odm->board_type: 0x%X\n",
("support_platform: 0x%X, support_interface: 0x%X, board_type: 0x%X\n",
p_dm_odm->support_platform, p_dm_odm->support_interface, p_dm_odm->board_type));
/* 1 AP doesn't use PHYDM power tracking table in these ICs */
@ -2342,7 +2346,22 @@ odm_config_rf_with_header_file(
}
#endif
return HAL_STATUS_SUCCESS;
if (config_type == CONFIG_RF_RADIO) {
if (p_dm_odm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) {
result = phydm_set_reg_by_fw(p_dm_odm,
PHYDM_HALMAC_CMD_END,
0,
0,
0,
(enum odm_rf_radio_path_e)0,
0);
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD,
("rf param offload end!result = %d", result));
}
}
return result;
}
enum hal_status
@ -2547,6 +2566,7 @@ odm_config_bb_with_header_file(
struct _ADAPTER *adapter = p_dm_odm->adapter;
PMGNT_INFO p_mgnt_info = &(adapter->MgntInfo);
#endif
enum hal_status result = HAL_STATUS_SUCCESS;
/* 1 AP doesn't use PHYDM initialization in these ICs */
#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
@ -2578,13 +2598,13 @@ odm_config_bb_with_header_file(
} else if (config_type == CONFIG_BB_PHY_REG_MP)
READ_AND_CONFIG_MP(8812a, _phy_reg_mp);
else if (config_type == CONFIG_BB_AGC_TAB_DIFF) {
p_dm_odm->fw_offload_ability &= ~PHYDM_PHY_PARAM_OFFLOAD;
/*AGC_TAB DIFF dont support FW offload*/
if ((36 <= *p_dm_odm->p_channel) && (*p_dm_odm->p_channel <= 64))
AGC_DIFF_CONFIG_MP(8812a, lb);
else if (100 <= *p_dm_odm->p_channel)
AGC_DIFF_CONFIG_MP(8812a, hb);
}
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() phy:Rtl8812AGCTABArray\n"));
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() agc:Rtl8812PHY_REGArray\n"));
}
#endif
#if (RTL8821A_SUPPORT == 1)
@ -2606,7 +2626,7 @@ odm_config_bb_with_header_file(
/*{1827}{1022} for BUFFALO power by rate table. Isaiah 2013-10-18*/
if (p_mgnt_info->CustomerID == RT_CID_DNI_BUFFALO) {
/*{1024} for BUFFALO power by rate table. (JP/US)*/
if (p_mgnt_info->channel_plan == RT_CHANNEL_DOMAIN_US_2G_CANADA_5G)
if (p_mgnt_info->ChannelPlan == RT_CHANNEL_DOMAIN_US_2G_CANADA_5G)
READ_AND_CONFIG_MP(8821a, _phy_reg_pg_dni_us);
else
READ_AND_CONFIG_MP(8821a, _phy_reg_pg_dni_jp);
@ -2615,8 +2635,6 @@ odm_config_bb_with_header_file(
#endif
READ_AND_CONFIG_MP(8821a, _phy_reg_pg);
}
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() phy:Rtl8821AGCTABArray\n"));
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() agc:Rtl8821PHY_REGArray\n"));
}
#endif
#if (RTL8192E_SUPPORT == 1)
@ -2729,8 +2747,6 @@ odm_config_bb_with_header_file(
READ_AND_CONFIG_MP(8822b, _agc_tab);
else if (config_type == CONFIG_BB_PHY_REG_PG)
READ_AND_CONFIG_MP(8822b, _phy_reg_pg);
/*else if (config_type == CONFIG_BB_PHY_REG_MP)*/
/*READ_AND_CONFIG_MP(8822b, _phy_reg_mp);*/
}
#endif
@ -2742,10 +2758,6 @@ odm_config_bb_with_header_file(
phydm_phypara_a_cut(p_dm_odm);
} else if (config_type == CONFIG_BB_AGC_TAB)
READ_AND_CONFIG_MP(8197f, _agc_tab);
/* else if(config_type == CONFIG_BB_PHY_REG_PG)
READ_AND_CONFIG_MP(8197f, _phy_reg_pg);
else if(config_type == CONFIG_BB_PHY_REG_MP)
READ_AND_CONFIG_MP(8197f, _phy_reg_mp); */
}
#endif
@ -2761,6 +2773,8 @@ odm_config_bb_with_header_file(
} else if (config_type == CONFIG_BB_PHY_REG_PG)
READ_AND_CONFIG(8821c, _phy_reg_pg);
else if (config_type == CONFIG_BB_AGC_TAB_DIFF) {
p_dm_odm->fw_offload_ability &= ~PHYDM_PHY_PARAM_OFFLOAD;
/*AGC_TAB DIFF dont support FW offload*/
if (p_dm_odm->current_rf_set_8821c == SWITCH_TO_BTG)
AGC_DIFF_CONFIG_MP(8821c, btg);
else if (p_dm_odm->current_rf_set_8821c == SWITCH_TO_WLG)
@ -2780,7 +2794,21 @@ odm_config_bb_with_header_file(
}
#endif
return HAL_STATUS_SUCCESS;
if (config_type == CONFIG_BB_PHY_REG || config_type == CONFIG_BB_AGC_TAB)
if (p_dm_odm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) {
result = phydm_set_reg_by_fw(p_dm_odm,
PHYDM_HALMAC_CMD_END,
0,
0,
0,
(enum odm_rf_radio_path_e)0,
0);
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD,
("phy param offload end!result = %d", result));
}
return result;
}
enum hal_status
@ -2788,14 +2816,11 @@ odm_config_mac_with_header_file(
struct PHY_DM_STRUCT *p_dm_odm
)
{
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
struct _ADAPTER *adapter = p_dm_odm->adapter;
#endif
enum hal_status result = HAL_STATUS_SUCCESS;
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD,
("===>odm_config_mac_with_header_file (%s)\n", (p_dm_odm->is_mp_chip) ? "MPChip" : "TestChip"));
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD,
("p_dm_odm->support_platform: 0x%X, p_dm_odm->support_interface: 0x%X, p_dm_odm->board_type: 0x%X\n",
("support_platform: 0x%X, support_interface: 0x%X, board_type: 0x%X\n",
p_dm_odm->support_platform, p_dm_odm->support_interface, p_dm_odm->board_type));
/* 1 AP doesn't use PHYDM initialization in these ICs */
@ -2805,11 +2830,8 @@ odm_config_mac_with_header_file(
READ_AND_CONFIG_MP(8812a, _mac_reg);
#endif
#if (RTL8821A_SUPPORT == 1)
if (p_dm_odm->support_ic_type == ODM_RTL8821) {
if (p_dm_odm->support_ic_type == ODM_RTL8821)
READ_AND_CONFIG_MP(8821a, _mac_reg);
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("<===8821_ODM_ConfigMACwithHeaderFile\n"));
}
#endif
#if (RTL8192E_SUPPORT == 1)
if (p_dm_odm->support_ic_type == ODM_RTL8192E)
@ -2868,7 +2890,20 @@ odm_config_mac_with_header_file(
READ_AND_CONFIG_MP(8195a, _mac_reg);
#endif
return HAL_STATUS_SUCCESS;
if (p_dm_odm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) {
result = phydm_set_reg_by_fw(p_dm_odm,
PHYDM_HALMAC_CMD_END,
0,
0,
0,
(enum odm_rf_radio_path_e)0,
0);
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD,
("mac param offload end!result = %d", result));
}
return result;
}
enum hal_status
@ -2991,20 +3026,6 @@ odm_config_fw_with_header_file(
}
#endif
/*#if (RTL8814A_SUPPORT == 1)
if (p_dm_odm->support_ic_type == ODM_RTL8814A)
{
if (config_type == CONFIG_FW_NIC)
READ_FIRMWARE_MP(8814a, _fw_nic);
else if (config_type == config_fw_wowlan)
READ_FIRMWARE_MP(8814a, _fw_wowlan);
#ifdef CONFIG_AP_WOWLAN
else if (config_type == config_fw_ap_wowlan)
READ_FIRMWARE_MP(8814a, _fw_ap);
#endif
}
#endif */
#if (RTL8814A_SUPPORT == 1)
if (p_dm_odm->support_ic_type == ODM_RTL8814A) {
if (config_type == CONFIG_FW_NIC)
@ -3334,9 +3355,10 @@ phydm_get_rx_phy_status_type0(
rx_power = p_phy_sta_rpt->pwdb - 97;
#endif
}
/* RTL8710B do not need recalculate the offset By James Liao@20170527 */
#if (RTL8710B_SUPPORT == 1)
else if (p_dm_odm->support_ic_type & ODM_RTL8710B)
rx_power = p_phy_sta_rpt->pwdb - 97;
//else if (p_dm_odm->support_ic_type & ODM_RTL8710B)
//rx_power = p_phy_sta_rpt->pwdb - 97;
#endif
#if (RTL8821C_SUPPORT == 1)

55
hal/phydm/phydm_interface.c
View File

@ -268,7 +268,7 @@ odm_get_bb_reg(
void
odm_set_rf_reg(
struct PHY_DM_STRUCT *p_dm_odm,
enum odm_rf_radio_path_e e_rf_path,
u1Byte e_rf_path,
u32 reg_addr,
u32 bit_mask,
u32 data
@ -293,7 +293,7 @@ odm_set_rf_reg(
u32
odm_get_rf_reg(
struct PHY_DM_STRUCT *p_dm_odm,
enum odm_rf_radio_path_e e_rf_path,
u1Byte e_rf_path,
u32 reg_addr,
u32 bit_mask
)
@ -312,7 +312,38 @@ odm_get_rf_reg(
#endif
}
enum hal_status
phydm_set_reg_by_fw(
struct PHY_DM_STRUCT *p_dm_odm,
enum phydm_halmac_param config_type,
u32 offset,
u32 data,
u32 mask,
enum odm_rf_radio_path_e e_rf_path,
u32 delay_time
)
{
enum hal_status stat = HAL_STATUS_SUCCESS;
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
stat = HAL_MAC_Config_PHY_WriteNByte(p_dm_odm,
config_type,
offset,
data,
mask,
e_rf_path,
delay_time);
#elif (0)/*(DM_ODM_SUPPORT_TYPE & ODM_CE)*/
return rtw_phydm_cfg_phy_para(p_dm_odm,
config_type,
offset,
data,
mask,
e_rf_path,
delay_time);
#endif
return stat;
}
/*
@ -627,7 +658,11 @@ ODM_sleep_us(u32 us)
void
odm_set_timer(
struct PHY_DM_STRUCT *p_dm_odm,
#if defined (LINUX_VERSION_CODE) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
struct legacy_timer_emu *p_timer,
#else
struct timer_list *p_timer,
#endif //defined (LINUX_VERSION_CODE) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
u32 ms_delay
)
{
@ -647,7 +682,11 @@ odm_set_timer(
void
odm_initialize_timer(
struct PHY_DM_STRUCT *p_dm_odm,
#if defined (LINUX_VERSION_CODE) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
struct legacy_timer_emu *p_timer,
#else
struct timer_list *p_timer,
#endif //defined (LINUX_VERSION_CODE) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
void *call_back_func,
void *p_context,
const char *sz_id
@ -668,7 +707,7 @@ odm_initialize_timer(
_init_timer(p_timer, adapter->pnetdev, call_back_func, p_dm_odm);
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
struct _ADAPTER *adapter = p_dm_odm->adapter;
PlatformInitializeTimer(adapter, p_timer, call_back_func, p_context, sz_id);
PlatformInitializeTimer(adapter, p_timer, (RT_TIMER_CALL_BACK)call_back_func, p_context, sz_id);
#endif
}
@ -676,7 +715,11 @@ odm_initialize_timer(
void
odm_cancel_timer(
struct PHY_DM_STRUCT *p_dm_odm,
#if defined (LINUX_VERSION_CODE) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
struct legacy_timer_emu *p_timer
#else
struct timer_list *p_timer
#endif //defined (LINUX_VERSION_CODE) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
)
{
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
@ -695,7 +738,11 @@ odm_cancel_timer(
void
odm_release_timer(
struct PHY_DM_STRUCT *p_dm_odm,
#if defined (LINUX_VERSION_CODE) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
struct legacy_timer_emu *p_timer
#else
struct timer_list *p_timer
#endif //defined (LINUX_VERSION_CODE) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
)
{
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
@ -1131,7 +1178,7 @@ odm_get_tx_power_index (
{
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
struct _ADAPTER *adapter = p_dm_odm->adapter;
return PHY_GetTxPowerIndex(p_dm_odm->adapter, RFPath, tx_rate, band_width, Channel);
return PHY_GetTxPowerIndex(p_dm_odm->adapter, RFPath, tx_rate, (CHANNEL_WIDTH)band_width, Channel);
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) && defined(DM_ODM_CE_MAC80211)
void *adapter = p_dm_odm->adapter;
return phy_get_tx_power_index(adapter, (enum odm_rf_radio_path_e)RFPath, tx_rate, band_width, Channel);

51
hal/phydm/phydm_interface.h
View File

@ -126,6 +126,18 @@ enum phydm_extend_c2h_evt {
};
enum phydm_halmac_param {
PHYDM_HALMAC_CMD_MAC_W8 = 0,
PHYDM_HALMAC_CMD_MAC_W16 = 1,
PHYDM_HALMAC_CMD_MAC_W32 = 2,
PHYDM_HALMAC_CMD_BB_W8,
PHYDM_HALMAC_CMD_BB_W16,
PHYDM_HALMAC_CMD_BB_W32,
PHYDM_HALMAC_CMD_RF_W,
PHYDM_HALMAC_CMD_DELAY_US,
PHYDM_HALMAC_CMD_DELAY_MS,
PHYDM_HALMAC_CMD_END = 0XFF,
};
/*
* =========== Extern Variable ??? It should be forbidden.
@ -209,7 +221,7 @@ odm_get_bb_reg(
void
odm_set_rf_reg(
struct PHY_DM_STRUCT *p_dm_odm,
enum odm_rf_radio_path_e e_rf_path,
u1Byte e_rf_path,
u32 reg_addr,
u32 bit_mask,
u32 data
@ -218,12 +230,23 @@ odm_set_rf_reg(
u32
odm_get_rf_reg(
struct PHY_DM_STRUCT *p_dm_odm,
enum odm_rf_radio_path_e e_rf_path,
u1Byte e_rf_path,
u32 reg_addr,
u32 bit_mask
);
enum hal_status
phydm_set_reg_by_fw(
struct PHY_DM_STRUCT *p_dm_odm,
enum phydm_halmac_param config_type,
u32 offset,
u32 data,
u32 mask,
enum odm_rf_radio_path_e e_rf_path,
u32 delay_time
);
/*
* Memory Relative Function.
* */
@ -339,15 +362,23 @@ ODM_sleep_us(u32 us);
void
odm_set_timer(
struct PHY_DM_STRUCT *p_dm_odm,
struct PHY_DM_STRUCT *p_dm,
#if defined (LINUX_VERSION_CODE) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
struct legacy_timer_emu *p_timer,
#else
struct timer_list *p_timer,
#endif //defined (LINUX_VERSION_CODE) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
u32 ms_delay
);
void
odm_initialize_timer(
struct PHY_DM_STRUCT *p_dm_odm,
struct PHY_DM_STRUCT *p_dm,
#if defined (LINUX_VERSION_CODE) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
struct legacy_timer_emu *p_timer,
#else
struct timer_list *p_timer,
#endif //defined (LINUX_VERSION_CODE) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
void *call_back_func,
void *p_context,
const char *sz_id
@ -355,14 +386,22 @@ odm_initialize_timer(
void
odm_cancel_timer(
struct PHY_DM_STRUCT *p_dm_odm,
struct PHY_DM_STRUCT *p_dm,
#if defined (LINUX_VERSION_CODE) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
struct legacy_timer_emu *p_timer
#else
struct timer_list *p_timer
#endif //defined (LINUX_VERSION_CODE) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
);
void
odm_release_timer(
struct PHY_DM_STRUCT *p_dm_odm,
struct PHY_DM_STRUCT *p_dm,
#if defined (LINUX_VERSION_CODE) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
struct legacy_timer_emu *p_timer
#else
struct timer_list *p_timer
#endif //defined (LINUX_VERSION_CODE) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
);
/*

2
hal/phydm/phydm_kfree.c
View File

@ -200,7 +200,6 @@ phydm_set_kfree_to_rf_8821c(
{
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info);
boolean is_odd;
u8 wlg, btg;
odm_set_rf_reg(p_dm_odm, e_rf_path, 0xde, BIT(0), 1);
@ -458,7 +457,6 @@ phydm_set_kfree_to_rf_8822b(
)
{
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info);
odm_set_rf_reg(p_dm_odm, e_rf_path, 0xde, BIT(0), 1);
odm_set_rf_reg(p_dm_odm, e_rf_path, 0xde, BIT(4), 1);

4
hal/phydm/phydm_noisemonitor.c
View File

@ -147,14 +147,14 @@ s16 odm_inband_noise_monitor_n_series(struct PHY_DM_STRUCT *p_dm_odm, u8 is_paus
reg_c50 = (u8)odm_get_bb_reg(p_dm_odm, REG_OFDM_0_XA_AGC_CORE1, MASKBYTE0);
reg_c50 &= ~BIT(7);
ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("0x%x = 0x%02x(%d)\n", REG_OFDM_0_XA_AGC_CORE1, reg_c50, reg_c50));
p_dm_odm->noise_level.noise[ODM_RF_PATH_A] = (u8)(-110 + reg_c50 + noise_data.sum[ODM_RF_PATH_A]);
p_dm_odm->noise_level.noise[ODM_RF_PATH_A] = (s8)(-110 + reg_c50 + noise_data.sum[ODM_RF_PATH_A]);
p_dm_odm->noise_level.noise_all += p_dm_odm->noise_level.noise[ODM_RF_PATH_A];
if (max_rf_path == 2) {
reg_c58 = (u8)odm_get_bb_reg(p_dm_odm, REG_OFDM_0_XB_AGC_CORE1, MASKBYTE0);
reg_c58 &= ~BIT(7);
ODM_RT_TRACE(p_dm_odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("0x%x = 0x%02x(%d)\n", REG_OFDM_0_XB_AGC_CORE1, reg_c58, reg_c58));
p_dm_odm->noise_level.noise[ODM_RF_PATH_B] = (u8)(-110 + reg_c58 + noise_data.sum[ODM_RF_PATH_B]);
p_dm_odm->noise_level.noise[ODM_RF_PATH_B] = (s8)(-110 + reg_c58 + noise_data.sum[ODM_RF_PATH_B]);
p_dm_odm->noise_level.noise_all += p_dm_odm->noise_level.noise[ODM_RF_PATH_B];
}
p_dm_odm->noise_level.noise_all /= max_rf_path;

36
hal/phydm/phydm_powertracking_ce.c
View File

@ -540,7 +540,7 @@ get_swing_index(
u32 *p_swing_table;
if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8723B
|| p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8188F || p_dm_odm->support_ic_type == ODM_RTL8703B
|| p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8188F || p_dm_odm->support_ic_type == ODM_RTL8703B || p_dm_odm->support_ic_type == ODM_RTL8723D || p_dm_odm->support_ic_type == ODM_RTL8710B
) {
bb_swing = odm_get_bb_reg(p_dm_odm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 0xFFC00000);
@ -572,6 +572,37 @@ get_swing_index(
return i;
}
u8
get_cck_swing_index(
void *p_dm_void
)
{
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
u8 i = 0;
u32 bb_cck_swing;
if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8723B ||
p_dm_odm->support_ic_type == ODM_RTL8192E) {
bb_cck_swing = odm_read_1byte(p_dm_odm, 0xa22);
for (i = 0; i < CCK_TABLE_SIZE; i++) {
if (bb_cck_swing == cck_swing_table_ch1_ch13_new[i][0])
break;
}
} else if (p_dm_odm->support_ic_type == ODM_RTL8703B) {
bb_cck_swing = odm_read_1byte(p_dm_odm, 0xa22);
for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
if (bb_cck_swing == cck_swing_table_ch1_ch14_88f[i][0])
break;
}
}
return i;
}
void
odm_txpowertracking_thermal_meter_init(
void *p_dm_void
@ -579,6 +610,7 @@ odm_txpowertracking_thermal_meter_init(
{
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
u8 default_swing_index = get_swing_index(p_dm_odm);
u8 default_cck_swing_index = get_cck_swing_index(p_dm_odm);
u8 p = 0;
struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
@ -637,7 +669,7 @@ odm_txpowertracking_thermal_meter_init(
if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8723B ||
p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8703B) {
p_rf_calibrate_info->default_ofdm_index = (default_swing_index >= OFDM_TABLE_SIZE) ? 30 : default_swing_index;
p_rf_calibrate_info->default_cck_index = 20;
p_rf_calibrate_info->default_cck_index = (default_cck_swing_index >= CCK_TABLE_SIZE) ? 20 : default_cck_swing_index;
} else if (p_dm_odm->support_ic_type == ODM_RTL8188F) { /*add by Mingzhi.Guo 2015-03-23*/
p_rf_calibrate_info->default_ofdm_index = 28; /*OFDM: -1dB*/
p_rf_calibrate_info->default_cck_index = 20; /*CCK:-6dB*/

38
hal/phydm/phydm_powertracking_win.c
View File

@ -264,8 +264,6 @@ u8 cck_swing_table_ch14_88f[CCK_TABLE_SIZE_88F][16] = {
};
u8 cck_swing_table_ch1_ch13_new[CCK_TABLE_SIZE][8] = {
{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, /* 0, -16.0dB */
{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 1, -15.5dB */
@ -540,7 +538,7 @@ get_swing_index(
u32 *p_swing_table;
if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8723B ||
p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8188F || p_dm_odm->support_ic_type == ODM_RTL8703B) {
p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8188F || p_dm_odm->support_ic_type == ODM_RTL8703B || p_dm_odm->support_ic_type == ODM_RTL8723D || p_dm_odm->support_ic_type == ODM_RTL8710B) {
bb_swing = odm_get_bb_reg(p_dm_odm, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 0xFFC00000);
p_swing_table = ofdm_swing_table_new;
@ -562,6 +560,37 @@ get_swing_index(
return i;
}
u8
get_cck_swing_index(
void *p_dm_void
)
{
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
u8 i = 0;
u32 bb_cck_swing;
if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8723B ||
p_dm_odm->support_ic_type == ODM_RTL8192E) {
bb_cck_swing = odm_read_1byte(p_dm_odm, 0xa22);
for (i = 0; i < CCK_TABLE_SIZE; i++) {
if (bb_cck_swing == cck_swing_table_ch1_ch13_new[i][0])
break;
}
} else if (p_dm_odm->support_ic_type == ODM_RTL8703B) {
bb_cck_swing = odm_read_1byte(p_dm_odm, 0xa22);
for (i = 0; i < CCK_TABLE_SIZE_88F; i++) {
if (bb_cck_swing == cck_swing_table_ch1_ch14_88f[i][0])
break;
}
}
return i;
}
void
odm_txpowertracking_thermal_meter_init(
void *p_dm_void
@ -569,6 +598,7 @@ odm_txpowertracking_thermal_meter_init(
{
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
u8 default_swing_index = get_swing_index(p_dm_odm);
u8 default_cck_swing_index = get_cck_swing_index(p_dm_odm);
struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
@ -637,7 +667,7 @@ odm_txpowertracking_thermal_meter_init(
if (p_dm_odm->support_ic_type == ODM_RTL8188E || p_dm_odm->support_ic_type == ODM_RTL8723B ||
p_dm_odm->support_ic_type == ODM_RTL8192E || p_dm_odm->support_ic_type == ODM_RTL8703B) {
p_rf_calibrate_info->default_ofdm_index = (default_swing_index >= OFDM_TABLE_SIZE) ? 30 : default_swing_index;
p_rf_calibrate_info->default_cck_index = 20;
p_rf_calibrate_info->default_cck_index = (default_cck_swing_index >= CCK_TABLE_SIZE) ? 20 : default_cck_swing_index;
} else if (p_dm_odm->support_ic_type == ODM_RTL8188F) { /*add by Mingzhi.Guo 2015-03-23*/
p_rf_calibrate_info->default_ofdm_index = 28; /*OFDM: -1dB*/
p_rf_calibrate_info->default_cck_index = 20; /*CCK:-6dB*/

805
hal/phydm/rtl8821a/halhwimg8821a_bb.c 100644
View File

@ -0,0 +1,805 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*Image2HeaderVersion: 2.18*/
#include "mp_precomp.h"
#include "../phydm_precomp.h"
#if (RTL8821A_SUPPORT == 1)
static boolean
check_positive(
struct PHY_DM_STRUCT *p_dm_odm,
const u32 condition1,
const u32 condition2,
const u32 condition3,
const u32 condition4
)
{
u8 _board_type = ((p_dm_odm->board_type & BIT(4)) >> 4) << 0 | /* _GLNA*/
((p_dm_odm->board_type & BIT(3)) >> 3) << 1 | /* _GPA*/
((p_dm_odm->board_type & BIT(7)) >> 7) << 2 | /* _ALNA*/
((p_dm_odm->board_type & BIT(6)) >> 6) << 3 | /* _APA */
((p_dm_odm->board_type & BIT(2)) >> 2) << 4; /* _BT*/
u32 cond1 = condition1, cond2 = condition2, cond3 = condition3, cond4 = condition4;
u32 driver1 = p_dm_odm->cut_version << 24 |
(p_dm_odm->support_interface & 0xF0) << 16 |
p_dm_odm->support_platform << 16 |
p_dm_odm->package_type << 12 |
(p_dm_odm->support_interface & 0x0F) << 8 |
_board_type;
u32 driver2 = (p_dm_odm->type_glna & 0xFF) << 0 |
(p_dm_odm->type_gpa & 0xFF) << 8 |
(p_dm_odm->type_alna & 0xFF) << 16 |
(p_dm_odm->type_apa & 0xFF) << 24;
u32 driver3 = 0;
u32 driver4 = (p_dm_odm->type_glna & 0xFF00) >> 8 |
(p_dm_odm->type_gpa & 0xFF00) |
(p_dm_odm->type_alna & 0xFF00) << 8 |
(p_dm_odm->type_apa & 0xFF00) << 16;
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE,
("===> check_positive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4));
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE,
("===> check_positive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4));
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE,
(" (Platform, Interface) = (0x%X, 0x%X)\n", p_dm_odm->support_platform, p_dm_odm->support_interface));
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE,
(" (Board, Package) = (0x%X, 0x%X)\n", p_dm_odm->board_type, p_dm_odm->package_type));
/*============== value Defined Check ===============*/
/*QFN type [15:12] and cut version [27:24] need to do value check*/
if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000)))
return false;
if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000)))
return false;
/*=============== Bit Defined Check ================*/
/* We don't care [31:28] */
cond1 &= 0x00FF0FFF;
driver1 &= 0x00FF0FFF;
if ((cond1 & driver1) == cond1) {
u32 bit_mask = 0;
if ((cond1 & 0x0F) == 0) /* board_type is DONTCARE*/
return true;
if ((cond1 & BIT(0)) != 0) /*GLNA*/
bit_mask |= 0x000000FF;
if ((cond1 & BIT(1)) != 0) /*GPA*/
bit_mask |= 0x0000FF00;
if ((cond1 & BIT(2)) != 0) /*ALNA*/
bit_mask |= 0x00FF0000;
if ((cond1 & BIT(3)) != 0) /*APA*/
bit_mask |= 0xFF000000;
if (((cond2 & bit_mask) == (driver2 & bit_mask)) && ((cond4 & bit_mask) == (driver4 & bit_mask))) /* board_type of each RF path is matched*/
return true;
else
return false;
} else
return false;
}
static boolean
check_negative(
struct PHY_DM_STRUCT *p_dm_odm,
const u32 condition1,
const u32 condition2
)
{
return true;
}
/******************************************************************************
* AGC_TAB.TXT
******************************************************************************/
u32 array_mp_8821a_agc_tab[] = {
0x81C, 0xBF000001,
0x81C, 0xBF020001,
0x81C, 0xBF040001,
0x81C, 0xBF060001,
0x81C, 0xBE080001,
0x81C, 0xBD0A0001,
0x81C, 0xBC0C0001,
0x81C, 0xBA0E0001,
0x81C, 0xB9100001,
0x81C, 0xB8120001,
0x81C, 0xB7140001,
0x81C, 0xB6160001,
0x81C, 0xB5180001,
0x81C, 0xB41A0001,
0x81C, 0xB31C0001,
0x81C, 0xB21E0001,
0x81C, 0xB1200001,
0x81C, 0xB0220001,
0x81C, 0xAF240001,
0x81C, 0xAE260001,
0x81C, 0xAD280001,
0x81C, 0xAC2A0001,
0x81C, 0xAB2C0001,
0x81C, 0xAA2E0001,
0x81C, 0xA9300001,
0x81C, 0xA8320001,
0x81C, 0xA7340001,
0x81C, 0xA6360001,
0x81C, 0xA5380001,
0x81C, 0xA43A0001,
0x81C, 0x683C0001,
0x81C, 0x673E0001,
0x81C, 0x66400001,
0x81C, 0x65420001,
0x81C, 0x64440001,
0x81C, 0x63460001,
0x81C, 0x62480001,
0x81C, 0x614A0001,
0x81C, 0x474C0001,
0x81C, 0x464E0001,
0x81C, 0x45500001,
0x81C, 0x44520001,
0x81C, 0x43540001,
0x81C, 0x42560001,
0x81C, 0x41580001,
0x81C, 0x285A0001,
0x81C, 0x275C0001,
0x81C, 0x265E0001,
0x81C, 0x25600001,
0x81C, 0x24620001,
0x81C, 0x0A640001,
0x81C, 0x09660001,
0x81C, 0x08680001,
0x81C, 0x076A0001,
0x81C, 0x066C0001,
0x81C, 0x056E0001,
0x81C, 0x04700001,
0x81C, 0x03720001,
0x81C, 0x02740001,
0x81C, 0x01760001,
0x81C, 0x01780001,
0x81C, 0x017A0001,
0x81C, 0x017C0001,
0x81C, 0x017E0001,
0x8000020c, 0x00000000, 0x40000000, 0x00000000,
0x81C, 0xFB000101,
0x81C, 0xFA020101,
0x81C, 0xF9040101,
0x81C, 0xF8060101,
0x81C, 0xF7080101,
0x81C, 0xF60A0101,
0x81C, 0xF50C0101,
0x81C, 0xF40E0101,
0x81C, 0xF3100101,
0x81C, 0xF2120101,
0x81C, 0xF1140101,
0x81C, 0xF0160101,
0x81C, 0xEF180101,
0x81C, 0xEE1A0101,
0x81C, 0xED1C0101,
0x81C, 0xEC1E0101,
0x81C, 0xEB200101,
0x81C, 0xEA220101,
0x81C, 0xE9240101,
0x81C, 0xE8260101,
0x81C, 0xE7280101,
0x81C, 0xE62A0101,
0x81C, 0xE52C0101,
0x81C, 0xE42E0101,
0x81C, 0xE3300101,
0x81C, 0xA5320101,
0x81C, 0xA4340101,
0x81C, 0xA3360101,
0x81C, 0x87380101,
0x81C, 0x863A0101,
0x81C, 0x853C0101,
0x81C, 0x843E0101,
0x81C, 0x69400101,
0x81C, 0x68420101,
0x81C, 0x67440101,
0x81C, 0x66460101,
0x81C, 0x49480101,
0x81C, 0x484A0101,
0x81C, 0x474C0101,
0x81C, 0x2A4E0101,
0x81C, 0x29500101,
0x81C, 0x28520101,
0x81C, 0x27540101,
0x81C, 0x26560101,
0x81C, 0x25580101,
0x81C, 0x245A0101,
0x81C, 0x235C0101,
0x81C, 0x055E0101,
0x81C, 0x04600101,
0x81C, 0x03620101,
0x81C, 0x02640101,
0x81C, 0x01660101,
0x81C, 0x01680101,
0x81C, 0x016A0101,
0x81C, 0x016C0101,
0x81C, 0x016E0101,
0x81C, 0x01700101,
0x81C, 0x01720101,
0x9000040c, 0x00000000, 0x40000000, 0x00000000,
0x81C, 0xFB000101,
0x81C, 0xFA020101,
0x81C, 0xF9040101,
0x81C, 0xF8060101,
0x81C, 0xF7080101,
0x81C, 0xF60A0101,
0x81C, 0xF50C0101,
0x81C, 0xF40E0101,
0x81C, 0xF3100101,
0x81C, 0xF2120101,
0x81C, 0xF1140101,
0x81C, 0xF0160101,
0x81C, 0xEF180101,
0x81C, 0xEE1A0101,
0x81C, 0xED1C0101,
0x81C, 0xEC1E0101,
0x81C, 0xEB200101,
0x81C, 0xEA220101,
0x81C, 0xE9240101,
0x81C, 0xE8260101,
0x81C, 0xE7280101,
0x81C, 0xE62A0101,
0x81C, 0xE52C0101,
0x81C, 0xE42E0101,
0x81C, 0xE3300101,
0x81C, 0xA5320101,
0x81C, 0xA4340101,
0x81C, 0xA3360101,
0x81C, 0x87380101,
0x81C, 0x863A0101,
0x81C, 0x853C0101,
0x81C, 0x843E0101,
0x81C, 0x69400101,
0x81C, 0x68420101,
0x81C, 0x67440101,
0x81C, 0x66460101,
0x81C, 0x49480101,
0x81C, 0x484A0101,
0x81C, 0x474C0101,
0x81C, 0x2A4E0101,
0x81C, 0x29500101,
0x81C, 0x28520101,
0x81C, 0x27540101,
0x81C, 0x26560101,
0x81C, 0x25580101,
0x81C, 0x245A0101,
0x81C, 0x235C0101,
0x81C, 0x055E0101,
0x81C, 0x04600101,
0x81C, 0x03620101,
0x81C, 0x02640101,
0x81C, 0x01660101,
0x81C, 0x01680101,
0x81C, 0x016A0101,
0x81C, 0x016C0101,
0x81C, 0x016E0101,
0x81C, 0x01700101,
0x81C, 0x01720101,
0xA0000000, 0x00000000,
0x81C, 0xFF000101,
0x81C, 0xFF020101,
0x81C, 0xFE040101,
0x81C, 0xFD060101,
0x81C, 0xFC080101,
0x81C, 0xFD0A0101,
0x81C, 0xFC0C0101,
0x81C, 0xFB0E0101,
0x81C, 0xFA100101,
0x81C, 0xF9120101,
0x81C, 0xF8140101,
0x81C, 0xF7160101,
0x81C, 0xF6180101,
0x81C, 0xF51A0101,
0x81C, 0xF41C0101,
0x81C, 0xF31E0101,
0x81C, 0xF2200101,
0x81C, 0xF1220101,
0x81C, 0xF0240101,
0x81C, 0xEF260101,
0x81C, 0xEE280101,
0x81C, 0xED2A0101,
0x81C, 0xEC2C0101,
0x81C, 0xEB2E0101,
0x81C, 0xEA300101,
0x81C, 0xE9320101,
0x81C, 0xE8340101,
0x81C, 0xE7360101,
0x81C, 0xE6380101,
0x81C, 0xE53A0101,
0x81C, 0xE43C0101,
0x81C, 0xE33E0101,
0x81C, 0xA5400101,
0x81C, 0xA4420101,
0x81C, 0xA3440101,
0x81C, 0x87460101,
0x81C, 0x86480101,
0x81C, 0x854A0101,
0x81C, 0x844C0101,
0x81C, 0x694E0101,
0x81C, 0x68500101,
0x81C, 0x67520101,
0x81C, 0x66540101,
0x81C, 0x49560101,
0x81C, 0x48580101,
0x81C, 0x475A0101,
0x81C, 0x2A5C0101,
0x81C, 0x295E0101,
0x81C, 0x28600101,
0x81C, 0x27620101,
0x81C, 0x26640101,
0x81C, 0x25660101,
0x81C, 0x24680101,
0x81C, 0x236A0101,
0x81C, 0x056C0101,
0x81C, 0x046E0101,
0x81C, 0x03700101,
0x81C, 0x02720101,
0xB0000000, 0x00000000,
0x81C, 0x01740101,
0x81C, 0x01760101,
0x81C, 0x01780101,
0x81C, 0x017A0101,
0x81C, 0x017C0101,
0x81C, 0x017E0101,
0xC50, 0x00000022,
0xC50, 0x00000020,
};
void
odm_read_and_config_mp_8821a_agc_tab(
struct PHY_DM_STRUCT *p_dm_odm
)
{
u32 i = 0;
u8 c_cond;
boolean is_matched = true, is_skipped = false;
u32 array_len = sizeof(array_mp_8821a_agc_tab)/sizeof(u32);
u32 *array = array_mp_8821a_agc_tab;
u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8821A_AGC_TAB\n"));
while ((i + 1) < array_len) {
v1 = array[i];
v2 = array[i + 1];
if (v1 & (BIT(31) | BIT30)) {/*positive & negative condition*/
if (v1 & BIT(31)) {/* positive condition*/
c_cond = (u8)((v1 & (BIT(29) | BIT(28))) >> 28);
if (c_cond == COND_ENDIF) {/*end*/
is_matched = true;
is_skipped = false;
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n"));
} else if (c_cond == COND_ELSE) { /*else*/
is_matched = is_skipped ? false : true;
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n"));
}
else {/*if , else if*/
pre_v1 = v1;
pre_v2 = v2;
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n"));
}
} else if (v1 & BIT(30)) { /*negative condition*/
if (is_skipped == false) {
if (check_positive(p_dm_odm, pre_v1, pre_v2, v1, v2)) {
is_matched = true;
is_skipped = true;
} else {
is_matched = false;
is_skipped = false;
}
} else
is_matched = false;
}
} else {
if (is_matched)
odm_config_bb_agc_8821a(p_dm_odm, v1, MASKDWORD, v2);
}
i = i + 2;
}
}
u32
odm_get_version_mp_8821a_agc_tab(void)
{
return 57;
}
/******************************************************************************
* PHY_REG.TXT
******************************************************************************/
u32 array_mp_8821a_phy_reg[] = {
0x800, 0x0020D090,
0x804, 0x080112E0,
0x808, 0x0E028211,
0x80C, 0x92131111,
0x810, 0x20101261,
0x814, 0x020C3D10,
0x818, 0x03A00385,
0x820, 0x00000000,
0x824, 0x00030FE0,
0x828, 0x00000000,
0x82C, 0x002081DD,
0x830, 0x2AAAEEC8,
0x834, 0x0037A706,
0x838, 0x06489B44,
0x83C, 0x0000095B,
0x840, 0xC0000001,
0x844, 0x40003CDE,
0x848, 0x62103F8B,
0x84C, 0x6CFDFFB8,
0x850, 0x28874706,
0x854, 0x0001520C,
0x858, 0x8060E000,
0x85C, 0x74210168,
0x860, 0x6929C321,
0x864, 0x79727432,
0x868, 0x8CA7A314,
0x86C, 0x888C2878,
0x870, 0x08888888,
0x874, 0x31612C2E,
0x878, 0x00000152,
0x87C, 0x000FD000,
0x8A0, 0x00000013,
0x8A4, 0x7F7F7F7F,
0x8A8, 0xA2000338,
0x8AC, 0x0FF0FA0A,
0x8B4, 0x000FC080,
0x8B8, 0x6C10D7FF,
0x8BC, 0x0CA52090,
0x8C0, 0x1BF00020,
0x8C4, 0x00000000,
0x8C8, 0x00013169,
0x8CC, 0x08248492,
0x8D4, 0x940008A0,
0x8D8, 0x290B5612,
0x8F8, 0x400002C0,
0x8FC, 0x00000000,
0x900, 0x00000700,
0x90C, 0x00000000,
0x910, 0x0000FC00,
0x914, 0x00000404,
0x918, 0x1C1028C0,
0x91C, 0x64B11A1C,
0x920, 0xE0767233,
0x924, 0x055AA500,
0x928, 0x00000004,
0x92C, 0xFFFE0000,
0x930, 0xFFFFFFFE,
0x934, 0x001FFFFF,
0x960, 0x00000000,
0x964, 0x00000000,
0x968, 0x00000000,
0x96C, 0x00000000,
0x970, 0x801FFFFF,
0x974, 0x000003FF,
0x978, 0x00000000,
0x97C, 0x00000000,
0x980, 0x00000000,
0x984, 0x00000000,
0x988, 0x00000000,
0x990, 0x27100000,
0x994, 0xFFFF0100,
0x998, 0xFFFFFF5C,
0x99C, 0xFFFFFFFF,
0x9A0, 0x000000FF,
0x9A4, 0x00480080,
0x9A8, 0x00000000,
0x9AC, 0x00000000,
0x9B0, 0x81081008,
0x9B4, 0x01081008,
0x9B8, 0x01081008,
0x9BC, 0x01081008,
0x9D0, 0x00000000,
0x9D4, 0x00000000,
0x9D8, 0x00000000,
0x9DC, 0x00000000,
0x9E0, 0x00005D00,
0x9E4, 0x00000003,
0x9E8, 0x00000001,
0xA00, 0x00D047C8,
0xA04, 0x01FF800C,
0xA08, 0x8C8A8300,
0xA0C, 0x2E68000F,
0xA10, 0x9500BB78,
0xA14, 0x11144028,
0xA18, 0x00881117,
0xA1C, 0x89140F00,
0xA20, 0x1A1B0000,
0xA24, 0x090E1317,
0xA28, 0x00000204,
0xA2C, 0x00900000,
0xA70, 0x101FFF00,
0xA74, 0x00000008,
0xA78, 0x00000900,
0xA7C, 0x225B0606,
0xA80, 0x21805490,
0xA84, 0x001F0000,
0xB00, 0x03100040,
0xB04, 0x0000B000,
0xB08, 0xAE0201EB,
0xB0C, 0x01003207,
0xB10, 0x00009807,
0xB14, 0x01000000,
0xB18, 0x00000002,
0xB1C, 0x00000002,
0xB20, 0x0000001F,
0xB24, 0x03020100,
0xB28, 0x07060504,
0xB2C, 0x0B0A0908,
0xB30, 0x0F0E0D0C,
0xB34, 0x13121110,
0xB38, 0x17161514,
0xB3C, 0x0000003A,
0xB40, 0x00000000,
0xB44, 0x00000000,
0xB48, 0x13000032,
0xB4C, 0x48080000,
0xB50, 0x00000000,
0xB54, 0x00000000,
0xB58, 0x00000000,
0xB5C, 0x00000000,
0xC00, 0x00000007,
0xC04, 0x00042020,
0xC08, 0x80410231,
0xC0C, 0x00000000,
0xC10, 0x00000100,
0xC14, 0x01000000,
0xC1C, 0x40000003,
0xC20, 0x2C2C2C2C,
0xC24, 0x30303030,
0xC28, 0x30303030,
0xC2C, 0x2C2C2C2C,
0xC30, 0x2C2C2C2C,
0xC34, 0x2C2C2C2C,
0xC38, 0x2C2C2C2C,
0xC3C, 0x2A2A2A2A,
0xC40, 0x2A2A2A2A,
0xC44, 0x2A2A2A2A,
0xC48, 0x2A2A2A2A,
0xC4C, 0x2A2A2A2A,
0xC50, 0x00000020,
0xC54, 0x001C1208,
0xC58, 0x30000C1C,
0xC5C, 0x00000058,
0xC60, 0x34344443,
0xC64, 0x07003333,
0xC68, 0x19791979,
0xC6C, 0x19791979,
0xC70, 0x19791979,
0xC74, 0x19791979,
0xC78, 0x19791979,
0xC7C, 0x19791979,
0xC80, 0x19791979,
0xC84, 0x19791979,
0xC94, 0x0100005C,
0xC98, 0x00000000,
0xC9C, 0x00000000,
0xCA0, 0x00000029,
0xCA4, 0x08040201,
0xCA8, 0x80402010,
0xCB0, 0x77775747,
0xCB4, 0x10000077,
0xCB8, 0x00508240,
};
void
odm_read_and_config_mp_8821a_phy_reg(
struct PHY_DM_STRUCT *p_dm_odm
)
{
u32 i = 0;
u8 c_cond;
boolean is_matched = true, is_skipped = false;
u32 array_len = sizeof(array_mp_8821a_phy_reg)/sizeof(u32);
u32 *array = array_mp_8821a_phy_reg;
u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8821A_PHY_REG\n"));
while ((i + 1) < array_len) {
v1 = array[i];
v2 = array[i + 1];
if (v1 & (BIT(31) | BIT30)) {/*positive & negative condition*/
if (v1 & BIT(31)) {/* positive condition*/
c_cond = (u8)((v1 & (BIT(29) | BIT(28))) >> 28);
if (c_cond == COND_ENDIF) {/*end*/
is_matched = true;
is_skipped = false;
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n"));
} else if (c_cond == COND_ELSE) { /*else*/
is_matched = is_skipped ? false : true;
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n"));
}
else {/*if , else if*/
pre_v1 = v1;
pre_v2 = v2;
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n"));
}
} else if (v1 & BIT(30)) { /*negative condition*/
if (is_skipped == false) {
if (check_positive(p_dm_odm, pre_v1, pre_v2, v1, v2)) {
is_matched = true;
is_skipped = true;
} else {
is_matched = false;
is_skipped = false;
}
} else
is_matched = false;
}
} else {
if (is_matched)
odm_config_bb_phy_8821a(p_dm_odm, v1, MASKDWORD, v2);
}
i = i + 2;
}
}
u32
odm_get_version_mp_8821a_phy_reg(void)
{
return 57;
}
/******************************************************************************
* PHY_REG_PG.TXT
******************************************************************************/
u32 array_mp_8821a_phy_reg_pg[] = {
0, 0, 0, 0x00000c20, 0xffffffff, 0x32343638,
0, 0, 0, 0x00000c24, 0xffffffff, 0x36363838,
0, 0, 0, 0x00000c28, 0xffffffff, 0x28303234,
0, 0, 0, 0x00000c2c, 0xffffffff, 0x34363838,
0, 0, 0, 0x00000c30, 0xffffffff, 0x26283032,
0, 0, 0, 0x00000c3c, 0xffffffff, 0x32343636,
0, 0, 0, 0x00000c40, 0xffffffff, 0x24262830,
0, 0, 0, 0x00000c44, 0x0000ffff, 0x00002022,
1, 0, 0, 0x00000c24, 0xffffffff, 0x34343636,
1, 0, 0, 0x00000c28, 0xffffffff, 0x26283032,
1, 0, 0, 0x00000c2c, 0xffffffff, 0x32343636,
1, 0, 0, 0x00000c30, 0xffffffff, 0x24262830,
1, 0, 0, 0x00000c3c, 0xffffffff, 0x32343636,
1, 0, 0, 0x00000c40, 0xffffffff, 0x24262830,
1, 0, 0, 0x00000c44, 0x0000ffff, 0x00002022
};
void
odm_read_and_config_mp_8821a_phy_reg_pg(
struct PHY_DM_STRUCT *p_dm_odm
)
{
u32 i = 0;
u32 array_len = sizeof(array_mp_8821a_phy_reg_pg)/sizeof(u32);
u32 *array = array_mp_8821a_phy_reg_pg;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
struct _ADAPTER *adapter = p_dm_odm->adapter;
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
PlatformZeroMemory(p_hal_data->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT * MAX_BYTES_LINE_HWCONFIG_TXT);
p_hal_data->nLinesReadPwrByRate = array_len / 6;
#endif
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8821A_PHY_REG_PG\n"));
p_dm_odm->phy_reg_pg_version = 1;
p_dm_odm->phy_reg_pg_value_type = PHY_REG_PG_EXACT_VALUE;
for (i = 0; i < array_len; i += 6) {
u32 v1 = array[i];
u32 v2 = array[i + 1];
u32 v3 = array[i + 2];
u32 v4 = array[i + 3];
u32 v5 = array[i + 4];
u32 v6 = array[i + 5];
odm_config_bb_phy_reg_pg_8821a(p_dm_odm, v1, v2, v3, v4, v5, v6);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
rsprintf((char *)p_hal_data->BufOfLinesPwrByRate[i / 6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,",
(v1 == 0 ? "2.4G" : " 5G"), (v2 == 0 ? "A" : "B"), (v3 == 0 ? "1Tx" : "2Tx"), v4, v5, v6);
#endif
}
}
/******************************************************************************
* PHY_REG_PG_E202SA.TXT
******************************************************************************/
u32 array_mp_8821a_phy_reg_pg_e202sa[] = {
0, 0, 0, 0x00000c20, 0xffffffff, 0x32323232,
0, 0, 0, 0x00000c24, 0xffffffff, 0x28282828,
0, 0, 0, 0x00000c28, 0xffffffff, 0x28282828,
0, 0, 0, 0x00000c2c, 0xffffffff, 0x22222222,
0, 0, 0, 0x00000c30, 0xffffffff, 0x22222222,
0, 0, 0, 0x00000c3c, 0xffffffff, 0x32343636,
0, 0, 0, 0x00000c40, 0xffffffff, 0x24262830,
0, 0, 0, 0x00000c44, 0x0000ffff, 0x00002022,
1, 0, 0, 0x00000c24, 0xffffffff, 0x26262626,
1, 0, 0, 0x00000c28, 0xffffffff, 0x26262626,
1, 0, 0, 0x00000c2c, 0xffffffff, 0x20202020,
1, 0, 0, 0x00000c30, 0xffffffff, 0x20202020,
1, 0, 0, 0x00000c3c, 0xffffffff, 0x16161616,
1, 0, 0, 0x00000c40, 0xffffffff, 0x16161616,
1, 0, 0, 0x00000c44, 0x0000ffff, 0x00001616
};
void
odm_read_and_config_mp_8821a_phy_reg_pg_e202sa(
struct PHY_DM_STRUCT *p_dm_odm
)
{
u32 i = 0;
u32 array_len = sizeof(array_mp_8821a_phy_reg_pg_e202sa)/sizeof(u32);
u32 *array = array_mp_8821a_phy_reg_pg_e202sa;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
struct _ADAPTER *adapter = p_dm_odm->adapter;
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
PlatformZeroMemory(p_hal_data->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT * MAX_BYTES_LINE_HWCONFIG_TXT);
p_hal_data->nLinesReadPwrByRate = array_len / 6;
#endif
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8821A_PHY_REG_PG_E202SA\n"));
p_dm_odm->phy_reg_pg_version = 1;
p_dm_odm->phy_reg_pg_value_type = PHY_REG_PG_EXACT_VALUE;
for (i = 0; i < array_len; i += 6) {
u32 v1 = array[i];
u32 v2 = array[i + 1];
u32 v3 = array[i + 2];
u32 v4 = array[i + 3];
u32 v5 = array[i + 4];
u32 v6 = array[i + 5];
odm_config_bb_phy_reg_pg_8821a(p_dm_odm, v1, v2, v3, v4, v5, v6);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
rsprintf((char *)p_hal_data->BufOfLinesPwrByRate[i / 6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,",
(v1 == 0 ? "2.4G" : " 5G"), (v2 == 0 ? "A" : "B"), (v3 == 0 ? "1Tx" : "2Tx"), v4, v5, v6);
#endif
}
}
#endif /* end of HWIMG_SUPPORT*/

69
hal/phydm/rtl8821a/halhwimg8821a_bb.h 100644
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@ -0,0 +1,69 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*Image2HeaderVersion: 2.18*/
#if (RTL8821A_SUPPORT == 1)
#ifndef __INC_MP_BB_HW_IMG_8821A_H
#define __INC_MP_BB_HW_IMG_8821A_H
/******************************************************************************
* AGC_TAB.TXT
******************************************************************************/
void
odm_read_and_config_mp_8821a_agc_tab(/* TC: Test Chip, MP: MP Chip*/
struct PHY_DM_STRUCT *p_dm_odm
);
u32 odm_get_version_mp_8821a_agc_tab(void);
/******************************************************************************
* PHY_REG.TXT
******************************************************************************/
void
odm_read_and_config_mp_8821a_phy_reg(/* TC: Test Chip, MP: MP Chip*/
struct PHY_DM_STRUCT *p_dm_odm
);
u32 odm_get_version_mp_8821a_phy_reg(void);
/******************************************************************************
* PHY_REG_PG.TXT
******************************************************************************/
void
odm_read_and_config_mp_8821a_phy_reg_pg(/* TC: Test Chip, MP: MP Chip*/
struct PHY_DM_STRUCT *p_dm_odm
);
u32 odm_get_version_mp_8821a_phy_reg_pg(void);
/******************************************************************************
* PHY_REG_PG_E202SA.TXT
******************************************************************************/
void
odm_read_and_config_mp_8821a_phy_reg_pg_e202sa(/* TC: Test Chip, MP: MP Chip*/
struct PHY_DM_STRUCT *p_dm_odm
);
u32 odm_get_version_mp_8821a_phy_reg_pg_e202sa(void);
#endif
#endif /* end of HWIMG_SUPPORT*/

6643
hal/phydm/rtl8821a/halhwimg8821a_fw.c 100644
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File diff suppressed because it is too large Load Diff

73
hal/phydm/rtl8821a/halhwimg8821a_fw.h 100644
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@ -0,0 +1,73 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*Image2HeaderVersion: 2.16*/
#if (RTL8821A_SUPPORT == 1)
#ifndef __INC_MP_FW_HW_IMG_8821A_H
#define __INC_MP_FW_HW_IMG_8821A_H
/******************************************************************************
* FW_AP.TXT
******************************************************************************/
void
odm_read_firmware_mp_8821a_fw_ap(
struct PHY_DM_STRUCT *p_dm_odm,
u8 *p_firmware,
u32 *p_firmware_size
);
/******************************************************************************
* FW_NIC.TXT
******************************************************************************/
void
odm_read_firmware_mp_8821a_fw_nic(
struct PHY_DM_STRUCT *p_dm_odm,
u8 *p_firmware,
u32 *p_firmware_size
);
/******************************************************************************
* FW_NIC_BT.TXT
******************************************************************************/
void
odm_read_firmware_mp_8821a_fw_nic_bt(
struct PHY_DM_STRUCT *p_dm_odm,
u8 *p_firmware,
u32 *p_firmware_size
);
/******************************************************************************
* FW_WoWLAN.TXT
******************************************************************************/
void
odm_read_firmware_mp_8821a_fw_wowlan(
struct PHY_DM_STRUCT *p_dm_odm,
u8 *p_firmware,
u32 *p_firmware_size
);
#endif
#endif /* end of HWIMG_SUPPORT*/

285
hal/phydm/rtl8821a/halhwimg8821a_mac.c 100644
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@ -0,0 +1,285 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*Image2HeaderVersion: 2.18*/
#include "mp_precomp.h"
#include "../phydm_precomp.h"
#if (RTL8812A_SUPPORT == 1)
static boolean
check_positive(
struct PHY_DM_STRUCT *p_dm_odm,
const u32 condition1,
const u32 condition2,
const u32 condition3,
const u32 condition4
)
{
u8 _board_type = ((p_dm_odm->board_type & BIT(4)) >> 4) << 0 | /* _GLNA*/
((p_dm_odm->board_type & BIT(3)) >> 3) << 1 | /* _GPA*/
((p_dm_odm->board_type & BIT(7)) >> 7) << 2 | /* _ALNA*/
((p_dm_odm->board_type & BIT(6)) >> 6) << 3 | /* _APA */
((p_dm_odm->board_type & BIT(2)) >> 2) << 4; /* _BT*/
u32 cond1 = condition1, cond2 = condition2, cond3 = condition3, cond4 = condition4;
u32 driver1 = p_dm_odm->cut_version << 24 |
(p_dm_odm->support_interface & 0xF0) << 16 |
p_dm_odm->support_platform << 16 |
p_dm_odm->package_type << 12 |
(p_dm_odm->support_interface & 0x0F) << 8 |
_board_type;
u32 driver2 = (p_dm_odm->type_glna & 0xFF) << 0 |
(p_dm_odm->type_gpa & 0xFF) << 8 |
(p_dm_odm->type_alna & 0xFF) << 16 |
(p_dm_odm->type_apa & 0xFF) << 24;
u32 driver3 = 0;
u32 driver4 = (p_dm_odm->type_glna & 0xFF00) >> 8 |
(p_dm_odm->type_gpa & 0xFF00) |
(p_dm_odm->type_alna & 0xFF00) << 8 |
(p_dm_odm->type_apa & 0xFF00) << 16;
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE,
("===> check_positive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4));
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE,
("===> check_positive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4));
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE,
(" (Platform, Interface) = (0x%X, 0x%X)\n", p_dm_odm->support_platform, p_dm_odm->support_interface));
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE,
(" (Board, Package) = (0x%X, 0x%X)\n", p_dm_odm->board_type, p_dm_odm->package_type));
/*============== value Defined Check ===============*/
/*QFN type [15:12] and cut version [27:24] need to do value check*/
if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000)))
return false;
if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000)))
return false;
/*=============== Bit Defined Check ================*/
/* We don't care [31:28] */
cond1 &= 0x00FF0FFF;
driver1 &= 0x00FF0FFF;
if ((cond1 & driver1) == cond1) {
u32 bit_mask = 0;
if ((cond1 & 0x0F) == 0) /* board_type is DONTCARE*/
return true;
if ((cond1 & BIT(0)) != 0) /*GLNA*/
bit_mask |= 0x000000FF;
if ((cond1 & BIT(1)) != 0) /*GPA*/
bit_mask |= 0x0000FF00;
if ((cond1 & BIT(2)) != 0) /*ALNA*/
bit_mask |= 0x00FF0000;
if ((cond1 & BIT(3)) != 0) /*APA*/
bit_mask |= 0xFF000000;
if (((cond2 & bit_mask) == (driver2 & bit_mask)) && ((cond4 & bit_mask) == (driver4 & bit_mask))) /* board_type of each RF path is matched*/
return true;
else
return false;
} else
return false;
}
static boolean
check_negative(
struct PHY_DM_STRUCT *p_dm_odm,
const u32 condition1,
const u32 condition2
)
{
return true;
}
/******************************************************************************
* MAC_REG.TXT
******************************************************************************/
u32 array_mp_8821a_mac_reg[] = {
0x421, 0x0000000F,
0x428, 0x0000000A,
0x429, 0x00000010,
0x430, 0x00000000,
0x431, 0x00000000,
0x432, 0x00000000,
0x433, 0x00000001,
0x434, 0x00000004,
0x435, 0x00000005,
0x436, 0x00000007,
0x437, 0x00000008,
0x43C, 0x00000004,
0x43D, 0x00000005,
0x43E, 0x00000007,
0x43F, 0x00000008,
0x440, 0x0000005D,
0x441, 0x00000001,
0x442, 0x00000000,
0x444, 0x00000010,
0x445, 0x00000000,
0x446, 0x00000000,
0x447, 0x00000000,
0x448, 0x00000000,
0x449, 0x000000F0,
0x44A, 0x0000000F,
0x44B, 0x0000003E,
0x44C, 0x00000010,
0x44D, 0x00000000,
0x44E, 0x00000000,
0x44F, 0x00000000,
0x450, 0x00000000,
0x451, 0x000000F0,
0x452, 0x0000000F,
0x453, 0x00000000,
0x456, 0x0000005E,
0x460, 0x00000066,
0x461, 0x00000066,
0x4C8, 0x0000003F,
0x4C9, 0x000000FF,
0x4CC, 0x000000FF,
0x4CD, 0x000000FF,
0x4CE, 0x00000001,
0x500, 0x00000026,
0x501, 0x000000A2,
0x502, 0x0000002F,
0x503, 0x00000000,
0x504, 0x00000028,
0x505, 0x000000A3,
0x506, 0x0000005E,
0x507, 0x00000000,
0x508, 0x0000002B,
0x509, 0x000000A4,
0x50A, 0x0000005E,
0x50B, 0x00000000,
0x50C, 0x0000004F,
0x50D, 0x000000A4,
0x50E, 0x00000000,
0x50F, 0x00000000,
0x512, 0x0000001C,
0x514, 0x0000000A,
0x516, 0x0000000A,
0x525, 0x0000004F,
0x550, 0x00000010,
0x551, 0x00000010,
0x559, 0x00000002,
0x55C, 0x00000050,
0x55D, 0x000000FF,
0x605, 0x00000030,
0x607, 0x00000007,
0x608, 0x0000000E,
0x609, 0x0000002A,
0x620, 0x000000FF,
0x621, 0x000000FF,
0x622, 0x000000FF,
0x623, 0x000000FF,
0x624, 0x000000FF,
0x625, 0x000000FF,
0x626, 0x000000FF,
0x627, 0x000000FF,
0x638, 0x00000050,
0x63C, 0x0000000A,
0x63D, 0x0000000A,
0x63E, 0x0000000E,
0x63F, 0x0000000E,
0x640, 0x00000040,
0x642, 0x00000040,
0x643, 0x00000000,
0x652, 0x000000C8,
0x66E, 0x00000005,
0x700, 0x00000021,
0x701, 0x00000043,
0x702, 0x00000065,
0x703, 0x00000087,
0x708, 0x00000021,
0x709, 0x00000043,
0x70A, 0x00000065,
0x70B, 0x00000087,
0x718, 0x00000040,
};
void
odm_read_and_config_mp_8821a_mac_reg(
struct PHY_DM_STRUCT *p_dm_odm
)
{
u32 i = 0;
u8 c_cond;
boolean is_matched = true, is_skipped = false;
u32 array_len = sizeof(array_mp_8821a_mac_reg) / sizeof(u32);
u32 *array = array_mp_8821a_mac_reg;
u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> odm_read_and_config_mp_8812a_mac_reg\n"));
while ((i + 1) < array_len) {
v1 = array[i];
v2 = array[i + 1];
if (v1 & (BIT(31) | BIT30)) {/*positive & negative condition*/
if (v1 & BIT(31)) {/* positive condition*/
c_cond = (u8)((v1 & (BIT(29) | BIT(28))) >> 28);
if (c_cond == COND_ENDIF) {/*end*/
is_matched = true;
is_skipped = false;
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n"));
} else if (c_cond == COND_ELSE) { /*else*/
is_matched = is_skipped ? false : true;
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n"));
} else {/*if , else if*/
pre_v1 = v1;
pre_v2 = v2;
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n"));
}
} else if (v1 & BIT(30)) { /*negative condition*/
if (is_skipped == false) {
if (check_positive(p_dm_odm, pre_v1, pre_v2, v1, v2)) {
is_matched = true;
is_skipped = true;
} else {
is_matched = false;
is_skipped = false;
}
} else
is_matched = false;
}
} else {
if (is_matched)
odm_config_mac_8821a(p_dm_odm, v1, (u8)v2);
}
i = i + 2;
}
}
u32
odm_get_version_mp_8821a_mac_reg(void)
{
return 57;
}
#endif /* end of HWIMG_SUPPORT*/

39
hal/phydm/rtl8821a/halhwimg8821a_mac.h 100644
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*Image2HeaderVersion: 2.18*/
#if (RTL8821A_SUPPORT == 1)
#ifndef __INC_MP_MAC_HW_IMG_8821A_H
#define __INC_MP_MAC_HW_IMG_8821A_H
/******************************************************************************
* MAC_REG.TXT
******************************************************************************/
void
odm_read_and_config_mp_8821a_mac_reg(/* TC: Test Chip, MP: MP Chip*/
struct PHY_DM_STRUCT *p_dm_odm
);
u32 odm_get_version_mp_8821a_mac_reg(void);
#endif
#endif /* end of HWIMG_SUPPORT*/

5462
hal/phydm/rtl8821a/halhwimg8821a_rf.c 100644
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File diff suppressed because it is too large Load Diff

149
hal/phydm/rtl8821a/halhwimg8821a_rf.h 100644
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*Image2HeaderVersion: 2.18*/
#if (RTL8821A_SUPPORT == 1)
#ifndef __INC_MP_RF_HW_IMG_8821A_H
#define __INC_MP_RF_HW_IMG_8821A_H
/******************************************************************************
* RadioA.TXT
******************************************************************************/
void
odm_read_and_config_mp_8821a_radioa(/* TC: Test Chip, MP: MP Chip*/
struct PHY_DM_STRUCT *p_dm_odm
);
u32 odm_get_version_mp_8821a_radioa(void);
/******************************************************************************
* RadioB.TXT
******************************************************************************/
void
odm_read_and_config_mp_8821a_radiob(/* TC: Test Chip, MP: MP Chip*/
struct PHY_DM_STRUCT *p_dm_odm
);
u32 odm_get_version_mp_8821a_radiob(void);
/******************************************************************************
* TxPowerTrack_PCIE.TXT
******************************************************************************/
void
odm_read_and_config_mp_8821a_txpowertrack_pcie(/* TC: Test Chip, MP: MP Chip*/
struct PHY_DM_STRUCT *p_dm_odm
);
u32 odm_get_version_mp_8821a_txpowertrack_pcie(void);
/******************************************************************************
* TxPowerTrack_SDIO.TXT
******************************************************************************/
void
odm_read_and_config_mp_8821a_txpowertrack_sdio(/* TC: Test Chip, MP: MP Chip*/
struct PHY_DM_STRUCT *p_dm_odm
);
u32 odm_get_version_mp_8821a_txpower_track_sdio(void);
/******************************************************************************
* TxPowerTrack_USB.TXT
******************************************************************************/
void
odm_read_and_config_mp_8821a_txpowertrack_usb(/* TC: Test Chip, MP: MP Chip*/
struct PHY_DM_STRUCT *p_dm_odm
);
u32 odm_get_version_mp_8821a_txpower_track_usb(void);
/******************************************************************************
* TXPWR_LMT_8811AU_FEM.TXT
******************************************************************************/
void
odm_read_and_config_mp_8821a_txpwr_lmt_8811a_u_fem(/* TC: Test Chip, MP: MP Chip*/
struct PHY_DM_STRUCT *p_dm_odm
);
u32 odm_get_version_mp_8821a_txpwr_lmt_8811a_u_fem(void);
/******************************************************************************
* TXPWR_LMT_8811AU_IPA.TXT
******************************************************************************/
void
odm_read_and_config_mp_8821a_txpwr_lmt_8811a_u_ipa(/* TC: Test Chip, MP: MP Chip*/
struct PHY_DM_STRUCT *p_dm_odm
);
u32 odm_get_version_mp_8821a_txpwr_lmt_8811a_u_ipa(void);
/******************************************************************************
* TXPWR_LMT_8821A.TXT
******************************************************************************/
void
odm_read_and_config_mp_8821a_txpwr_lmt_8821a(/* TC: Test Chip, MP: MP Chip*/
struct PHY_DM_STRUCT *p_dm_odm
);
u32 odm_get_version_mp_8821a_txpwr_lmt_8821a(void);
/******************************************************************************
* TXPWR_LMT_8821A_E202SA.TXT
******************************************************************************/
void
odm_read_and_config_mp_8821a_txpwr_lmt_8821A_e202sa(/* TC: Test Chip, MP: MP Chip*/
struct PHY_DM_STRUCT *p_dm_odm
);
u32 odm_get_version_mp_8821a_txpwr_lmt_8821a_e202sa(void);
/******************************************************************************
* TXPWR_LMT_8821A_SAR_13dBm.TXT
******************************************************************************/
void
odm_read_and_config_mp_8821a_txpwr_lmt_8821a_sar_13dBm(/* TC: Test Chip, MP: MP Chip*/
struct PHY_DM_STRUCT *p_dm_odm
);
u32 odm_get_version_mp_8821a_txpwr_lmt_8821a_sar_13dBm(void);
/******************************************************************************
* TXPWR_LMT_8821A_SAR_5mm.TXT
******************************************************************************/
void
odm_read_and_config_mp_8821A_txpwr_lmt_8821a_sar_5mm(/* TC: Test Chip, MP: MP Chip*/
struct PHY_DM_STRUCT *p_dm_odm
);
u32 odm_get_version_mp_8821a_txpwr_lmt_8821a_sar_5mm(void);
/******************************************************************************
* TXPWR_LMT_8821A_SAR_8mm.TXT
******************************************************************************/
void
odm_read_and_config_mp_8821a_txpwr_lmt_8821a_sar_8mm(/* TC: Test Chip, MP: MP Chip*/
struct PHY_DM_STRUCT *p_dm_odm
);
u32 odm_get_version_mp_8821a_txpwr_lmt_8821a_sar_8mm(void);
#endif
#endif /* end of HWIMG_SUPPORT*/

312
hal/phydm/rtl8821a/halphyrf_8821a_ce.c 100644
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#include "mp_precomp.h"
#include "../phydm_precomp.h"
/*---------------------------Define Local Constant---------------------------*/
/* 2010/04/25 MH Define the max tx power tracking tx agc power. */
#define ODM_TXPWRTRACK_MAX_IDX8821A 6
/*---------------------------Define Local Constant---------------------------*/
/* 3============================================================
* 3 Tx Power Tracking
* 3============================================================ */
void odm_tx_pwr_track_set_pwr8821a(
void *p_dm_void,
enum pwrtrack_method method,
u8 rf_path,
u8 channel_mapped_index
)
{
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
struct _ADAPTER *adapter = p_dm_odm->adapter;
HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
u8 pwr_tracking_limit = 26; /* +1.0dB */
u8 tx_rate = 0xFF;
u8 final_ofdm_swing_index = 0;
u8 final_cck_swing_index = 0;
u8 i = 0;
u32 final_bb_swing_idx[1];
struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info);
if (*(p_dm_odm->p_mp_mode) == true) {
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
#if (MP_DRIVER == 1)
PMPT_CONTEXT p_mpt_ctx = &(adapter->mpt_ctx);
tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index);
#endif
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
PMPT_CONTEXT p_mpt_ctx = &(adapter->mppriv.mpt_ctx);
tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index);
#endif
#endif
} else {
u16 rate = *(p_dm_odm->p_forced_data_rate);
if (!rate) { /*auto rate*/
if (rate != 0xFF) {
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
tx_rate = adapter->HalFunc.GetHwRateFromMRateHandler(p_dm_odm->tx_rate);
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
tx_rate = hw_rate_to_m_rate(p_dm_odm->tx_rate);
#endif
}
} else /*force rate*/
tx_rate = (u8)rate;
}
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", tx_rate));
ODM_RT_TRACE(p_dm_odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("===>ODM_TxPwrTrackSetPwr8821A\n"));
if(tx_rate != 0xFF) {
/* 2 CCK */
if((tx_rate >= MGN_1M)&&(tx_rate <= MGN_11M))
pwr_tracking_limit = 32; //+4dB
//2 OFDM
else if((tx_rate >= MGN_6M)&&(tx_rate <= MGN_48M))
pwr_tracking_limit = 30; //+3dB
else if(tx_rate == MGN_54M)
pwr_tracking_limit = 28; //+2dB
//2 HT
else if((tx_rate >= MGN_MCS0)&&(tx_rate <= MGN_MCS2)) //QPSK/BPSK
pwr_tracking_limit = 34; //+5dB
else if((tx_rate >= MGN_MCS3)&&(tx_rate <= MGN_MCS4)) //16QAM
pwr_tracking_limit = 30; //+3dB
else if((tx_rate >= MGN_MCS5)&&(tx_rate <= MGN_MCS7)) //64QAM
pwr_tracking_limit = 28; //+2dB
//2 VHT
else if((tx_rate >= MGN_VHT1SS_MCS0)&&(tx_rate <= MGN_VHT1SS_MCS2)) //QPSK/BPSK
pwr_tracking_limit = 34; //+5dB
else if((tx_rate >= MGN_VHT1SS_MCS3)&&(tx_rate <= MGN_VHT1SS_MCS4)) //16QAM
pwr_tracking_limit = 30; //+3dB
else if((tx_rate >= MGN_VHT1SS_MCS5)&&(tx_rate <= MGN_VHT1SS_MCS6)) //64QAM
pwr_tracking_limit = 28; //+2dB
else if(tx_rate == MGN_VHT1SS_MCS7) //64QAM
pwr_tracking_limit = 26; //+1dB
else if(tx_rate == MGN_VHT1SS_MCS8) //256QAM
pwr_tracking_limit = 24; //+0dB
else if(tx_rate == MGN_VHT1SS_MCS9) /* 256QAM */
pwr_tracking_limit = 22; //-1dB
else
pwr_tracking_limit = 24;
}
ODM_RT_TRACE(p_dm_odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("tx_rate=0x%x, pwr_tracking_limit=%d\n", tx_rate, pwr_tracking_limit));
if (method == BBSWING) {
if (rf_path == ODM_RF_PATH_A) {
final_bb_swing_idx[ODM_RF_PATH_A] = (p_dm_odm->rf_calibrate_info.OFDM_index[ODM_RF_PATH_A] > pwr_tracking_limit) ? pwr_tracking_limit : p_dm_odm->rf_calibrate_info.OFDM_index[ODM_RF_PATH_A];
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("p_dm_odm->rf_calibrate_info.OFDM_index[ODM_RF_PATH_A]=%d, p_dm_odm->RealBbSwingIdx[ODM_RF_PATH_A]=%d\n",
p_dm_odm->rf_calibrate_info.OFDM_index[ODM_RF_PATH_A], final_bb_swing_idx[ODM_RF_PATH_A]));
odm_set_bb_reg(p_dm_odm, REG_B_TX_SCALE_JAGUAR, 0xFFE00000, tx_scaling_table_jaguar[final_bb_swing_idx[ODM_RF_PATH_A]]);
}
}
else if (method == MIX_MODE) {
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("p_rf_calibrate_info->default_ofdm_index=%d, p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path]=%d, RF_Path = %d\n",
p_rf_calibrate_info->default_ofdm_index, p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path], rf_path));
final_cck_swing_index = p_rf_calibrate_info->default_cck_index + p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path];
final_ofdm_swing_index = p_rf_calibrate_info->default_ofdm_index + p_rf_calibrate_info->absolute_ofdm_swing_idx[rf_path];
if (rf_path == ODM_RF_PATH_A)
{
if (final_ofdm_swing_index > pwr_tracking_limit) /*BBSwing higher then Limit*/
{
p_rf_calibrate_info->remnant_cck_swing_idx = final_cck_swing_index - pwr_tracking_limit;
p_rf_calibrate_info->remnant_ofdm_swing_idx[rf_path] = final_ofdm_swing_index - pwr_tracking_limit;
odm_set_bb_reg(p_dm_odm, REG_A_TX_SCALE_JAGUAR, 0xFFE00000, tx_scaling_table_jaguar[pwr_tracking_limit]);
p_rf_calibrate_info->modify_tx_agc_flag_path_a = true;
phy_set_tx_power_level_by_path(adapter, *p_dm_odm->p_channel, ODM_RF_PATH_A);
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A Over BBSwing Limit, PwrTrackingLimit = %d , Remnant TxAGC Value = %d\n", pwr_tracking_limit, p_rf_calibrate_info->remnant_ofdm_swing_idx[rf_path]));
} else if (final_ofdm_swing_index <= 0) {
p_rf_calibrate_info->remnant_cck_swing_idx = final_cck_swing_index;
p_rf_calibrate_info->remnant_ofdm_swing_idx[rf_path] = final_ofdm_swing_index;
odm_set_bb_reg(p_dm_odm, REG_A_TX_SCALE_JAGUAR, 0xFFE00000, tx_scaling_table_jaguar[0]);
p_rf_calibrate_info->modify_tx_agc_flag_path_a = true;
phy_set_tx_power_level_by_path(adapter, *p_dm_odm->p_channel, ODM_RF_PATH_A);
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A Lower then BBSwing lower bound 0, Remnant tx_agc value = %d\n", p_rf_calibrate_info->remnant_ofdm_swing_idx[rf_path]));
} else {
odm_set_bb_reg(p_dm_odm, REG_A_TX_SCALE_JAGUAR, 0xFFE00000, tx_scaling_table_jaguar[final_ofdm_swing_index]);
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A Compensate with BBSwing, final_ofdm_swing_index = %d\n", final_ofdm_swing_index));
if (p_rf_calibrate_info->modify_tx_agc_flag_path_a) { /*If tx_agc has changed, reset tx_agc again*/
p_rf_calibrate_info->remnant_cck_swing_idx = 0;
p_rf_calibrate_info->remnant_ofdm_swing_idx[rf_path] = 0;
phy_set_tx_power_level_by_path(adapter, *p_dm_odm->p_channel, ODM_RF_PATH_A);
p_rf_calibrate_info->modify_tx_agc_flag_path_a = false;
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Path_A p_dm_odm->Modify_TxAGC_Flag = false\n"));
}
}
}
}
else
{
return;
}
} // odm_TxPwrTrackSetPwr88E
void get_delta_swing_table_8821a(
void* p_dm_void,
u8* *TemperatureUP_A,
u8* *TemperatureDOWN_A,
u8* *TemperatureUP_B,
u8* *TemperatureDOWN_B
)
{
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
struct _ADAPTER *adapter = p_dm_odm->adapter;
struct odm_rf_calibration_structure *p_rf_calibrate_info = &(p_dm_odm->rf_calibrate_info);
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter);
u8 TxRate = 0xFF;
u8 channel = pHalData->current_channel;
if (*(p_dm_odm->p_mp_mode) == true) {
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
#if (MP_DRIVER == 1)
PMPT_CONTEXT pMptCtx = &(adapter->MptCtx);
TxRate = mpt_to_mgnt_rate(pMptCtx->MptRateIndex);
#endif
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
PMPT_CONTEXT pMptCtx = &(adapter->mppriv.mpt_ctx);
TxRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
#endif
#endif
} else {
u16 rate = *(p_dm_odm->p_forced_data_rate);
if (!rate) { /*auto rate*/
if (rate != 0xFF) {
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
TxRate = adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate);
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
TxRate = hw_rate_to_m_rate(p_dm_odm->tx_rate);
#endif
}
} else { /*force rate*/
TxRate = (u8)rate;
}
}
ODM_RT_TRACE(p_dm_odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate));
if ( 1 <= channel && channel <= 14) {
if (IS_CCK_RATE(TxRate)) {
*TemperatureUP_A = p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_p;
*TemperatureDOWN_A = p_rf_calibrate_info->delta_swing_table_idx_2g_cck_a_n;
*TemperatureUP_B = p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_p;
*TemperatureDOWN_B = p_rf_calibrate_info->delta_swing_table_idx_2g_cck_b_n;
} else {
*TemperatureUP_A = p_rf_calibrate_info->delta_swing_table_idx_2ga_p;
*TemperatureDOWN_A = p_rf_calibrate_info->delta_swing_table_idx_2ga_n;
*TemperatureUP_B = p_rf_calibrate_info->delta_swing_table_idx_2gb_p;
*TemperatureDOWN_B = p_rf_calibrate_info->delta_swing_table_idx_2gb_n;
}
} else if ( 36 <= channel && channel <= 64) {
*TemperatureUP_A = p_rf_calibrate_info->delta_swing_table_idx_5ga_p[0];
*TemperatureDOWN_A = p_rf_calibrate_info->delta_swing_table_idx_5ga_n[0];
*TemperatureUP_B = p_rf_calibrate_info->delta_swing_table_idx_5gb_p[0];
*TemperatureDOWN_B = p_rf_calibrate_info->delta_swing_table_idx_5gb_n[0];
} else if ( 100 <= channel && channel <= 140) {
*TemperatureUP_A = p_rf_calibrate_info->delta_swing_table_idx_5ga_p[1];
*TemperatureDOWN_A = p_rf_calibrate_info->delta_swing_table_idx_5ga_n[1];
*TemperatureUP_B = p_rf_calibrate_info->delta_swing_table_idx_5gb_p[1];
*TemperatureDOWN_B = p_rf_calibrate_info->delta_swing_table_idx_5gb_n[1];
} else if ( 149 <= channel && channel <= 173) {
*TemperatureUP_A = p_rf_calibrate_info->delta_swing_table_idx_5ga_p[2];
*TemperatureDOWN_A = p_rf_calibrate_info->delta_swing_table_idx_5ga_n[2];
*TemperatureUP_B = p_rf_calibrate_info->delta_swing_table_idx_5gb_p[2];
*TemperatureDOWN_B = p_rf_calibrate_info->delta_swing_table_idx_5gb_n[2];
} else {
*TemperatureUP_A = (u8*)delta_swing_table_idx_2ga_p_8188e;
*TemperatureDOWN_A = (u8*)delta_swing_table_idx_2ga_n_8188e;
*TemperatureUP_B = (u8*)delta_swing_table_idx_2ga_p_8188e;
*TemperatureDOWN_B = (u8*)delta_swing_table_idx_2ga_n_8188e;
}
return;
}
void configure_txpower_track_8821a(
struct _TXPWRTRACK_CFG *p_config
)
{
p_config->swing_table_size_cck = TXSCALE_TABLE_SIZE;
p_config->swing_table_size_ofdm = TXSCALE_TABLE_SIZE;
p_config->threshold_iqk = IQK_THRESHOLD;
p_config->average_thermal_num = AVG_THERMAL_NUM_8812A;
p_config->rf_path_count = MAX_PATH_NUM_8821A;
p_config->thermal_reg_addr = RF_T_METER_8812A;
p_config->odm_tx_pwr_track_set_pwr = odm_tx_pwr_track_set_pwr8821a;
p_config->do_iqk = do_iqk_8821a;
p_config->phy_lc_calibrate = phy_lc_calibrate_8821a;
p_config->get_delta_swing_table = get_delta_swing_table_8821a;
}
#define DP_BB_REG_NUM 7
#define DP_RF_REG_NUM 1
#define DP_RETRY_LIMIT 10
#define DP_PATH_NUM 2
#define DP_DPK_NUM 3
#define DP_DPK_VALUE_NUM 2
void phy_lc_calibrate_8821a(
void* p_dm_void
)
{
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
u8 StartTime;
u8 ProgressingTime;
StartTime = odm_get_current_time( p_dm_odm);
phy_lc_calibrate_8812a(p_dm_odm);
ProgressingTime = odm_get_progressing_time( p_dm_odm, StartTime);
ODM_RT_TRACE(p_dm_odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK ProgressingTime = %d\n", ProgressingTime));
}

49
hal/phydm/rtl8821a/halphyrf_8821a_ce.h 100644
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HAL_PHY_RF_8821A_H__
#define __HAL_PHY_RF_8821A_H__
/*--------------------------Define Parameters-------------------------------*/
void configure_txpower_track_8821a(
struct _TXPWRTRACK_CFG *p_config
);
void odm_tx_pwr_track_set_pwr_8821a(
void* pDM_VOID,
enum pwrtrack_method Method,
u8 RFPath,
u8 ChannelMappedIndex
);
void phy_lc_calibrate_8821a(
void* pDM_VOID
);
void get_delta_swing_table_8821a(
void* pDM_VOID,
u8* *TemperatureUP_A,
u8* *TemperatureDOWN_A,
u8* *TemperatureUP_B,
u8* *TemperatureDOWN_B
);
#endif // #ifndef __HAL_PHY_RF_8821A_H__

879
hal/phydm/rtl8821a/phydm_iqk_8821a_ce.c 100644
View File

@ -0,0 +1,879 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#include "mp_precomp.h"
#include "../phydm_precomp.h"
/*---------------------------Define Local Constant---------------------------*/
#define cal_num_8821A 3
#define MACBB_REG_NUM_8821A 8
#define AFE_REG_NUM_8821A 4
#define RF_REG_NUM_8821A 3
/*---------------------------Define Local Constant---------------------------*/
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
void do_iqk_8821a(
void* p_dm_void,
u8 DeltaThermalIndex,
u8 ThermalValue,
u8 Threshold
)
{
struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
p_dm_odm->rf_calibrate_info.thermal_value_iqk= ThermalValue;
phy_iq_calibrate_8821a(p_dm_odm, false);
}
#endif
void _IQK_RX_FillIQC_8821A(
struct PHY_DM_STRUCT *p_dm_odm,
u1Byte Path,
unsigned int RX_X,
unsigned int RX_Y
)
{
switch (Path) {
case ODM_RF_PATH_A:
{
odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C
odm_set_bb_reg(p_dm_odm, 0xc10, 0x000003ff, RX_X>>1);
odm_set_bb_reg(p_dm_odm, 0xc10, 0x03ff0000, (RX_Y>>1) & 0x000003ff);
ODM_RT_TRACE(p_dm_odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X = %x;;RX_Y = %x ====>fill to IQC\n", RX_X>>1, RX_Y>>1));
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xc10 = %x ====>fill to IQC\n", odm_read_4byte(p_dm_odm, 0xc10)));
}
break;
default:
break;
};
}
void _IQK_TX_FillIQC_8821A(
struct PHY_DM_STRUCT *p_dm_odm,
u1Byte Path,
unsigned int TX_X,
unsigned int TX_Y
)
{
switch (Path) {
case ODM_RF_PATH_A:
{
odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1
odm_write_4byte(p_dm_odm, 0xc90, 0x00000080);
odm_write_4byte(p_dm_odm, 0xcc4, 0x20040000);
odm_write_4byte(p_dm_odm, 0xcc8, 0x20000000);
odm_set_bb_reg(p_dm_odm, 0xccc, 0x000007ff, TX_Y);
odm_set_bb_reg(p_dm_odm, 0xcd4, 0x000007ff, TX_X);
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX_X = %x;;TX_Y = %x =====> fill to IQC\n", TX_X, TX_Y));
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xcd4 = %x;;0xccc = %x ====>fill to IQC\n", odm_get_bb_reg(p_dm_odm, 0xcd4, 0x000007ff), odm_get_bb_reg(p_dm_odm, 0xccc, 0x000007ff)));
}
break;
default:
break;
};
}
void _IQK_BackupMacBB_8821A(
struct PHY_DM_STRUCT *p_dm_odm,
u32* MACBB_backup,
u32* Backup_MACBB_REG,
u32 MACBB_NUM
)
{
u32 i;
odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C
//save MACBB default value
for (i = 0; i < MACBB_NUM; i++){
MACBB_backup[i] = odm_read_4byte(p_dm_odm, Backup_MACBB_REG[i]);
}
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupMacBB Success!!!!\n"));
}
void _IQK_BackupRF_8821A(
struct PHY_DM_STRUCT *p_dm_odm,
u32* RFA_backup,
u32* RFB_backup,
u32* Backup_RF_REG,
u32 RF_NUM
)
{
u32 i;
odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C
//Save RF Parameters
for (i = 0; i < RF_NUM; i++){
RFA_backup[i] = odm_get_rf_reg(p_dm_odm, ODM_RF_PATH_A, Backup_RF_REG[i], bMaskDWord);
}
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupRF Success!!!!\n"));
}
void _IQK_BackupAFE_8821A(
struct PHY_DM_STRUCT *p_dm_odm,
u32* AFE_backup,
u32* Backup_AFE_REG,
u32 AFE_NUM
)
{
u32 i;
odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C
//Save AFE Parameters
for (i = 0; i < AFE_NUM; i++){
AFE_backup[i] = odm_read_4byte(p_dm_odm, Backup_AFE_REG[i]);
}
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupAFE Success!!!!\n"));
}
void _IQK_RestoreMacBB_8821A(
struct PHY_DM_STRUCT *p_dm_odm,
u32* MACBB_backup,
u32* Backup_MACBB_REG,
u32 MACBB_NUM
)
{
u32 i;
odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C
//Reload MacBB Parameters
for (i = 0; i < MACBB_NUM; i++){
odm_write_4byte(p_dm_odm, Backup_MACBB_REG[i], MACBB_backup[i]);
}
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreMacBB Success!!!!\n"));
}
void _IQK_RestoreRF_8821A(
struct PHY_DM_STRUCT *p_dm_odm,
u1Byte Path,
u32* Backup_RF_REG,
u32* RF_backup,
u32 RF_REG_NUM
)
{
u32 i;
odm_set_bb_reg(p_dm_odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C
for (i = 0; i < RF_REG_NUM; i++)
odm_set_rf_reg(p_dm_odm, Path, Backup_RF_REG[i], bRFRegOffsetMask, RF_backup[i]);
switch(Path){
case ODM_RF_PATH_A:
{
ODM_RT_TRACE(p_dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreRF Path A Success!!!!\n"));
}
break;
default:
break;
}
}
void _IQK_RestoreAFE_8821A(
struct PHY_DM_STRUCT *pDM_Odm,
u32* AFE_backup,
u32* Backup_AFE_REG,
u32 AFE_NUM
)
{
u32 i;
odm_set_bb_reg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C
//Reload AFE Parameters
for (i = 0; i < AFE_NUM; i++){
odm_write_4byte(pDM_Odm, Backup_AFE_REG[i], AFE_backup[i]);
}
odm_set_bb_reg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1
odm_write_4byte(pDM_Odm, 0xc80, 0x0);
odm_write_4byte(pDM_Odm, 0xc84, 0x0);
odm_write_4byte(pDM_Odm, 0xc88, 0x0);
odm_write_4byte(pDM_Odm, 0xc8c, 0x3c000000);
odm_write_4byte(pDM_Odm, 0xc90, 0x00000080);
odm_write_4byte(pDM_Odm, 0xc94, 0x00000000);
odm_write_4byte(pDM_Odm, 0xcc4, 0x20040000);
odm_write_4byte(pDM_Odm, 0xcc8, 0x20000000);
odm_write_4byte(pDM_Odm, 0xcb8, 0x0);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreAFE Success!!!!\n"));
}
void _IQK_ConfigureMAC_8821A(
struct PHY_DM_STRUCT *pDM_Odm
)
{
// ========MAC register setting========
odm_set_bb_reg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C
odm_write_1byte(pDM_Odm, 0x522, 0x3f);
odm_set_bb_reg(pDM_Odm, 0x550, BIT(11)|BIT(3), 0x0);
odm_write_1byte(pDM_Odm, 0x808, 0x00); // RX ante off
odm_set_bb_reg(pDM_Odm, 0x838, 0xf, 0xc); // CCA off
odm_write_1byte(pDM_Odm, 0xa07, 0xf); // CCK RX Path off
}
void _IQK_Tx_8821A(
struct PHY_DM_STRUCT *pDM_Odm,
u1Byte Path
)
{
u8 TX_fail, RX_fail, delay_count, IQK_ready, cal_retry, cal = 0;
int TX_X = 0, TX_Y = 0, RX_X = 0, RX_Y = 0, TX_Average = 0, RX_Average = 0, RXIQK_Loop = 0, RX_X_temp = 0, RX_Y_temp = 0;
int TX_X0[cal_num_8821A], TX_Y0[cal_num_8821A], RX_X0[2][cal_num_8821A], RX_Y0[2][cal_num_8821A];
boolean TX0IQKOK = FALSE, RX0IQKOK = FALSE;
boolean VDF_enable = FALSE;
int i, k, VDF_Y[3], VDF_X[3], Tx_dt[3], ii, dx = 0, dy = 0, TX_finish = 0, RX_finish1 = 0, RX_finish2 = 0;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BandWidth = %d, SupportInterface = %d, ExtPA = %d, ext_pa_5g = %d\n", *pDM_Odm->p_band_width, pDM_Odm->support_interface, pDM_Odm->ext_pa, pDM_Odm->ext_pa_5g));
if (*pDM_Odm->p_band_width == 2){
VDF_enable = TRUE;
}
while (cal < cal_num_8821A){
switch (Path) {
case ODM_RF_PATH_A:
{
//Path-A LOK
odm_set_bb_reg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C
// ========Path-A AFE all on========
// Port 0 DAC/ADC on
odm_write_4byte(pDM_Odm, 0xc60, 0x77777777);
odm_write_4byte(pDM_Odm, 0xc64, 0x77777777);
odm_write_4byte(pDM_Odm, 0xc68, 0x19791979);
odm_set_bb_reg(pDM_Odm, 0xc00, 0xf, 0x4);// hardware 3-wire off
// LOK Setting
//====== LOK ======
// 1. DAC/ADC sampling rate (160 MHz)
odm_set_bb_reg(pDM_Odm, 0xc5c, BIT(26)|BIT(25)|BIT(24), 0x7);
// 2. LoK RF Setting (at BW = 20M)
odm_set_rf_reg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x80002);
odm_set_rf_reg(pDM_Odm, Path, 0x18, 0x00c00, 0x3); // BW 20M
odm_set_rf_reg(pDM_Odm, Path, 0x30, bRFRegOffsetMask, 0x20000);
odm_set_rf_reg(pDM_Odm, Path, 0x31, bRFRegOffsetMask, 0x0003f);
odm_set_rf_reg(pDM_Odm, Path, 0x32, bRFRegOffsetMask, 0xf3fc3);
odm_set_rf_reg(pDM_Odm, Path, 0x65, bRFRegOffsetMask, 0x931d5);
odm_set_rf_reg(pDM_Odm, Path, 0x8f, bRFRegOffsetMask, 0x8a001);
odm_write_4byte(pDM_Odm, 0x90c, 0x00008000);
odm_set_bb_reg(pDM_Odm, 0xc94, BIT(0), 0x1);
odm_write_4byte(pDM_Odm, 0x978, 0x29002000);// TX (X,Y)
odm_write_4byte(pDM_Odm, 0x97c, 0xa9002000);// RX (X,Y)
odm_write_4byte(pDM_Odm, 0x984, 0x00462910);// [0]:AGC_en, [15]:idac_K_Mask
odm_set_bb_reg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1
if (pDM_Odm->ext_pa_5g)
odm_write_4byte(pDM_Odm, 0xc88, 0x821403f7);
else
odm_write_4byte(pDM_Odm, 0xc88, 0x821403f4);
if (*pDM_Odm->p_band_type)
odm_write_4byte(pDM_Odm, 0xc8c, 0x68163e96);
else
odm_write_4byte(pDM_Odm, 0xc8c, 0x28163e96);
odm_write_4byte(pDM_Odm, 0xc80, 0x18008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16
odm_write_4byte(pDM_Odm, 0xc84, 0x38008c10);// RX_Tone_idx[9:0], RxK_Mask[29]
odm_write_4byte(pDM_Odm, 0xcb8, 0x00100000);// cb8[20] iqk_dpk module
odm_write_4byte(pDM_Odm, 0x980, 0xfa000000);
odm_write_4byte(pDM_Odm, 0x980, 0xf8000000);
ODM_delay_ms(10); //Delay 10ms
odm_write_4byte(pDM_Odm, 0xcb8, 0x00000000);
odm_set_bb_reg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C
odm_set_rf_reg(pDM_Odm, Path, 0x58, 0x7fe00, odm_get_rf_reg(pDM_Odm, Path, 0x8, 0xffc00)); // Load LOK
switch (*pDM_Odm->p_band_width)
{
case 1:
{
odm_set_rf_reg(pDM_Odm, Path, 0x18, 0x00c00, 0x1);
}
break;
case 2:
{
odm_set_rf_reg(pDM_Odm, Path, 0x18, 0x00c00, 0x0);
}
break;
default:
break;
}
odm_set_bb_reg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1
// 3. TX RF Setting
odm_set_bb_reg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C
odm_set_rf_reg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x80000);
odm_set_rf_reg(pDM_Odm, Path, 0x30, bRFRegOffsetMask, 0x20000);
odm_set_rf_reg(pDM_Odm, Path, 0x31, bRFRegOffsetMask, 0x0003f);
odm_set_rf_reg(pDM_Odm, Path, 0x32, bRFRegOffsetMask, 0xf3fc3);
odm_set_rf_reg(pDM_Odm, Path, 0x65, bRFRegOffsetMask, 0x931d5);
odm_set_rf_reg(pDM_Odm, Path, 0x8f, bRFRegOffsetMask, 0x8a001);
odm_set_rf_reg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x00000);
odm_write_4byte(pDM_Odm, 0x90c, 0x00008000);
odm_set_bb_reg(pDM_Odm, 0xc94, BIT(0), 0x1);
odm_write_4byte(pDM_Odm, 0x978, 0x29002000);// TX (X,Y)
odm_write_4byte(pDM_Odm, 0x97c, 0xa9002000);// RX (X,Y)
odm_write_4byte(pDM_Odm, 0x984, 0x0046a910);// [0]:AGC_en, [15]:idac_K_Mask
odm_set_bb_reg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1
if (pDM_Odm->ext_pa_5g)
odm_write_4byte(pDM_Odm, 0xc88, 0x821403f7);
else
odm_write_4byte(pDM_Odm, 0xc88, 0x821403e3);
if (*pDM_Odm->p_band_type)
odm_write_4byte(pDM_Odm, 0xc8c, 0x40163e96);
else
odm_write_4byte(pDM_Odm, 0xc8c, 0x00163e96);
if (VDF_enable == 1){
for (k = 0;k <= 2; k++){
switch (k){
case 0:
{
odm_write_4byte(pDM_Odm, 0xc80, 0x18008c38);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16
odm_write_4byte(pDM_Odm, 0xc84, 0x38008c38);// RX_Tone_idx[9:0], RxK_Mask[29]
odm_set_bb_reg(pDM_Odm, 0xce8, BIT(31), 0x0);
}
break;
case 1:
{
odm_set_bb_reg(pDM_Odm, 0xc80, BIT(28), 0x0);
odm_set_bb_reg(pDM_Odm, 0xc84, BIT(28), 0x0);
odm_set_bb_reg(pDM_Odm, 0xce8, BIT(31), 0x0);
}
break;
case 2:
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("VDF_Y[1] = %x;;;VDF_Y[0] = %x\n", VDF_Y[1]>>21 & 0x00007ff, VDF_Y[0]>>21 & 0x00007ff));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("VDF_X[1] = %x;;;VDF_X[0] = %x\n", VDF_X[1]>>21 & 0x00007ff, VDF_X[0]>>21 & 0x00007ff));
Tx_dt[cal] = (VDF_Y[1]>>20)-(VDF_Y[0]>>20);
Tx_dt[cal] = ((16*Tx_dt[cal])*10000/15708);
Tx_dt[cal] = (Tx_dt[cal] >> 1 )+(Tx_dt[cal] & BIT(0));
odm_write_4byte(pDM_Odm, 0xc80, 0x18008c20);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16
odm_write_4byte(pDM_Odm, 0xc84, 0x38008c20);// RX_Tone_idx[9:0], RxK_Mask[29]
odm_set_bb_reg(pDM_Odm, 0xce8, BIT(31), 0x1);
odm_set_bb_reg(pDM_Odm, 0xce8, 0x3fff0000, Tx_dt[cal] & 0x00003fff);
}
break;
}
odm_write_4byte(pDM_Odm, 0xcb8, 0x00100000);// cb8[20] iqk_dpk module
cal_retry = 0;
while(1){
// one shot
odm_write_4byte(pDM_Odm, 0x980, 0xfa000000);
odm_write_4byte(pDM_Odm, 0x980, 0xf8000000);
ODM_delay_ms(10); //Delay 10ms
odm_write_4byte(pDM_Odm, 0xcb8, 0x00000000);
delay_count = 0;
while (1){
IQK_ready = odm_get_bb_reg(pDM_Odm, 0xd00, BIT(10));
if ((~IQK_ready) || (delay_count>20)){
break;
}
else{
ODM_delay_ms(1);
delay_count++;
}
}
if (delay_count < 20){ // If 20ms No Result, then cal_retry++
// ============TXIQK Check==============
TX_fail = odm_get_bb_reg(pDM_Odm, 0xd00, BIT(12));
if (~TX_fail){
odm_write_4byte(pDM_Odm, 0xcb8, 0x02000000);
VDF_X[k] = odm_get_bb_reg(pDM_Odm, 0xd00, 0x07ff0000)<<21;
odm_write_4byte(pDM_Odm, 0xcb8, 0x04000000);
VDF_Y[k] = odm_get_bb_reg(pDM_Odm, 0xd00, 0x07ff0000)<<21;
TX0IQKOK = TRUE;
break;
}
else{
odm_set_bb_reg(pDM_Odm, 0xccc, 0x000007ff, 0x0);
odm_set_bb_reg(pDM_Odm, 0xcd4, 0x000007ff, 0x200);
TX0IQKOK = FALSE;
cal_retry++;
if (cal_retry == 10) {
break;
}
}
}
else{
TX0IQKOK = FALSE;
cal_retry++;
if (cal_retry == 10){
break;
}
}
}
}
if (k == 3){
TX_X0[cal] = VDF_X[k-1] ;
TX_Y0[cal] = VDF_Y[k-1];
}
}
else{
odm_write_4byte(pDM_Odm, 0xc80, 0x18008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16
odm_write_4byte(pDM_Odm, 0xc84, 0x38008c10);// RX_Tone_idx[9:0], RxK_Mask[29]
odm_write_4byte(pDM_Odm, 0xcb8, 0x00100000);// cb8[20] iqk_dpk module
cal_retry = 0;
while(1){
// one shot
odm_write_4byte(pDM_Odm, 0x980, 0xfa000000);
odm_write_4byte(pDM_Odm, 0x980, 0xf8000000);
ODM_delay_ms(10); //Delay 10ms
odm_write_4byte(pDM_Odm, 0xcb8, 0x00000000);
delay_count = 0;
while (1){
IQK_ready = odm_get_bb_reg(pDM_Odm, 0xd00, BIT(10));
if ((~IQK_ready) || (delay_count>20)) {
break;
}
else{
ODM_delay_ms(1);
delay_count++;
}
}
if (delay_count < 20){ // If 20ms No Result, then cal_retry++
// ============TXIQK Check==============
TX_fail = odm_get_bb_reg(pDM_Odm, 0xd00, BIT(12));
if (~TX_fail){
odm_write_4byte(pDM_Odm, 0xcb8, 0x02000000);
TX_X0[cal] = odm_get_bb_reg(pDM_Odm, 0xd00, 0x07ff0000)<<21;
odm_write_4byte(pDM_Odm, 0xcb8, 0x04000000);
TX_Y0[cal] = odm_get_bb_reg(pDM_Odm, 0xd00, 0x07ff0000)<<21;
TX0IQKOK = TRUE;
break;
}
else{
odm_set_bb_reg(pDM_Odm, 0xccc, 0x000007ff, 0x0);
odm_set_bb_reg(pDM_Odm, 0xcd4, 0x000007ff, 0x200);
TX0IQKOK = FALSE;
cal_retry++;
if (cal_retry == 10) {
break;
}
}
}
else{
TX0IQKOK = FALSE;
cal_retry++;
if (cal_retry == 10)
break;
}
}
}
if (TX0IQKOK == FALSE)
break; // TXK fail, Don't do RXK
//====== RX IQK ======
odm_set_bb_reg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C
// 1. RX RF Setting
odm_set_rf_reg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x80000);
odm_set_rf_reg(pDM_Odm, Path, 0x30, bRFRegOffsetMask, 0x30000);
odm_set_rf_reg(pDM_Odm, Path, 0x31, bRFRegOffsetMask, 0x0002f);
odm_set_rf_reg(pDM_Odm, Path, 0x32, bRFRegOffsetMask, 0xfffbb);
odm_set_rf_reg(pDM_Odm, Path, 0x8f, bRFRegOffsetMask, 0x88001);
odm_set_rf_reg(pDM_Odm, Path, 0x65, bRFRegOffsetMask, 0x931d8);
odm_set_rf_reg(pDM_Odm, Path, 0xef, bRFRegOffsetMask, 0x00000);
odm_set_bb_reg(pDM_Odm, 0x978, 0x03FF8000, (TX_X0[cal])>>21&0x000007ff);
odm_set_bb_reg(pDM_Odm, 0x978, 0x000007FF, (TX_Y0[cal])>>21&0x000007ff);
odm_set_bb_reg(pDM_Odm, 0x978, BIT(31), 0x1);
odm_set_bb_reg(pDM_Odm, 0x97c, BIT(31), 0x0);
odm_write_4byte(pDM_Odm, 0x90c, 0x00008000);
odm_write_4byte(pDM_Odm, 0x984, 0x0046a911);
odm_set_bb_reg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1
odm_write_4byte(pDM_Odm, 0xc80, 0x38008c10);// TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16
odm_write_4byte(pDM_Odm, 0xc84, 0x18008c10);// RX_Tone_idx[9:0], RxK_Mask[29]
odm_write_4byte(pDM_Odm, 0xc88, 0x02140119);
if (pDM_Odm->support_interface == 1){
RXIQK_Loop = 2; // for 2% fail;
}
else{
RXIQK_Loop = 1;
}
for(i = 0; i < RXIQK_Loop; i++){
if (pDM_Odm->support_interface == 1)
if(i == 0)
odm_write_4byte(pDM_Odm, 0xc8c, 0x28161100); //Good
else
odm_write_4byte(pDM_Odm, 0xc8c, 0x28160d00);
else
odm_write_4byte(pDM_Odm, 0xc8c, 0x28160d00);
odm_write_4byte(pDM_Odm, 0xcb8, 0x00100000);// cb8[20] iqk_dpk module
cal_retry = 0;
while(1){
// one shot
odm_write_4byte(pDM_Odm, 0x980, 0xfa000000);
odm_write_4byte(pDM_Odm, 0x980, 0xf8000000);
ODM_delay_ms(10); //Delay 10ms
odm_write_4byte(pDM_Odm, 0xcb8, 0x00000000);
delay_count = 0;
while (1){
IQK_ready = odm_get_bb_reg(pDM_Odm, 0xd00, BIT(10));
if ((~IQK_ready)||(delay_count>20)){
break;
}
else{
ODM_delay_ms(1);
delay_count++;
}
}
if (delay_count < 20){ // If 20ms No Result, then cal_retry++
// ============RXIQK Check==============
RX_fail = odm_get_bb_reg(pDM_Odm, 0xd00, BIT(11));
if (RX_fail == 0){
/*
DbgPrint("====== RXIQK (%d) ======", i);
odm_write_4byte(pDM_Odm, 0xcb8, 0x05000000);
reg1 = odm_get_bb_reg(pDM_Odm, 0xd00, 0xffffffff);
odm_write_4byte(pDM_Odm, 0xcb8, 0x06000000);
reg2 = odm_get_bb_reg(pDM_Odm, 0xd00, 0x0000001f);
DbgPrint("reg1 = %d, reg2 = %d", reg1, reg2);
Image_Power = (reg2<<32)+reg1;
DbgPrint("Before PW = %d\n", Image_Power);
odm_write_4byte(pDM_Odm, 0xcb8, 0x07000000);
reg1 = odm_get_bb_reg(pDM_Odm, 0xd00, 0xffffffff);
odm_write_4byte(pDM_Odm, 0xcb8, 0x08000000);
reg2 = odm_get_bb_reg(pDM_Odm, 0xd00, 0x0000001f);
Image_Power = (reg2<<32)+reg1;
DbgPrint("After PW = %d\n", Image_Power);
*/
odm_write_4byte(pDM_Odm, 0xcb8, 0x06000000);
RX_X0[i][cal] = odm_get_bb_reg(pDM_Odm, 0xd00, 0x07ff0000)<<21;
odm_write_4byte(pDM_Odm, 0xcb8, 0x08000000);
RX_Y0[i][cal] = odm_get_bb_reg(pDM_Odm, 0xd00, 0x07ff0000)<<21;
RX0IQKOK = TRUE;
break;
}
else{
odm_set_bb_reg(pDM_Odm, 0xc10, 0x000003ff, 0x200>>1);
odm_set_bb_reg(pDM_Odm, 0xc10, 0x03ff0000, 0x0>>1);
RX0IQKOK = FALSE;
cal_retry++;
if (cal_retry == 10)
break;
}
}
else{
RX0IQKOK = FALSE;
cal_retry++;
if (cal_retry == 10)
break;
}
}
}
if (TX0IQKOK)
TX_Average++;
if (RX0IQKOK)
RX_Average++;
}
break;
default:
break;
}
cal++;
}
// FillIQK Result
switch (Path){
case ODM_RF_PATH_A:
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("========Path_A =======\n"));
if (TX_Average == 0)
break;
for (i = 0; i < TX_Average; i++){
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("TX_X0[%d] = %x ;; TX_Y0[%d] = %x\n", i, (TX_X0[i])>>21&0x000007ff, i, (TX_Y0[i])>>21&0x000007ff));
}
for (i = 0; i < TX_Average; i++){
for (ii = i+1; ii <TX_Average; ii++){
dx = (TX_X0[i]>>21) - (TX_X0[ii]>>21);
if (dx < 3 && dx > -3){
dy = (TX_Y0[i]>>21) - (TX_Y0[ii]>>21);
if (dy < 3 && dy > -3){
TX_X = ((TX_X0[i]>>21) + (TX_X0[ii]>>21))/2;
TX_Y = ((TX_Y0[i]>>21) + (TX_Y0[ii]>>21))/2;
TX_finish = 1;
break;
}
}
}
if (TX_finish == 1)
break;
}
if (TX_finish == 1){
_IQK_TX_FillIQC_8821A(pDM_Odm, Path, TX_X, TX_Y);
}
else{
_IQK_TX_FillIQC_8821A(pDM_Odm, Path, 0x200, 0x0);
}
if (RX_Average == 0)
break;
for (i = 0; i < RX_Average; i++){
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X0[0][%d] = %x ;; RX_Y0[0][%d] = %x\n", i, (RX_X0[0][i])>>21&0x000007ff, i, (RX_Y0[0][i])>>21&0x000007ff));
if (RXIQK_Loop == 2) {
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RX_X0[1][%d] = %x ;; RX_Y0[1][%d] = %x\n", i, (RX_X0[1][i])>>21&0x000007ff, i, (RX_Y0[1][i])>>21&0x000007ff));
}
}
for (i = 0; i < RX_Average; i++){
for (ii = i+1; ii <RX_Average; ii++){
dx = (RX_X0[0][i]>>21) - (RX_X0[0][ii]>>21);
if (dx < 4 && dx > -4){
dy = (RX_Y0[0][i]>>21) - (RX_Y0[0][ii]>>21);
if (dy < 4 && dy > -4){
RX_X_temp = ((RX_X0[0][i]>>21) + (RX_X0[0][ii]>>21))/2;
RX_Y_temp = ((RX_Y0[0][i]>>21) + (RX_Y0[0][ii]>>21))/2;
RX_finish1 = 1;
break;
}
}
}
if (RX_finish1 == 1){
RX_X = RX_X_temp;
RX_Y = RX_Y_temp;
break;
}
}
if(RXIQK_Loop == 2){
for (i = 0; i < RX_Average; i++){
for (ii = i+1; ii <RX_Average; ii++){
dx = (RX_X0[1][i]>>21) - (RX_X0[1][ii]>>21);
if (dx < 4 && dx > -4){
dy = (RX_Y0[1][i]>>21) - (RX_Y0[1][ii]>>21);
if (dy < 4 && dy > -4){
RX_X = ((RX_X0[1][i]>>21) + (RX_X0[1][ii]>>21))/2;
RX_Y = ((RX_Y0[1][i]>>21) + (RX_Y0[1][ii]>>21))/2;
RX_finish2 = 1;
break;
}
}
}
if (RX_finish2 == 1)
break;
}
if(RX_finish1 && RX_finish2){
RX_X = (RX_X+RX_X_temp)/2;
RX_Y = (RX_Y+RX_Y_temp)/2;
}
}
if (RX_finish1 || RX_finish2){
_IQK_RX_FillIQC_8821A(pDM_Odm, Path, RX_X, RX_Y);
}
else{
_IQK_RX_FillIQC_8821A(pDM_Odm, Path, 0x200, 0x0);
}
}
break;
default:
break;
}
}
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
void phy_iq_calibrate_by_fw_8821a(
struct PHY_DM_STRUCT *pDM_Odm
)
{
u1Byte IQKcmd[3] = {*pDM_Odm->p_channel, 0x0, 0x0};
u1Byte Buf1 = 0x0;
u1Byte Buf2 = 0x0;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("pChannel: %d \n", *pDM_Odm->p_channel));
//Byte 2, Bit 4 ~ Bit 5 : BandType
if(*pDM_Odm->p_band_type) {
Buf1 = 0x2<<4;
} else {
Buf1 = 0x1<<4;
}
//Byte 2, Bit 0 ~ Bit 3 : Bandwidth
if(*pDM_Odm->p_band_width == ODM_BW20M) {
Buf2 = 0x1;
} else if(*pDM_Odm->p_band_width == ODM_BW40M) {
Buf2 = 0x1<<1;
} else if(*pDM_Odm->p_band_width == ODM_BW80M) {
Buf2 = 0x1<<2;
} else {
Buf2 = 0x1<<3;
}
IQKcmd[1] = Buf1 | Buf2;
IQKcmd[2] = pDM_Odm->ext_pa_5g | pDM_Odm->ext_lna_5g<<1;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== FW IQK Start ==\n"));
pDM_Odm->rf_calibrate_info.iqk_start_time = 0;
pDM_Odm->rf_calibrate_info.iqk_start_time = odm_get_current_time( pDM_Odm);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== StartTime: %lld\n", pDM_Odm->rf_calibrate_info.iqk_start_time));
odm_fill_h2c_cmd(pDM_Odm, ODM_H2C_IQ_CALIBRATION, 3, IQKcmd);
}
#endif
void _phy_iq_calibrate_8821a(
struct PHY_DM_STRUCT *pDM_Odm
)
{
u4Byte MACBB_backup[MACBB_REG_NUM_8821A], AFE_backup[AFE_REG_NUM_8821A], RFA_backup[RF_REG_NUM_8821A], RFB_backup[RF_REG_NUM_8821A];
u4Byte Backup_MACBB_REG[MACBB_REG_NUM_8821A] = {0x520, 0x550, 0x808, 0xa04, 0x90c, 0xc00, 0x838, 0x82c};
u4Byte Backup_AFE_REG[AFE_REG_NUM_8821A] = {0xc5c, 0xc60, 0xc64, 0xc68};
u4Byte Backup_RF_REG[RF_REG_NUM_8821A] = {0x65, 0x8f, 0x0};
_IQK_BackupMacBB_8821A(pDM_Odm, MACBB_backup, Backup_MACBB_REG, MACBB_REG_NUM_8821A);
_IQK_BackupAFE_8821A(pDM_Odm, AFE_backup, Backup_AFE_REG, AFE_REG_NUM_8821A);
_IQK_BackupRF_8821A(pDM_Odm, RFA_backup, RFB_backup, Backup_RF_REG, RF_REG_NUM_8821A);
_IQK_ConfigureMAC_8821A(pDM_Odm);
_IQK_Tx_8821A(pDM_Odm, ODM_RF_PATH_A);
_IQK_RestoreRF_8821A(pDM_Odm, ODM_RF_PATH_A, Backup_RF_REG, RFA_backup, RF_REG_NUM_8821A);
_IQK_RestoreAFE_8821A(pDM_Odm, AFE_backup, Backup_AFE_REG, AFE_REG_NUM_8821A);
_IQK_RestoreMacBB_8821A(pDM_Odm, MACBB_backup, Backup_MACBB_REG, MACBB_REG_NUM_8821A);
}
void phy_reset_iqk_result_8821a(
struct PHY_DM_STRUCT *pDM_Odm
)
{
odm_set_bb_reg(pDM_Odm, 0x82c, BIT(31), 0x1); // [31] = 1 --> Page C1
odm_set_bb_reg(pDM_Odm, 0xccc, 0x000007ff, 0x0);
odm_set_bb_reg(pDM_Odm, 0xcd4, 0x000007ff, 0x200);
odm_write_4byte(pDM_Odm, 0xce8, 0x0);
odm_set_bb_reg(pDM_Odm, 0x82c, BIT(31), 0x0); // [31] = 0 --> Page C
odm_set_bb_reg(pDM_Odm, 0xc10, 0x000003ff, 0x100);
}
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
void phy_iq_calibrate_8821a(
struct PHY_DM_STRUCT *pDM_Odm,
boolean bReCovery
)
{
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
struct _ADAPTER *pAdapter = pDM_Odm->adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
u4Byte counter = 0;
#endif
#endif
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN )
if (odm_check_power_status(pAdapter) == FALSE)
return;
#endif
if (*(pDM_Odm->p_mp_mode)){ //(MP_DRIVER == 1)
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#if (MP_DRIVER == 1)
PMPT_CONTEXT pMptCtx = &(pAdapter->mpt_ctx);
if( pMptCtx->is_single_tone || pMptCtx->is_carrier_suppression)
return;
#endif
#else// (DM_ODM_SUPPORT_TYPE == ODM_CE)
PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
if( pMptCtx->is_single_tone || pMptCtx->is_carrier_suppression)
return;
#endif
}
pDM_Odm->iqk_fw_offload = 0;
//3 == FW IQK ==
if(pDM_Odm->iqk_fw_offload)
{
if ( ! pDM_Odm->rf_calibrate_info.is_iqk_in_progress)
{
odm_acquire_spin_lock( pDM_Odm, RT_IQK_SPINLOCK);
pDM_Odm->rf_calibrate_info.is_iqk_in_progress = true;
odm_release_spin_lock( pDM_Odm, RT_IQK_SPINLOCK);
phy_iq_calibrate_by_fw_8821a(pDM_Odm);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
for(counter = 0; counter < 10; counter++){
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== FW IQK IN PROGRESS == #%d\n", counter));
ODM_delay_ms(50);
if ( ! pDM_Odm->rf_calibrate_info.is_iqk_in_progress)
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== FW IQK RETURN FROM WAITING ==\n"));
break;
}
}
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
rtl8812_iqk_wait(pAdapter, 500);
#endif
if (pDM_Odm->rf_calibrate_info.is_iqk_in_progress)
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== FW IQK TIMEOUT (Still in progress after 500ms) ==\n"));
odm_acquire_spin_lock( pDM_Odm, RT_IQK_SPINLOCK);
pDM_Odm->rf_calibrate_info.is_iqk_in_progress = FALSE;
odm_release_spin_lock( pDM_Odm, RT_IQK_SPINLOCK);
}
}
else
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== Return the IQK CMD, because the IQK in Progress ==\n"));
}
}
//3 == Driver IQK ==
else {
if ( ! pDM_Odm->rf_calibrate_info.is_iqk_in_progress) {
odm_acquire_spin_lock(pDM_Odm, RT_IQK_SPINLOCK);
pDM_Odm->rf_calibrate_info.is_iqk_in_progress = TRUE;
odm_release_spin_lock(pDM_Odm, RT_IQK_SPINLOCK);
pDM_Odm->rf_calibrate_info.iqk_start_time = odm_get_current_time( pDM_Odm);
_phy_iq_calibrate_8821a(pDM_Odm);
pDM_Odm->rf_calibrate_info.iqk_progressing_time = odm_get_progressing_time( pDM_Odm, pDM_Odm->rf_calibrate_info.iqk_start_time);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK ProgressingTime = %lld ms\n", pDM_Odm->rf_calibrate_info.iqk_progressing_time));
odm_acquire_spin_lock(pDM_Odm, RT_IQK_SPINLOCK);
pDM_Odm->rf_calibrate_info.is_iqk_in_progress = FALSE;
odm_release_spin_lock(pDM_Odm, RT_IQK_SPINLOCK);
}
else
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("== Return the IQK CMD, because the IQK in Progress ==\n"));
}
}
}
#else
#endif

45
hal/phydm/rtl8821a/phydm_iqk_8821a_ce.h 100644
View File

@ -0,0 +1,45 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDM_IQK_8821A_H__
#define __PHYDM_IQK_8821A_H__
/*--------------------------Define Parameters-------------------------------*/
/*---------------------------End Define Parameters-------------------------------*/
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
void do_iqk_8821a(
void* pDM_VOID,
u8 DeltaThermalIndex,
u8 ThermalValue,
u8 Threshold
);
void phy_iq_calibrate_8821a(
struct PHY_DM_STRUCT *p_dm_odm,
boolean bReCovery
);
#else
void phy_iq_calibrate_8821a(
struct PHY_DM_STRUCT *p_dm_odm
);
#endif
#endif // #ifndef __PHYDM_IQK_8821A_H__

215
hal/phydm/rtl8821a/phydm_regconfig8821a.c 100644
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@ -0,0 +1,215 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#include "mp_precomp.h"
#include "../phydm_precomp.h"
#if (RTL8821A_SUPPORT == 1)
void odm_config_rf_reg_8821a(
struct PHY_DM_STRUCT *p_dm_odm,
u32 addr,
u32 data,
enum odm_rf_radio_path_e RF_PATH,
u32 reg_addr
)
{
if (addr == 0xfe || addr == 0xffe) {
#ifdef CONFIG_LONG_DELAY_ISSUE
ODM_sleep_ms(50);
#else
ODM_delay_ms(50);
#endif
}
else if ( addr == 0xfd)
{
ODM_delay_ms(5);
}
else if (addr == 0xfc)
{
ODM_delay_ms(1);
}
else if (addr == 0xfb)
{
ODM_delay_us(50);
}
else if (addr == 0xfa)
{
ODM_delay_us(5);
}
else if (addr == 0xf9)
{
ODM_delay_us(1);
}
else
{
odm_set_rf_reg(p_dm_odm, RF_PATH, reg_addr, RFREGOFFSETMASK, data);
// Add 1us delay between BB/RF register setting.
ODM_delay_us(1);
}
}
void
odm_config_rf_radio_a_8821a(
struct PHY_DM_STRUCT *p_dm_odm,
u32 addr,
u32 data
)
{
u32 content = 0x1000; /* RF_Content: radioa_txt */
u32 maskfor_phy_set = (u32)(content & 0xE000);
odm_config_rf_reg_8821a(p_dm_odm, addr, data, ODM_RF_PATH_A, addr | maskfor_phy_set);
ODM_RT_TRACE(p_dm_odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", addr, data));
}
void
odm_config_rf_radio_b_8821a(
struct PHY_DM_STRUCT *p_dm_odm,
u32 addr,
u32 data
)
{
u32 content = 0x1001; /* RF_Content: radiob_txt */
u32 maskfor_phy_set = (u32)(content & 0xE000);
odm_config_rf_reg_8821a(p_dm_odm, addr, data, ODM_RF_PATH_B, addr | maskfor_phy_set);
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> odm_config_rf_with_header_file: [RadioB] %08X %08X\n", addr, data));
}
void
odm_config_mac_8821a(
struct PHY_DM_STRUCT *p_dm_odm,
u32 addr,
u8 data
)
{
odm_write_1byte(p_dm_odm, addr, data);
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> odm_config_mac_with_header_file: [MAC_REG] %08X %08X\n", addr, data));
}
void
odm_config_bb_agc_8821a(
struct PHY_DM_STRUCT *p_dm_odm,
u32 addr,
u32 bitmask,
u32 data
)
{
odm_set_bb_reg(p_dm_odm, addr, bitmask, data);
/* Add 1us delay between BB/RF register setting. */
ODM_delay_us(1);
ODM_RT_TRACE(p_dm_odm, ODM_COMP_INIT, ODM_DBG_TRACE, ("===> odm_config_bb_with_header_file: [AGC_TAB] %08X %08X\n", addr, data));
}
void
odm_config_bb_phy_reg_pg_8821a(
struct PHY_DM_STRUCT *p_dm_odm,
u32 band,
u32 rf_path,
u32 tx_num,
u32 addr,
u32 bitmask,
u32 data
)
{
if (addr == 0xfe || addr == 0xffe)
#ifdef CONFIG_LONG_DELAY_ISSUE
ODM_sleep_ms(50);
#else
ODM_delay_ms(50);
#endif
else if (addr == 0xfd)
ODM_delay_ms(5);
else if (addr == 0xfc)
ODM_delay_ms(1);
else if (addr == 0xfb)
ODM_delay_us(50);
else if (addr == 0xfa)
ODM_delay_us(5);
else if (addr == 0xf9)
ODM_delay_us(1);
ODM_RT_TRACE(p_dm_odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", addr, bitmask, data));
#if !(DM_ODM_SUPPORT_TYPE&ODM_AP)
phy_store_tx_power_by_rate(p_dm_odm->adapter, band, rf_path, tx_num, addr, bitmask, data);
#endif
}
void
odm_config_bb_phy_8821a(
struct PHY_DM_STRUCT *p_dm_odm,
u32 addr,
u32 bitmask,
u32 data
)
{
if (addr == 0xfe)
#ifdef CONFIG_LONG_DELAY_ISSUE
ODM_sleep_ms(50);
#else
ODM_delay_ms(50);
#endif
else if (addr == 0xfd)
ODM_delay_ms(5);
else if (addr == 0xfc)
ODM_delay_ms(1);
else if (addr == 0xfb)
ODM_delay_us(50);
else if (addr == 0xfa)
ODM_delay_us(5);
else if (addr == 0xf9)
ODM_delay_us(1);
else if (addr == 0xa24)
p_dm_odm->rf_calibrate_info.rega24 = data;
odm_set_bb_reg(p_dm_odm, addr, bitmask, data);
// Add 1us delay between BB/RF register setting.
ODM_delay_us(1);
ODM_RT_TRACE(p_dm_odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", addr, data));
}
void
odm_config_bb_txpwr_lmt_8821a(
struct PHY_DM_STRUCT *p_dm_odm,
u8 *regulation,
u8 *band,
u8 *bandwidth,
u8 *rate_section,
u8 *rf_path,
u8 *channel,
u8 *power_limit
)
{
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
phy_set_tx_power_limit(p_dm_odm, regulation, band,
bandwidth, rate_section, rf_path, channel, power_limit);
#endif
}
#endif /* #if (RTL8821A_SUPPORT == 1)*/

95
hal/phydm/rtl8821a/phydm_regconfig8821a.h 100644
View File

@ -0,0 +1,95 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __INC_ODM_REGCONFIG_H_8821A
#define __INC_ODM_REGCONFIG_H_8821A
#if (RTL8821A_SUPPORT == 1)
void
odm_config_rf_reg_8821a(
struct PHY_DM_STRUCT *p_dm_odm,
u32 addr,
u32 data,
enum odm_rf_radio_path_e RF_PATH,
u32 reg_addr
);
void
odm_config_rf_radio_a_8821a(
struct PHY_DM_STRUCT *p_dm_odm,
u32 addr,
u32 data
);
void
odm_config_rf_radio_b_8821a(
struct PHY_DM_STRUCT *p_dm_odm,
u32 addr,
u32 data
);
void
odm_config_mac_8821a(
struct PHY_DM_STRUCT *p_dm_odm,
u32 addr,
u8 data
);
void
odm_config_bb_agc_8821a(
struct PHY_DM_STRUCT *p_dm_odm,
u32 addr,
u32 bitmask,
u32 data
);
void
odm_config_bb_phy_reg_pg_8821a(
struct PHY_DM_STRUCT *p_dm_odm,
u32 band,
u32 rf_path,
u32 tx_num,
u32 addr,
u32 bitmask,
u32 data
);
void
odm_config_bb_phy_8821a(
struct PHY_DM_STRUCT *p_dm_odm,
u32 addr,
u32 bitmask,
u32 data
);
void
odm_config_bb_txpwr_lmt_8821a(
struct PHY_DM_STRUCT *p_dm_odm,
u8 *regulation,
u8 *band,
u8 *bandwidth,
u8 *rate_section,
u8 *rf_path,
u8 *channel,
u8 *power_limit
);
#endif
#endif /* end of SUPPORT */

67
hal/phydm/rtl8821a/phydm_rtl8821a.c 100644
View File

@ -0,0 +1,67 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/* ************************************************************
* include files
* ************************************************************ */
#include "mp_precomp.h"
#include "../phydm_precomp.h"
#if (RTL8821A_SUPPORT == 1)
void odm_dynamic_try_state_agg_8821a(
struct PHY_DM_STRUCT *p_dm_odm
)
{
if ((p_dm_odm->support_ic_type & ODM_RTL8821) && (p_dm_odm->support_interface == ODM_ITRF_USB)) {
if(p_dm_odm->rssi_min > 25)
odm_write_1byte(p_dm_odm, 0x4CF, 0x02);
else if(p_dm_odm->rssi_min < 20)
odm_write_1byte(p_dm_odm, 0x4CF, 0x00);
}
}
void odm_dynamic_packet_detection_th_8821a(
struct PHY_DM_STRUCT *p_dm_odm
)
{
if (p_dm_odm->support_ic_type & ODM_RTL8821) {
if (p_dm_odm->rssi_min <= 25) {
odm_set_bb_reg(p_dm_odm, rPwed_TH_Jaguar, bMaskDWord, 0x2aaaf1a8);
odm_set_bb_reg(p_dm_odm, rBWIndication_Jaguar, BIT26, 1);
} else if (p_dm_odm->rssi_min >= 30) {
odm_set_bb_reg(p_dm_odm, rPwed_TH_Jaguar, bMaskDWord, 0x2aaaeec8);
odm_set_bb_reg(p_dm_odm, rBWIndication_Jaguar, BIT26, 0);
}
}
}
void odm_hw_setting_8821a(
struct PHY_DM_STRUCT *p_dm_odm
)
{
odm_dynamic_try_state_agg_8821a(p_dm_odm);
odm_dynamic_packet_detection_th_8821a(p_dm_odm);
}
#endif //#if (RTL8821A_SUPPORT == 1)

29
hal/phydm/rtl8821a/phydm_rtl8821a.h 100644
View File

@ -0,0 +1,29 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODM_RTL8821A_H__
#define __ODM_RTL8821A_H__
void
odm_hw_setting_8821a(
struct PHY_DM_STRUCT *p_dm_odm
);
#endif

5
hal/phydm/rtl8821a/version_rtl8821a.h 100644
View File

@ -0,0 +1,5 @@
/*RTL8821A PHY Parameters*/
#define SVN_COMMIT_VERSION_8821A 62
#define RELEASE_DATE_8821A 20150727
#define COMMIT_BY_8821A "BB_YUCHEN"
#define RELEASE_VERSION_8821A 56

2
hal/phydm/txbf/halcomtxbf.c
View File

@ -132,7 +132,7 @@ phydm_beamform_set_sounding_clk(
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
struct _ADAPTER *padapter = p_dm_odm->adapter;
rtw_run_in_thread_cmd(padapter, hal_com_txbf_clk_work_item_callback, padapter);
rtw_run_in_thread_cmd(padapter, hal_com_txbf_clk_work_item_callback, p_dm_odm);
#else
hal_com_txbf_clk_work_item_callback(p_dm_odm);
#endif

30751
hal/rtl8812a/hal8812a_fw.c
View File

File diff suppressed because it is too large Load Diff

10
hal/rtl8812a/hal8812a_fw.h
View File

@ -25,18 +25,18 @@
#ifdef LOAD_FW_HEADER_FROM_DRIVER
#if (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)))
extern u8 array_mp_8812a_fw_ap[23746];
extern u8 array_mp_8812a_fw_ap[24112];
extern u32 array_length_mp_8812a_fw_ap;
#endif
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) || (DM_ODM_SUPPORT_TYPE & (ODM_CE))
extern u8 array_mp_8812a_fw_nic[26718];
extern u8 array_mp_8812a_fw_nic[27054];
extern u32 array_length_mp_8812a_fw_nic;
extern u8 array_mp_8812a_fw_nic_bt[28238];
extern u8 array_mp_8812a_fw_nic_bt[29918];
extern u32 array_length_mp_8812a_fw_nic_bt;
extern u8 array_mp_8812a_fw_nic_mcc[29240];
extern u8 array_mp_8812a_fw_nic_mcc[29452];
extern u32 array_length_mp_8812a_fw_nic_mcc;
extern u8 array_mp_8812a_fw_wowlan[31002];
extern u8 array_mp_8812a_fw_wowlan[31924];
extern u32 array_length_mp_8812a_fw_wowlan;
#endif
#endif /* end of LOAD_FW_HEADER_FROM_DRIVER */

31
hal/rtl8812a/rtl8812a_cmd.c
View File

@ -69,7 +69,7 @@ s32 fill_h2c_cmd_8812(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffe
u32 msgbox_addr;
u32 msgbox_ex_addr;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
u8 cmd_idx, ext_cmd_len;
u8 cmd_idx;
u32 h2c_cmd = 0;
u32 h2c_cmd_ex = 0;
s32 ret = _FAIL;
@ -105,23 +105,24 @@ s32 fill_h2c_cmd_8812(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffe
*(u8 *)(&h2c_cmd) = ElementID;
if (CmdLen <= 3)
if (CmdLen <= 3) {
_rtw_memcpy((u8 *)(&h2c_cmd) + 1, pCmdBuffer, CmdLen);
else {
h2c_cmd_ex = 0;
} else {
_rtw_memcpy((u8 *)(&h2c_cmd) + 1, pCmdBuffer, 3);
ext_cmd_len = CmdLen - 3;
_rtw_memcpy((u8 *)(&h2c_cmd_ex), pCmdBuffer + 3, ext_cmd_len);
/* Write Ext command */
msgbox_ex_addr = REG_HMEBOX_EXT0_8812 + (h2c_box_num * RTL8812_EX_MESSAGE_BOX_SIZE);
#ifdef CONFIG_H2C_EF
for (cmd_idx = 0; cmd_idx < ext_cmd_len; cmd_idx++)
rtw_write8(padapter, msgbox_ex_addr + cmd_idx, *((u8 *)(&h2c_cmd_ex) + cmd_idx));
#else
h2c_cmd_ex = le32_to_cpu(h2c_cmd_ex);
rtw_write32(padapter, msgbox_ex_addr, h2c_cmd_ex);
#endif
_rtw_memcpy((u8 *)(&h2c_cmd_ex), pCmdBuffer + 3, (CmdLen - 3));
}
/* Write Ext command */
msgbox_ex_addr = REG_HMEBOX_EXT0_8812 + (h2c_box_num * RTL8812_EX_MESSAGE_BOX_SIZE);
#ifdef CONFIG_H2C_EF
for (cmd_idx = 0; cmd_idx < RTL8812_EX_MESSAGE_BOX_SIZE; cmd_idx++)
rtw_write8(padapter, msgbox_ex_addr + cmd_idx, *((u8 *)(&h2c_cmd_ex) + cmd_idx));
#else
h2c_cmd_ex = le32_to_cpu(h2c_cmd_ex);
rtw_write32(padapter, msgbox_ex_addr, h2c_cmd_ex);
#endif
/* Write command */
msgbox_addr = REG_HMEBOX_0 + (h2c_box_num * RTL8812_MESSAGE_BOX_SIZE);
#ifdef CONFIG_H2C_EF

63
hal/rtl8812a/rtl8812a_hal_init.c
View File

@ -23,7 +23,8 @@
#include <rtl8812a_hal.h>
#ifdef CONFIG_RTL8812A
#include "hal8812a_fw.h"
#else
#endif
#ifdef CONFIG_RTL8821A
#include "hal8821a_fw.h"
#endif
/* -------------------------------------------------------------------------
@ -553,11 +554,16 @@ FirmwareDownload8812(
#ifdef CONFIG_WOWLAN
if (pwrpriv->wowlan_mode) {
#ifdef CONFIG_RTL8812A
pFirmware->szFwBuffer = array_mp_8812a_fw_wowlan;
pFirmware->ulFwLength = array_length_mp_8812a_fw_wowlan;
#else
pFirmware->szFwBuffer = array_mp_8821a_fw_wowlan;
pFirmware->ulFwLength = array_length_mp_8821a_fw_wowlan;
if (pHalData->odmpriv.support_ic_type == ODM_RTL8812)
pFirmware->szFwBuffer = array_mp_8812a_fw_wowlan;
pFirmware->ulFwLength = array_length_mp_8812a_fw_wowlan;
}
#endif
#ifdef CONFIG_RTL8821A
if (pHalData->odmpriv.support_ic_type == ODM_RTL8821)
pFirmware->szFwBuffer = array_mp_8821a_fw_wowlan;
pFirmware->ulFwLength = array_length_mp_8821a_fw_wowlan;
}
#endif
RTW_INFO("%s fw:%s, size: %d\n", __func__, "WoWLAN", pFirmware->ulFwLength);
@ -567,11 +573,16 @@ FirmwareDownload8812(
#ifdef CONFIG_AP_WOWLAN
if (pwrpriv->wowlan_ap_mode) {
#ifdef CONFIG_RTL8812A
pFirmware->szFwBuffer = array_mp_8812a_fw_ap;
pFirmware->ulFwLength = array_length_mp_8812a_fw_ap;
#else
pFirmware->szFwBuffer = array_mp_8821a_fw_ap;
pFirmware->ulFwLength = array_length_mp_8821a_fw_ap;
if (pHalData->odmpriv.support_ic_type == ODM_RTL8812) {
pFirmware->szFwBuffer = array_mp_8812a_fw_ap;
pFirmware->ulFwLength = array_length_mp_8812a_fw_ap;
}
#endif
#ifdef CONFIG_RTL8821A
if (pHalData->odmpriv.support_ic_type == ODM_RTL8821) {
pFirmware->szFwBuffer = array_mp_8821a_fw_ap;
pFirmware->ulFwLength = array_length_mp_8821a_fw_ap;
}
#endif
RTW_INFO("%s fw: %s, size: %d\n", __func__, "AP_WoWLAN", pFirmware->ulFwLength);
@ -582,11 +593,16 @@ FirmwareDownload8812(
if (pHalData->EEPROMBluetoothCoexist == _TRUE) {
#ifdef CONFIG_RTL8812A
pFirmware->szFwBuffer = array_mp_8812a_fw_nic_bt;
pFirmware->ulFwLength = array_length_mp_8812a_fw_nic_bt;
#else
pFirmware->szFwBuffer = array_mp_8821a_fw_nic_bt;
pFirmware->ulFwLength = array_length_mp_8821a_fw_nic_bt;
if (pHalData->odmpriv.support_ic_type == ODM_RTL8812) {
pFirmware->szFwBuffer = array_mp_8812a_fw_nic_bt;
pFirmware->ulFwLength = array_length_mp_8812a_fw_nic_bt;
}
#endif
#ifdef CONFIG_RTL8821A
if (pHalData->odmpriv.support_ic_type == ODM_RTL8821) {
pFirmware->szFwBuffer = array_mp_8821a_fw_nic_bt;
pFirmware->ulFwLength = array_length_mp_8821a_fw_nic_bt;
}
#endif
RTW_INFO("%s fw:%s, size: %d\n", __FUNCTION__, "NIC-BTCOEX", pFirmware->ulFwLength);
@ -595,11 +611,16 @@ FirmwareDownload8812(
{
#ifdef CONFIG_RTL8812A
pFirmware->szFwBuffer = array_mp_8812a_fw_nic;
pFirmware->ulFwLength = array_length_mp_8812a_fw_nic;
#else
pFirmware->szFwBuffer = array_mp_8821a_fw_nic;
pFirmware->ulFwLength = array_length_mp_8821a_fw_nic;
if (pHalData->odmpriv.support_ic_type == ODM_RTL8812) {
pFirmware->szFwBuffer = array_mp_8812a_fw_nic;
pFirmware->ulFwLength = array_length_mp_8812a_fw_nic;
}
#endif
#ifdef CONFIG_RTL8821A
if (pHalData->odmpriv.support_ic_type == ODM_RTL8821) {
pFirmware->szFwBuffer = array_mp_8821a_fw_nic;
pFirmware->ulFwLength = array_length_mp_8821a_fw_nic;
}
#endif
RTW_INFO("%s fw:%s, size: %d\n", __FUNCTION__, "NIC", pFirmware->ulFwLength);

6
hal/rtl8812a/rtl8812a_phycfg.c
View File

@ -1307,12 +1307,14 @@ PHY_SwitchWirelessBand8812(
#ifdef CONFIG_RTL8821A
/* 20160224 yiwei , 8811au one antenna module don't support antenna div , so driver must to control antenna band , otherwise one of the band will has issue */
#if 0
if (IS_HARDWARE_TYPE_8821(Adapter)) {
if (Adapter->registrypriv.drv_ant_band_switch == 1 && pHalData->AntDivCfg == 0) {
phydm_set_ext_band_switch_8821A(&(pHalData->odmpriv) , ODM_BAND_2_4G);
phydm_set_ext_band_switch_8821a(&(pHalData->odmpriv) , ODM_BAND_2_4G);
RTW_DBG("Switch ant band to ODM_BAND_2_4G\n");
}
}
#endif
#endif /*#ifdef CONFIG_RTL8821A*/
phy_set_bb_reg(Adapter, rOFDMCCKEN_Jaguar, bOFDMEN_Jaguar | bCCKEN_Jaguar, 0x03);
@ -1364,12 +1366,14 @@ PHY_SwitchWirelessBand8812(
#ifdef CONFIG_RTL8821A
/* 20160224 yiwei , 8811a one antenna module don't support antenna div , so driver must to control antenna band , otherwise one of the band will has issue */
#if 0
if (IS_HARDWARE_TYPE_8821(Adapter)) {
if (Adapter->registrypriv.drv_ant_band_switch == 1 && pHalData->AntDivCfg == 0) {
phydm_set_ext_band_switch_8821A(&(pHalData->odmpriv) , ODM_BAND_5G);
RTW_DBG("Switch ant band to ODM_BAND_5G\n");
}
}
#endif
#endif /*#ifdef CONFIG_RTL8821A*/
if (IS_HARDWARE_TYPE_8821(Adapter))

10
hal/rtl8812a/usb/usb_halinit.c
View File

@ -165,8 +165,14 @@ void rtl8812au_interface_configure(_adapter *padapter)
}
}
#else /* !CONFIG_PREALLOC_RX_SKB_BUFFER */
pHalData->rxagg_usb_size = 0x5;
pHalData->rxagg_usb_timeout = 0x20;
#if defined(CONFIG_PLATFORM_HISILICON) && defined(CONFIG_RTL8812A)
pHalData->rxagg_usb_size = 3; /*unit 4k for USB aggregation mode */
pHalData->rxagg_usb_timeout = 8; /*unit 32us*/
#else
pHalData->rxagg_usb_size = 6; /* unit 4k for USB aggregation mode */
pHalData->rxagg_usb_timeout = 0x20; /* unit 32us */
#endif /* CONFIG_PLATFORM_HISILICON */
#endif /* CONFIG_PREALLOC_RX_SKB_BUFFER */
}

4
ifcfg-wlan0
View File

@ -1,4 +0,0 @@
#DHCP client
DEVICE=wlan0
BOOTPROTO=dhcp
ONBOOT=yes

2
include/autoconf.h
View File

@ -333,7 +333,7 @@
/*
* Debug Related Config
*/
#define DBG 0
#define DBG 1
#define CONFIG_PROC_DEBUG

5
include/drv_types.h
View File

@ -420,9 +420,6 @@ struct registry_priv {
#endif
u8 check_hw_status;
#ifdef CONFIG_SW_LED
u8 led_ctrl;
#endif
u32 pci_aspm_config;
};
@ -906,7 +903,7 @@ struct dvobj_priv {
#ifdef CONFIG_AP_MODE
u8 nr_ap_if; /* total interface s number of ap/go mode. */
u32 inter_bcn_space; /* unit:ms */
u16 inter_bcn_space; /* unit:ms */
_queue ap_if_q;
#endif

4
include/osdep_service.h
View File

@ -349,9 +349,13 @@ __inline static unsigned char _cancel_timer_ex(_timer *ptimer)
{
u8 bcancelled;
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
return del_timer_sync(&ptimer->t);
#else
_cancel_timer(ptimer, &bcancelled);
return bcancelled;
#endif //(LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
}
static __inline void thread_enter(char *name)

28
include/osdep_service_linux.h
View File

@ -164,7 +164,15 @@ typedef spinlock_t _lock;
#else
typedef struct semaphore _mutex;
#endif
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
typedef struct legacy_timer_emu {
struct timer_list t;
void (*function)(unsigned long);
unsigned long data;
} _timer;
#else
typedef struct timer_list _timer;
#endif //(LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
typedef struct completion _completion;
struct __queue {
@ -294,22 +302,42 @@ __inline static void rtw_list_delete(_list *plist)
list_del_init(plist);
}
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
static void legacy_timer_emu_func(struct timer_list *t)
{
struct legacy_timer_emu *lt = from_timer(lt, t, t);
lt->function(lt->data);
}
#endif //(LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
__inline static void _init_timer(_timer *ptimer, _nic_hdl nic_hdl, void *pfunc, void *cntx)
{
/* setup_timer(ptimer, pfunc,(u32)cntx); */
ptimer->function = pfunc;
ptimer->data = (unsigned long)cntx;
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
timer_setup(&ptimer->t, legacy_timer_emu_func, 0);
#else
init_timer(ptimer);
#endif //(LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
}
__inline static void _set_timer(_timer *ptimer, u32 delay_time)
{
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
mod_timer(&ptimer->t, (jiffies + (delay_time * HZ / 1000)));
#else
mod_timer(ptimer , (jiffies + (delay_time * HZ / 1000)));
#endif //(LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
}
__inline static void _cancel_timer(_timer *ptimer, u8 *bcancelled)
{
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
*bcancelled = del_timer_sync(&ptimer->t) == 1 ? 1 : 0;
#else
*bcancelled = del_timer_sync(ptimer) == 1 ? 1 : 0;
#endif //(LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0))
}
static inline void _init_workitem(_workitem *pwork, void *pfunc, void *cntx)

2
include/rtl8812a_recv.h
View File

@ -29,6 +29,8 @@
#ifndef CONFIG_MINIMAL_MEMORY_USAGE
#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER
#define MAX_RECVBUF_SZ (rtw_rtkm_get_buff_size()) /*depend rtkm*/
#elif defined(CONFIG_PLATFORM_HISILICON) && defined(CONFIG_RTL8812A)
#define MAX_RECVBUF_SZ (16384) /* 16k */
#else
#define MAX_RECVBUF_SZ (32768) /*32k*/
#endif

3
include/rtw_cmd.h
View File

@ -245,6 +245,7 @@ enum rtw_drvextra_cmd_id {
TEST_H2C_CID,
MP_CMD_WK_CID,
CUSTOMER_STR_WK_CID,
SET_SECURITYPRIV,
MAX_WK_CID
};
@ -1029,7 +1030,7 @@ extern u8 rtw_dynamic_chk_wk_cmd(_adapter *adapter);
u8 rtw_lps_ctrl_wk_cmd(_adapter *padapter, u8 lps_ctrl_type, u8 enqueue);
u8 rtw_dm_in_lps_wk_cmd(_adapter *padapter);
u8 rtw_lps_change_dtim_cmd(_adapter *padapter, u8 dtim);
u8 rtw_set_securitypriv_cmd(_adapter *padapter, u8 *sme);
#if (RATE_ADAPTIVE_SUPPORT == 1)
u8 rtw_rpt_timer_cfg_cmd(_adapter *padapter, u16 minRptTime);
#endif

4
include/rtw_mlme.h
View File

@ -51,7 +51,7 @@
#define WIFI_ADHOC_MASTER_STATE 0x00000040
#define WIFI_UNDER_LINKING 0x00000080
#define WIFI_UNDER_WPS 0x00000100
/*#define WIFI_UNDEFINED_STATE 0x00000200*/
#define WIFI_UNDER_DISCONNTING 0x00000200
#define WIFI_STA_ALIVE_CHK_STATE 0x00000400
#define WIFI_SITE_MONITOR 0x00000800 /* under site surveying */
#define WIFI_WDS 0x00001000
@ -486,6 +486,8 @@ struct tdls_info {
#ifdef CONFIG_WFD
struct wifi_display_info *wfd_info;
#endif
struct submit_ctx *tdls_sctx;
};
struct tdls_txmgmt {

1
include/rtw_mlme_ext.h
View File

@ -921,6 +921,7 @@ void rtw_macid_ctl_set_rate_bmp1(struct macid_ctl_t *macid_ctl, u8 id, u32 bmp);
void rtw_macid_ctl_init(struct macid_ctl_t *macid_ctl);
void rtw_macid_ctl_deinit(struct macid_ctl_t *macid_ctl);
u8 rtw_iface_bcmc_id_get(_adapter *padapter);
void rtw_iface_bcmc_id_set(_adapter *padapter, u8 mac_id);
u32 report_join_res(_adapter *padapter, int res);
void report_survey_event(_adapter *padapter, union recv_frame *precv_frame);

1
include/rtw_recv.h
View File

@ -115,6 +115,7 @@ struct recv_reorder_ctrl {
struct stainfo_rxcache {
u16 tid_rxseq[16];
u8 iv[16][8];
#if 0
unsigned short tid0_rxseq;
unsigned short tid1_rxseq;

2
include/rtw_security.h
View File

@ -141,6 +141,7 @@ struct security_priv {
union Keytype dot118021XGrprxmickey[4];
union pn48 dot11Grptxpn; /* PN48 used for Grp Key xmit. */
union pn48 dot11Grprxpn; /* PN48 used for Grp Key recv. */
u8 iv_seq[4][8];
#ifdef CONFIG_IEEE80211W
u32 dot11wBIPKeyid; /* key id used for BIP Key ( tx key index) */
union Keytype dot11wBIPKey[6]; /* BIP Key, for index4 and index5 */
@ -242,6 +243,7 @@ struct security_priv {
u64 aes_sw_dec_cnt_mc;
u64 aes_sw_dec_cnt_uc;
#endif /* DBG_SW_SEC_CNT */
int set_security_ret;
};
struct sha256_state {

1
include/rtw_tdls.h
View File

@ -111,6 +111,7 @@ u8 rtw_tdls_is_chsw_allowed(_adapter *padapter);
void rtw_reset_tdls_info(_adapter *padapter);
int rtw_init_tdls_info(_adapter *padapter);
void rtw_free_tdls_info(struct tdls_info *ptdlsinfo);
void rtw_free_all_tdls_sta(_adapter *padapter, u8 from_cmd_thread);
int issue_nulldata_to_TDLS_peer_STA(_adapter *padapter, unsigned char *da, unsigned int power_mode, int try_cnt, int wait_ms);
void rtw_init_tdls_timer(_adapter *padapter, struct sta_info *psta);
void rtw_free_tdls_timer(struct sta_info *psta);

2
include/rtw_version.h
View File

@ -1 +1 @@
#define DRIVERVERSION "v5.2.9_22809.20170621"
#define DRIVERVERSION "v5.2.9.3_24903.20171101"

2
include/rtw_vht.h
View File

@ -141,4 +141,6 @@ void VHTOnAssocRsp(_adapter *padapter);
u8 rtw_vht_mcsmap_to_nss(u8 *pvht_mcs_map);
void rtw_vht_nss_to_mcsmap(u8 nss, u8 *target_mcs_map, u8 *cur_mcs_map);
extern const u16 VHT_MCS_DATA_RATE[3][2][30];
#endif /* _RTW_VHT_H_ */

36
include/wifi.h
View File

@ -997,6 +997,42 @@ typedef enum _HT_CAP_AMPDU_DENSITY {
#define IEEE80211_HT_IE_NON_GF_STA_PRSNT 0x0004
#define IEEE80211_HT_IE_NON_HT_STA_PRSNT 0x0010
/* 802.11ac VHT Capabilities */
#define IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895 0x00000000
#define IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991 0x00000001
#define IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 0x00000002
#define IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ 0x00000004
#define IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160_80PLUS80MHZ 0x00000008
#define IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_MASK 0x0000000C
#define IEEE80211_VHT_CAP_RXLDPC 0x00000010
#define IEEE80211_VHT_CAP_SHORT_GI_80 0x00000020
#define IEEE80211_VHT_CAP_SHORT_GI_160 0x00000040
#define IEEE80211_VHT_CAP_TXSTBC 0x00000080
#define IEEE80211_VHT_CAP_RXSTBC_1 0x00000100
#define IEEE80211_VHT_CAP_RXSTBC_2 0x00000200
#define IEEE80211_VHT_CAP_RXSTBC_3 0x00000300
#define IEEE80211_VHT_CAP_RXSTBC_4 0x00000400
#define IEEE80211_VHT_CAP_RXSTBC_MASK 0x00000700
#define IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE 0x00000800
#define IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE 0x00001000
#define IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT 13
#define IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK \
(7 << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT)
#define IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_SHIFT 16
#define IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK \
(7 << IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_SHIFT)
#define IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE 0x00080000
#define IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE 0x00100000
#define IEEE80211_VHT_CAP_VHT_TXOP_PS 0x00200000
#define IEEE80211_VHT_CAP_HTC_VHT 0x00400000
#define IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT 23
#define IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK \
(7 << IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT)
#define IEEE80211_VHT_CAP_VHT_LINK_ADAPTATION_VHT_UNSOL_MFB 0x08000000
#define IEEE80211_VHT_CAP_VHT_LINK_ADAPTATION_VHT_MRQ_MFB 0x0c000000
#define IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN 0x10000000
#define IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN 0x20000000
/* block-ack parameters */
#define IEEE80211_ADDBA_PARAM_POLICY_MASK 0x0002
#define IEEE80211_ADDBA_PARAM_TID_MASK 0x003C

299
os_dep/linux/ioctl_cfg80211.c
View File

@ -1257,6 +1257,8 @@ static int rtw_cfg80211_set_encryption(struct net_device *dev, struct ieee_param
_rtw_memcpy(padapter->securitypriv.dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8);
_rtw_memcpy(padapter->securitypriv.dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8);
padapter->securitypriv.binstallGrpkey = _TRUE;
if (param->u.crypt.idx < 4)
_rtw_memcpy(padapter->securitypriv.iv_seq[param->u.crypt.idx], param->u.crypt.seq, 8);
/* DEBUG_ERR((" param->u.crypt.key_len=%d\n", param->u.crypt.key_len)); */
RTW_INFO(" ~~~~set sta key:groupkey\n");
@ -3034,7 +3036,7 @@ leave_ibss:
static int cfg80211_rtw_connect(struct wiphy *wiphy, struct net_device *ndev,
struct cfg80211_connect_params *sme)
{
int ret = 0;
int ret = 0, set_security_ret = 0;
struct wlan_network *pnetwork = NULL;
NDIS_802_11_AUTHENTICATION_MODE authmode;
NDIS_802_11_SSID ndis_ssid;
@ -3113,6 +3115,13 @@ static int cfg80211_rtw_connect(struct wiphy *wiphy, struct net_device *ndev,
}
#endif
if (check_fwstate(pmlmepriv, WIFI_UNDER_DISCONNTING)) {
RTW_INFO(FUNC_NDEV_FMT" WIFI_UNDER_DISCONNTING exit\n", FUNC_NDEV_ARG(ndev));
ret = -EBUSY;
goto cancel_ps_deny;
}
rtw_mi_scan_abort(padapter, _TRUE);
_rtw_memset(&ndis_ssid, 0, sizeof(NDIS_802_11_SSID));
@ -3124,8 +3133,21 @@ static int cfg80211_rtw_connect(struct wiphy *wiphy, struct net_device *ndev,
if (sme->bssid)
RTW_INFO("bssid="MAC_FMT"\n", MAC_ARG(sme->bssid));
#if 1
set_security_ret = rtw_set_securitypriv_cmd(padapter, (u8 *)sme);
if (set_security_ret < 0) {
RTW_INFO("rtw_set_securitypriv_cmd=%d\n", ret);
ret = -EBUSY;
goto cancel_ps_deny;
} else {
if (psecuritypriv->set_security_ret < 0) {
ret = psecuritypriv->set_security_ret;
RTW_INFO("psecuritypriv->set_security_ret=%d\n", psecuritypriv->set_security_ret);
goto cancel_ps_deny;
}
}
#else
psecuritypriv->ndisencryptstatus = Ndis802_11EncryptionDisabled;
psecuritypriv->dot11PrivacyAlgrthm = _NO_PRIVACY_;
psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_;
@ -3249,10 +3271,11 @@ static int cfg80211_rtw_connect(struct wiphy *wiphy, struct net_device *ndev,
authmode = psecuritypriv->ndisauthtype;
rtw_set_802_11_authentication_mode(padapter, authmode);
#endif
/* rtw_set_802_11_encryption_mode(padapter, padapter->securitypriv.ndisencryptstatus); */
if (rtw_set_802_11_connect(padapter, (u8 *)sme->bssid, &ndis_ssid) == _FALSE) {
RTW_INFO("rtw_set_802_11_connect=_FALSE\n");
ret = -1;
goto cancel_ps_deny;
}
@ -3302,8 +3325,15 @@ static int cfg80211_rtw_disconnect(struct wiphy *wiphy, struct net_device *ndev,
rtw_set_to_roam(padapter, 0);
if (MLME_IS_STA(padapter) && check_fwstate(&(padapter->mlmepriv), WIFI_UNDER_DISCONNTING)) {
RTW_INFO(FUNC_NDEV_FMT" WIFI_UNDER_DISCONNTING exit\n", FUNC_NDEV_ARG(ndev));
goto exit;
}
/* if(check_fwstate(&padapter->mlmepriv, _FW_LINKED)) */
{
set_fwstate(&(padapter->mlmepriv), WIFI_UNDER_DISCONNTING);
rtw_scan_abort(padapter);
LeaveAllPowerSaveMode(padapter);
rtw_disassoc_cmd(padapter, 500, RTW_CMDF_WAIT_ACK);
@ -3316,6 +3346,7 @@ static int cfg80211_rtw_disconnect(struct wiphy *wiphy, struct net_device *ndev,
rtw_pwr_wakeup(padapter);
}
exit:
rtw_wdev_set_not_indic_disco(pwdev_priv, 0);
RTW_INFO(FUNC_NDEV_FMT" return 0\n", FUNC_NDEV_ARG(ndev));
@ -4331,9 +4362,9 @@ static int cfg80211_rtw_del_station(struct wiphy *wiphy, struct net_device *ndev
RTW_INFO("flush all sta, and cam_entry\n");
flush_all_cam_entry(padapter); /* clear CAM */
#ifdef CONFIG_AP_MODE
ret = rtw_sta_flush(padapter, _TRUE);
#endif
return ret;
}
@ -6654,6 +6685,120 @@ void rtw_cfg80211_init_wdev_data(_adapter *padapter)
#endif
}
static void rtw_cfg80211_init_vht_capab(_adapter *padapter, struct ieee80211_sta_vht_cap *vht_cap, u8 rf_type)
{
struct registry_priv *pregistrypriv = &padapter->registrypriv;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv;
u8 bw, rf_num, rx_stbc_nss = 0;
u16 HighestRate;
u32 rx_packet_offset, max_recvbuf_sz;
vht_cap->vht_supported = _TRUE;
rtw_vht_use_default_setting(padapter);
/* Reference: core/rtw_vht.c */
/* MCS map */
vht_cap->vht_mcs.tx_mcs_map = pvhtpriv->vht_mcs_map[0] | (pvhtpriv->vht_mcs_map[1] << 8);
vht_cap->vht_mcs.rx_mcs_map = vht_cap->vht_mcs.tx_mcs_map;
/* B0 B1 Maximum MPDU Length */
rtw_hal_get_def_var(padapter, HAL_DEF_RX_PACKET_OFFSET, &rx_packet_offset);
rtw_hal_get_def_var(padapter, HAL_DEF_MAX_RECVBUF_SZ, &max_recvbuf_sz);
if ((max_recvbuf_sz - rx_packet_offset) >= 11454) {
vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
} else if ((max_recvbuf_sz - rx_packet_offset) >= 7991) {
vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991;
} else if ((max_recvbuf_sz - rx_packet_offset) >= 3895) {
vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895;
}
/* B2 B3 Supported Channel Width Set */
if (hal_chk_bw_cap(padapter, BW_CAP_160M) && REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_160)) {
if (hal_chk_bw_cap(padapter, BW_CAP_80_80M) && REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_80_80))
vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160_80PLUS80MHZ;
else
vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ;
}
/* B4 Rx LDPC */
if(TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_RX)) {
vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC;
}
/* B5 ShortGI for 80MHz */
if (pvhtpriv->sgi_80m)
vht_cap->cap |= IEEE80211_VHT_CAP_SHORT_GI_80;
/* B6 ShortGI for 160MHz */
// todo
/* B7 Tx STBC */
if(TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX)) {
vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
}
/* B8 B9 B10 Rx STBC */
if(TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_RX)) {
rtw_hal_get_def_var(padapter, HAL_DEF_RX_STBC, (u8 *)(&rx_stbc_nss));
if (rx_stbc_nss == 1)
vht_cap->cap |= IEEE80211_VHT_CAP_RXSTBC_1;
else if (rx_stbc_nss == 2)
vht_cap->cap |= IEEE80211_VHT_CAP_RXSTBC_2;
else if (rx_stbc_nss == 3)
vht_cap->cap |= IEEE80211_VHT_CAP_RXSTBC_3;
}
/* B11 SU Beamformer Capable */
if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) {
vht_cap->cap |= IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE;
/* B16 17 18 Number of Sounding Dimensions */
rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMER_CAP, (u8 *)&rf_num);
vht_cap->cap |= rf_num << IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_SHIFT;
/* B19 MU Beamformer Capable */
if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE))
vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE;
}
/* B12 SU Beamformee Capable */
if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)) {
vht_cap->cap |= IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE;
// B13 14 15 Compressed Steering Number of Beamformer Antennas Supported
rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMEE_CAP, (u8 *)&rf_num);
vht_cap->cap |= rf_num << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT;
/* B20 MU Beamformee Capable */
if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE))
vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE;
}
// TXOP PS disabled or not supported
/* B21 VHT TXOP PS */
/* B22 +HTC-VHT Capable */
vht_cap->cap |= IEEE80211_VHT_CAP_HTC_VHT;
/* B23 24 25 Maximum A-MPDU Length Exponent */
if (pregistrypriv->ampdu_factor != 0xFE)
vht_cap->cap |= pregistrypriv->ampdu_factor << IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT;
else
vht_cap->cap |= 7 << IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT;
// Link Adaptation not supported
/* B26 27 VHT Link Adaptation Capable */
/* find the largest bw supported by both registry and hal */
bw = hal_largest_bw(padapter, REGSTY_BW_5G(pregistrypriv));
HighestRate = VHT_MCS_DATA_RATE[bw][pvhtpriv->sgi_80m][((pvhtpriv->vht_highest_rate - MGN_VHT1SS_MCS0)&0x3f)];
HighestRate = (HighestRate+1) >> 1;
vht_cap->vht_mcs.tx_highest = HighestRate; //indicate we support highest rx rate is 600Mbps.
vht_cap->vht_mcs.rx_highest = HighestRate; //indicate we support highest rx rate is 600Mbps.
}
void rtw_cfg80211_init_wiphy(_adapter *padapter)
{
u8 rf_type;
@ -6673,8 +6818,10 @@ void rtw_cfg80211_init_wiphy(_adapter *padapter)
#ifdef CONFIG_IEEE80211_BAND_5GHZ
if (is_supported_5g(padapter->registrypriv.wireless_mode)) {
bands = wiphy->bands[NL80211_BAND_5GHZ];
if (bands)
if (bands) {
rtw_cfg80211_init_ht_capab(padapter, &bands->ht_cap, NL80211_BAND_5GHZ, rf_type);
rtw_cfg80211_init_vht_capab(padapter, &bands->vht_cap, rf_type);
}
}
#endif
/* init regulary domain */
@ -7228,4 +7375,144 @@ void rtw_cfg80211_dev_res_unregister(struct dvobj_priv *dvobj)
#endif
}
void rtw_cfg80211_set_securitypriv(_adapter *padapter, u8 *buf)
{
struct cfg80211_connect_params *sme = (struct cfg80211_connect_params *)buf;
NDIS_802_11_AUTHENTICATION_MODE authmode;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct security_priv *psecuritypriv = &padapter->securitypriv;
int ret = 0;
RTW_INFO("=>"FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
psecuritypriv->ndisencryptstatus = Ndis802_11EncryptionDisabled;
psecuritypriv->dot11PrivacyAlgrthm = _NO_PRIVACY_;
psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_;
psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open; /* open system */
psecuritypriv->ndisauthtype = Ndis802_11AuthModeOpen;
psecuritypriv->set_security_ret = 0;
#ifdef CONFIG_WAPI_SUPPORT
padapter->wapiInfo.bWapiEnable = false;
#endif
ret = rtw_cfg80211_set_wpa_version(psecuritypriv, sme->crypto.wpa_versions);
if (ret < 0)
goto exit;
#ifdef CONFIG_WAPI_SUPPORT
if (sme->crypto.wpa_versions & NL80211_WAPI_VERSION_1) {
padapter->wapiInfo.bWapiEnable = true;
padapter->wapiInfo.extra_prefix_len = WAPI_EXT_LEN;
padapter->wapiInfo.extra_postfix_len = SMS4_MIC_LEN;
}
#endif
ret = rtw_cfg80211_set_auth_type(psecuritypriv, sme->auth_type);
#ifdef CONFIG_WAPI_SUPPORT
if (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_WAPI)
padapter->mlmeextpriv.mlmext_info.auth_algo = psecuritypriv->dot11AuthAlgrthm;
#endif
if (ret < 0)
goto exit;
RTW_INFO("%s, ie_len=%zu\n", __func__, sme->ie_len);
ret = rtw_cfg80211_set_wpa_ie(padapter, (u8 *)sme->ie, sme->ie_len);
if (ret < 0)
goto exit;
if (sme->crypto.n_ciphers_pairwise) {
ret = rtw_cfg80211_set_cipher(psecuritypriv, sme->crypto.ciphers_pairwise[0], _TRUE);
if (ret < 0)
goto exit;
}
/* For WEP Shared auth */
if (sme->key_len > 0 && sme->key) {
u32 wep_key_idx, wep_key_len, wep_total_len;
NDIS_802_11_WEP *pwep = NULL;
RTW_INFO("%s(): Shared/Auto WEP\n", __FUNCTION__);
wep_key_idx = sme->key_idx;
wep_key_len = sme->key_len;
if (sme->key_idx > WEP_KEYS) {
ret = -EINVAL;
goto exit;
}
if (wep_key_len > 0) {
wep_key_len = wep_key_len <= 5 ? 5 : 13;
wep_total_len = wep_key_len + FIELD_OFFSET(NDIS_802_11_WEP, KeyMaterial);
pwep = (NDIS_802_11_WEP *) rtw_malloc(wep_total_len);
if (pwep == NULL) {
RTW_INFO(" wpa_set_encryption: pwep allocate fail !!!\n");
ret = -ENOMEM;
goto exit;
}
_rtw_memset(pwep, 0, wep_total_len);
pwep->KeyLength = wep_key_len;
pwep->Length = wep_total_len;
if (wep_key_len == 13) {
padapter->securitypriv.dot11PrivacyAlgrthm = _WEP104_;
padapter->securitypriv.dot118021XGrpPrivacy = _WEP104_;
}
} else {
ret = -EINVAL;
goto exit;
}
pwep->KeyIndex = wep_key_idx;
pwep->KeyIndex |= 0x80000000;
_rtw_memcpy(pwep->KeyMaterial, (void *)sme->key, pwep->KeyLength);
if (rtw_set_802_11_add_wep(padapter, pwep) == (u8)_FAIL)
ret = -EOPNOTSUPP ;
if (pwep)
rtw_mfree((u8 *)pwep, wep_total_len);
if (ret < 0)
goto exit;
}
ret = rtw_cfg80211_set_cipher(psecuritypriv, sme->crypto.cipher_group, _FALSE);
if (ret < 0)
goto exit;
if (sme->crypto.n_akm_suites) {
ret = rtw_cfg80211_set_key_mgt(psecuritypriv, sme->crypto.akm_suites[0]);
if (ret < 0)
goto exit;
}
#ifdef CONFIG_8011R
else {
/*It could be a connection without RSN IEs*/
psecuritypriv->rsn_akm_suite_type = 0;
}
#endif
#ifdef CONFIG_WAPI_SUPPORT
if (sme->crypto.akm_suites[0] == WLAN_AKM_SUITE_WAPI_PSK)
padapter->wapiInfo.bWapiPSK = true;
else if (sme->crypto.akm_suites[0] == WLAN_AKM_SUITE_WAPI_CERT)
padapter->wapiInfo.bWapiPSK = false;
#endif
authmode = psecuritypriv->ndisauthtype;
rtw_set_802_11_authentication_mode(padapter, authmode);
exit:
psecuritypriv->set_security_ret = ret;
RTW_INFO("<="FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter));
}
#endif /* CONFIG_IOCTL_CFG80211 */

1
os_dep/linux/ioctl_cfg80211.h
View File

@ -292,6 +292,7 @@ void rtw_cfg80211_rx_probe_request(_adapter *padapter, union recv_frame *rframe)
int rtw_cfg80211_set_mgnt_wpsp2pie(struct net_device *net, char *buf, int len, int type);
bool rtw_cfg80211_pwr_mgmt(_adapter *adapter);
void rtw_cfg80211_set_securitypriv(_adapter *padapter, u8 *buf);
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0)) && !defined(COMPAT_KERNEL_RELEASE)
#define rtw_cfg80211_rx_mgmt(wdev, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt(wdev_to_ndev(wdev), freq, buf, len, gfp)

8
os_dep/linux/ioctl_linux.c
View File

@ -1379,6 +1379,10 @@ static int wpa_set_encryption(struct net_device *dev, struct ieee_param *param,
}
padapter->securitypriv.binstallGrpkey = _TRUE;
/* DEBUG_ERR((" param->u.crypt.key_len=%d\n", param->u.crypt.key_len)); */
if (param->u.crypt.idx < 4) {
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
_rtw_memcpy(padapter->securitypriv.iv_seq[param->u.crypt.idx], param->u.crypt.seq, 8);
}
RTW_INFO(" ~~~~set sta key:groupkey\n");
padapter->securitypriv.dot118021XGrpKeyid = param->u.crypt.idx;
@ -7882,9 +7886,9 @@ static int rtw_hostapd_sta_flush(struct net_device *dev)
RTW_INFO("%s\n", __FUNCTION__);
flush_all_cam_entry(padapter); /* clear CAM */
#ifdef CONFIG_AP_MODE
ret = rtw_sta_flush(padapter, _TRUE);
#endif
return ret;
}

5
os_dep/linux/mlme_linux.c
View File

@ -163,6 +163,9 @@ void rtw_os_indicate_disconnect(_adapter *adapter, u16 reason, u8 locally_gener
netif_carrier_off(adapter->pnetdev); /* Do it first for tx broadcast pkt after disconnection issue! */
/* modify for CONFIG_IEEE80211W, none 11w also can use the same command */
rtw_reset_securitypriv_cmd(adapter);
#ifdef CONFIG_IOCTL_CFG80211
rtw_cfg80211_indicate_disconnect(adapter, reason, locally_generated);
#endif /* CONFIG_IOCTL_CFG80211 */
@ -172,8 +175,6 @@ void rtw_os_indicate_disconnect(_adapter *adapter, u16 reason, u8 locally_gener
#ifdef RTK_DMP_PLATFORM
_set_workitem(&adapter->mlmepriv.Linkdown_workitem);
#endif
/* modify for CONFIG_IEEE80211W, none 11w also can use the same command */
rtw_reset_securitypriv_cmd(adapter);
}

10
os_dep/linux/os_intfs.c
View File

@ -710,12 +710,6 @@ module_param(rtw_en_gro, int, 0644);
#endif /* CONFIG_RTW_GRO */
#endif /* CONFIG_RTW_NAPI */
#ifdef CONFIG_SW_LED
int rtw_led_ctrl = 1; /* Default to normal blink */
module_param(rtw_led_ctrl, int, 0644);
MODULE_PARM_DESC(rtw_led_ctrl,"Led Control: 0=Always off, 1=Normal blink, 2=Always on");
#endif /* CONFIG_SW_LED */
void rtw_regsty_load_target_tx_power(struct registry_priv *regsty)
{
int path, rs;
@ -1044,10 +1038,6 @@ uint loadparam(_adapter *padapter)
registry_par->trx_share_mode = rtw_trx_share_mode;
#endif
#ifdef CONFIG_SW_LED
registry_par->led_ctrl = (u8)rtw_led_ctrl;
#endif /* CONFIG_SW_LED */
#ifdef CONFIG_PCI_HCI
registry_par->pci_aspm_config = rtw_pci_aspm_enable;
#endif

3
os_dep/linux/usb_intf.c
View File

@ -168,6 +168,7 @@ static struct usb_device_id rtw_usb_id_tbl[] = {
{USB_DEVICE(0x0789, 0x016E), .driver_info = RTL8812}, /* Logitec - Edimax */
{USB_DEVICE(0x07B8, 0x8812), .driver_info = RTL8812}, /* Abocom - Abocom */
{USB_DEVICE(0x0B05, 0x17D2), .driver_info = RTL8812}, /* ASUS - Edimax */
{USB_DEVICE(0x0BDA, 0x8812), .driver_info = RTL8812}, /* KOOTEK */
{USB_DEVICE(0x0DF6, 0x0074), .driver_info = RTL8812}, /* Sitecom - Edimax */
{USB_DEVICE(0x0E66, 0x0022), .driver_info = RTL8812}, /* HAWKING - Edimax */
{USB_DEVICE(0x1058, 0x0632), .driver_info = RTL8812}, /* WD - Cybertan */
@ -185,9 +186,7 @@ static struct usb_device_id rtw_usb_id_tbl[] = {
{USB_DEVICE(0x2357, 0x010D), .driver_info = RTL8812}, /* TP-Link - Archer T4U AC1300 */
{USB_DEVICE(0x2357, 0x010E), .driver_info = RTL8812}, /* TP-Link - Archer T4UH AC1300 */
{USB_DEVICE(0x2357, 0x010F), .driver_info = RTL8812}, /* TP-Link - T4UHP */
{USB_DEVICE(0x2357, 0x0122), .driver_info = RTL8812}, /* TP-Link - T4UHP (other) */
{USB_DEVICE(0x7392, 0xA822), .driver_info = RTL8812}, /* Edimax - Edimax */
{USB_DEVICE(0x0BDA, 0x8812), .driver_info = RTL8812}, /* Alfa - AWUS036AC, AWUS036ACH & AWUS036EAC */
#endif
#ifdef CONFIG_RTL8821A

4
os_dep/osdep_service.c
View File

@ -2023,8 +2023,10 @@ static int readFile(struct file *fp, char *buf, int len)
return -EPERM;
while (sum < len) {
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0))
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0) && LINUX_VERSION_CODE < KERNEL_VERSION(4, 14, 0))
rlen = __vfs_read(fp, buf + sum, len - sum, &fp->f_pos);
#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0))
rlen = kernel_read(fp, buf + sum, len - sum, &fp->f_pos);
#else
rlen = fp->f_op->read(fp, buf + sum, len - sum, &fp->f_pos);
#endif

17
rtl8812au.conf
View File

@ -1,17 +0,0 @@
# Place this file in directory /etc/modprobe.d/
# Uncomment one options line so when modprobe occurs either manually or
# automatically (e.g., after boot with wifi usb adapter connected) it
# will set that option value. Manual modprobe will override this file
# if option value also included at the command line, e.g.,
# $ sudo modprobe -r rtl8812au
# $ sudo modprobe rtl8812au rtw_led_ctrl=1
#
# Led always off
#options rtl8812au rtw_led_ctrl=0
#
# Default: normal blink of led (all options lines commented causes normal
# blink too).
options rtl8812au rtw_led_ctrl=1
#
# Led always on
#options rtl8812au rtw_led_ctrl=2

20
runwpa
View File

@ -1,20 +0,0 @@
#!/bin/bash
if [ "`which iwconfig`" = "" ] ; then
echo "WARNING:Wireless tool not exist!"
echo " Please install it!"
exit
else
if [ `uname -r | cut -d. -f2` -eq 4 ]; then
wpa_supplicant -D ipw -c wpa1.conf -i wlan0
else
if [ `iwconfig -v |awk '{print $4}' | head -n 1` -lt 18 ] ; then
wpa_supplicant -D ipw -c wpa1.conf -i wlan0
else
wpa_supplicant -D wext -c wpa1.conf -i wlan0
fi
fi
fi

16
wlan0dhcp
View File

@ -1,16 +0,0 @@
#!/bin/bash
var0=`ps aux|awk '/dhclient wlan0/'|awk '$11!="awk"{print $2}'`
kill $var0
cp ifcfg-wlan0 /etc/sysconfig/network-scripts/
dhclient wlan0
var1=`ifconfig wlan0 |awk '/inet/{print $2}'|awk -F: '{print $2}'`
rm -f /etc/sysconfig/network-scripts/ifcfg-wlan0
echo "get ip: $var1"