anthony
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rtl8812au
mirror of https://github.com/aircrack-ng/rtl8812au
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Add a bunch of VID/PID's + Add 8814/8821AU support

pull/821/head
kimocoder 2019-11-09 18:53:04 +00:00
parent a7279f8240
commit 7c9ab6fe6f
79 changed files with 67733 additions and 20 deletions
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6
Makefile
View File

@ -37,8 +37,8 @@ EXTRA_LDFLAGS += --strip-debug
########################## WIFI IC ############################
CONFIG_RTL8812A = y
CONFIG_RTL8821A = n
CONFIG_RTL8814A = n
CONFIG_RTL8821A = y
CONFIG_RTL8814A = y
######################### Interface ###########################
CONFIG_USB_HCI = y
########################## Features ###########################
@ -188,7 +188,7 @@ ifeq ($(CONFIG_PCI_HCI), y)
HCI_NAME = pci
endif
ifeq ($(CONFIG_RTL8812A)_$(CONFIG_RTL8821A)_$(CONFIG_RTL8814A), y_n_n)
ifeq ($(CONFIG_RTL8812A)_$(CONFIG_RTL8821A)_$(CONFIG_RTL8814A), y_y_y)
EXTRA_CFLAGS += -DDRV_NAME=\"rtl88xxau\"
ifeq ($(CONFIG_USB_HCI), y)

4
core/rtw_ap.c
View File

@ -2428,9 +2428,9 @@ int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len)
/* Parsing VHT OPERATION IE */
if (vht_cap == _TRUE
&& MLME_IS_MESH(padapter) /* allow only mesh temporarily before VHT IE checking is ready */
) {
rtw_check_for_vht20(padapter, ie + _BEACON_IE_OFFSET_, pbss_network->IELength - _BEACON_IE_OFFSET_);
if(MLME_IS_MESH(padapter)) /* allow only mesh temporarily before VHT IE checking is ready */
rtw_check_for_vht20(padapter, ie + _BEACON_IE_OFFSET_, pbss_network->IELength - _BEACON_IE_OFFSET_);
pmlmepriv->ori_vht_en = 1;
pmlmepriv->vhtpriv.vht_option = _TRUE;
} else if (REGSTY_IS_11AC_AUTO(pregistrypriv)) {

2
core/rtw_rf.c
View File

@ -1238,7 +1238,7 @@ exit:
void rtw_rf_set_tx_gain_offset(_adapter *adapter, u8 path, s8 offset)
{
#if !defined(CONFIG_RTL8814A) && !defined(CONFIG_RTL8822B) && !defined(CONFIG_RTL8821C)
#if defined(CONFIG_RTL8821A)
u8 write_value;
#endif
u8 target_path = 0;

2
dkms.conf
View File

@ -1,5 +1,5 @@
PACKAGE_NAME="realtek-rtl88xxau"
PACKAGE_VERSION="5.6.4.2~20191031"
PACKAGE_VERSION="5.6.4.2~20191108"
CLEAN="'make' clean"
BUILT_MODULE_NAME[0]=88XXau
PROCS_NUM=`nproc`

93
hal/efuse/rtl8814a/HalEfuseMask8814A_PCIE.c 100644
View File

@ -0,0 +1,93 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#include <drv_types.h>
#include "HalEfuseMask8814A_PCIE.h"
/******************************************************************************
* MPCIE.TXT
******************************************************************************/
u1Byte Array_MP_8814A_MPCIE[] = {
0xFF,
0xFF,
0xFF,
0xFF,
0xFF,
0xFF,
0xFF,
0xFF,
0xFF,
0xFF,
0xFF,
0xFF,
0xF3,
0xFF,
0x10,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
};
u2Byte
EFUSE_GetArrayLen_MP_8814A_MPCIE(VOID)
{
return sizeof(Array_MP_8814A_MPCIE)/sizeof(u1Byte);
}
VOID
EFUSE_GetMaskArray_MP_8814A_MPCIE(pu1Byte Array)
{
u2Byte len = EFUSE_GetArrayLen_MP_8814A_MPCIE(), i = 0;
for (i = 0; i < len; ++i)
Array[i] = Array_MP_8814A_MPCIE[i];
}
BOOLEAN
EFUSE_IsAddressMasked_MP_8814A_MPCIE(u2Byte Offset)
{
int r = Offset/16;
int c = (Offset%16) / 2;
int result = 0;
if (c < 4) /*Upper double word*/
result = (Array_MP_8814A_MPCIE[r] & (0x10 << c));
else
result = (Array_MP_8814A_MPCIE[r] & (0x01 << (c-4)));
return (result > 0) ? 0 : 1;
}

33
hal/efuse/rtl8814a/HalEfuseMask8814A_PCIE.h 100644
View File

@ -0,0 +1,33 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/******************************************************************************
* MPCIE.TXT
******************************************************************************/
u2Byte EFUSE_GetArrayLen_MP_8814A_MPCIE(VOID);
VOID EFUSE_GetMaskArray_MP_8814A_MPCIE(pu1Byte Array);
BOOLEAN EFUSE_IsAddressMasked_MP_8814A_MPCIE(u2Byte Offset);

90
hal/efuse/rtl8814a/HalEfuseMask8814A_USB.c 100644
View File

@ -0,0 +1,90 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#include <drv_types.h>
#include "HalEfuseMask8814A_USB.h"
/******************************************************************************
* MUSB.TXT
******************************************************************************/
u1Byte Array_MP_8814A_MUSB[] = {
0xFF,
0xFF,
0xFF,
0xFF,
0xFF,
0xFF,
0xFF,
0xFF,
0xFF,
0xFF,
0xFF,
0xFF,
0xF3,
0x7F,
0xFF,
0xFF,
0xFF,
0x70,
0x04,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
};
u2Byte EFUSE_GetArrayLen_MP_8814A_MUSB(VOID)
{
return sizeof(Array_MP_8814A_MUSB)/sizeof(u1Byte);
}
VOID EFUSE_GetMaskArray_MP_8814A_MUSB(pu1Byte Array)
{
u2Byte len = EFUSE_GetArrayLen_MP_8814A_MUSB(), i = 0;
for (i = 0; i < len; ++i)
Array[i] = Array_MP_8814A_MUSB[i];
}
BOOLEAN EFUSE_IsAddressMasked_MP_8814A_MUSB(u2Byte Offset)
{
int r = Offset/16;
int c = (Offset%16) / 2;
int result = 0;
if (c < 4) /*Upper double word*/
result = (Array_MP_8814A_MUSB[r] & (0x10 << c));
else
result = (Array_MP_8814A_MUSB[r] & (0x01 << (c-4)));
return (result > 0) ? 0 : 1;
}

33
hal/efuse/rtl8814a/HalEfuseMask8814A_USB.h 100644
View File

@ -0,0 +1,33 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/******************************************************************************
* MUSB.TXT
******************************************************************************/
u2Byte EFUSE_GetArrayLen_MP_8814A_MUSB(VOID);
VOID EFUSE_GetMaskArray_MP_8814A_MUSB(pu1Byte Array);
BOOLEAN EFUSE_IsAddressMasked_MP_8814A_MUSB(u2Byte Offset);

1754
hal/phydm/halrf/rtl8814a/halrf_8814a_ap.c 100644
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File diff suppressed because it is too large Load Diff

164
hal/phydm/halrf/rtl8814a/halrf_8814a_ap.h 100644
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@ -0,0 +1,164 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HAL_PHY_RF_8814A_H__
#define __HAL_PHY_RF_8814A_H__
/*--------------------------Define Parameters-------------------------------*/
#define IQK_DELAY_TIME_8814A 10 //ms
#define index_mapping_NUM_8814A 15
#define AVG_THERMAL_NUM_8814A 4
#define RF_T_METER_8814A 0x42
#define MAX_PATH_NUM_8814A 4
#include "../halphyrf_ap.h"
void ConfigureTxpowerTrack_8814A(
PTXPWRTRACK_CFG pConfig
);
VOID
GetDeltaSwingTable_8814A(
IN PDM_ODM_T pDM_Odm,
OUT pu1Byte *TemperatureUP_A,
OUT pu1Byte *TemperatureDOWN_A,
OUT pu1Byte *TemperatureUP_B,
OUT pu1Byte *TemperatureDOWN_B
);
VOID
GetDeltaSwingTable_8814A_PathCD(
IN PDM_ODM_T pDM_Odm,
OUT pu1Byte *TemperatureUP_C,
OUT pu1Byte *TemperatureDOWN_C,
OUT pu1Byte *TemperatureUP_D,
OUT pu1Byte *TemperatureDOWN_D
);
VOID
ConfigureTxpowerTrack_8814A(
IN PTXPWRTRACK_CFG pConfig
);
VOID
ODM_TxPwrTrackSetPwr8814A(
IN PDM_ODM_T pDM_Odm,
IN PWRTRACK_METHOD Method,
IN u1Byte RFPath,
IN u1Byte ChannelMappedIndex
);
u1Byte
CheckRFGainOffset(
PDM_ODM_T pDM_Odm,
PWRTRACK_METHOD Method,
u1Byte RFPath
);
//
// LC calibrate
//
void
PHY_LCCalibrate_8814A(
IN PDM_ODM_T pDM_Odm
);
void
phy_LCCalibrate_8814A(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN BOOLEAN is2T
);
//
// AP calibrate
//
void
PHY_APCalibrate_8814A(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN s1Byte delta);
void
PHY_DigitalPredistortion_8814A( IN PADAPTER pAdapter);
#if 0 //FOR_8814_IQK
VOID
_PHY_SaveADDARegisters(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN pu4Byte ADDAReg,
IN pu4Byte ADDABackup,
IN u4Byte RegisterNum
);
VOID
_PHY_PathADDAOn(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN pu4Byte ADDAReg,
IN BOOLEAN isPathAOn,
IN BOOLEAN is2T
);
VOID
_PHY_MACSettingCalibration(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN pu4Byte MACReg,
IN pu4Byte MACBackup
);
VOID
_PHY_PathAStandBy(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm
#else
IN PADAPTER pAdapter
#endif
);
#endif
#endif // #ifndef __HAL_PHY_RF_8814A_H__

564
hal/phydm/halrf/rtl8814a/halrf_8814a_ce.c 100644
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@ -0,0 +1,564 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#include "mp_precomp.h"
#include "../../phydm_precomp.h"
/*---------------------------Define Local Constant---------------------------*/
// 2010/04/25 MH Define the max tx power tracking tx agc power.
#define ODM_TXPWRTRACK_MAX_IDX_8814A 6
/*---------------------------Define Local Constant---------------------------*/
//3============================================================
//3 Tx Power Tracking
//3============================================================
// Add CheckRFGainOffset By YuChen to make sure that RF gain offset will not over upperbound 4'b1010
u8
CheckRFGainOffset(
struct dm_struct *pDM_Odm,
enum pwrtrack_method Method,
u8 RFPath
)
{
s1Byte UpperBound = 10, LowerBound = -5; // 4'b1010 = 10
s1Byte Final_RF_Index = 0;
BOOLEAN bPositive = FALSE;
u32 bitMask = 0;
u8 Final_OFDM_Swing_Index = 0, TxScalingUpperBound = 28, TxScalingLowerBound = 4;// upper bound +2dB, lower bound -10dB
struct dm_rf_calibration_struct * prf_calibrate_info = &(pDM_Odm->rf_calibrate_info);
if(Method == MIX_MODE) //normal Tx power tracking
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("is 8814 MP chip\n"));
bitMask = BIT19;
prf_calibrate_info->absolute_ofdm_swing_idx[RFPath] = prf_calibrate_info->absolute_ofdm_swing_idx[RFPath] + prf_calibrate_info->kfree_offset[RFPath];
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("=========================== [Path-%d] TXBB Offset============================\n", RFPath));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("absolute_ofdm_swing_idx[RFPath](%d) = absolute_ofdm_swing_idx[RFPath](%d) + kfree_offset[RFPath](%d), RFPath=%d\n", prf_calibrate_info->absolute_ofdm_swing_idx[RFPath], prf_calibrate_info->absolute_ofdm_swing_idx[RFPath], prf_calibrate_info->kfree_offset[RFPath], RFPath));
if (prf_calibrate_info->absolute_ofdm_swing_idx[RFPath] >= 0) /* check if RF_Index is positive or not*/
bPositive = TRUE;
else
bPositive = FALSE;
odm_set_rf_reg(pDM_Odm, RFPath, rRF_TxGainOffset, bitMask, bPositive);
bitMask = BIT18|BIT17|BIT16|BIT15;
Final_RF_Index = prf_calibrate_info->absolute_ofdm_swing_idx[RFPath] / 2; /*TxBB 1 step equal 1dB, BB swing 1step equal 0.5dB*/
}
if(Final_RF_Index > UpperBound) //Upper bound = 10dB, if more htan upper bound, then move to bb swing max = +2dB
{
odm_set_rf_reg(pDM_Odm, RFPath, rRF_TxGainOffset, bitMask, UpperBound); //set RF Reg0x55 per path
Final_OFDM_Swing_Index = prf_calibrate_info->default_ofdm_index + (prf_calibrate_info->absolute_ofdm_swing_idx[RFPath] - (UpperBound << 1));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Final_OFDM_Swing_Index(%d) = default_ofdm_index(%d) + (absolute_ofdm_swing_idx[RFPath](%d) - (UpperBound(%d) << 1)), RFPath=%d\n", Final_OFDM_Swing_Index, prf_calibrate_info->default_ofdm_index, prf_calibrate_info->absolute_ofdm_swing_idx[RFPath], UpperBound, RFPath));
if (Final_OFDM_Swing_Index > TxScalingUpperBound) { /* bb swing upper bound = +2dB */
Final_OFDM_Swing_Index = TxScalingUpperBound;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Final_OFDM_Swing_Index(%d) > TxScalingUpperBound(%d) Final_OFDM_Swing_Index = TxScalingUpperBound\n", Final_OFDM_Swing_Index, TxScalingUpperBound));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("===========================================================================\n"));
}
return Final_OFDM_Swing_Index;
}
else if(Final_RF_Index < LowerBound) // lower bound = -5dB
{
odm_set_rf_reg(pDM_Odm, RFPath, rRF_TxGainOffset, bitMask, (-1)*(LowerBound)); //set RF Reg0x55 per path
Final_OFDM_Swing_Index = prf_calibrate_info->default_ofdm_index - ((LowerBound<<1) - prf_calibrate_info->absolute_ofdm_swing_idx[RFPath]);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Final_OFDM_Swing_Index(%d) = default_ofdm_index(%d) - ((LowerBound(%d)<<1) - absolute_ofdm_swing_idx[RFPath](%d)), RFPath=%d\n", Final_OFDM_Swing_Index, prf_calibrate_info->default_ofdm_index, LowerBound, prf_calibrate_info->absolute_ofdm_swing_idx[RFPath], RFPath));
if (Final_OFDM_Swing_Index < TxScalingLowerBound) { /* BB swing lower bound = -10dB */
Final_OFDM_Swing_Index = TxScalingLowerBound;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Final_OFDM_Swing_Index(%d) > TxScalingLowerBound(%d) Final_OFDM_Swing_Index = TxScalingLowerBound\n", Final_OFDM_Swing_Index, TxScalingLowerBound));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("===========================================================================\n"));
}
return Final_OFDM_Swing_Index;
}
else // normal case
{
if(bPositive == TRUE)
odm_set_rf_reg(pDM_Odm, RFPath, rRF_TxGainOffset, bitMask, Final_RF_Index); //set RF Reg0x55 per path
else
odm_set_rf_reg(pDM_Odm, RFPath, rRF_TxGainOffset, bitMask, (-1)*Final_RF_Index); //set RF Reg0x55 per path
Final_OFDM_Swing_Index = prf_calibrate_info->default_ofdm_index + (prf_calibrate_info->absolute_ofdm_swing_idx[RFPath])%2;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Final_OFDM_Swing_Index(%d) = default_ofdm_index(%d) + (absolute_ofdm_swing_idx[RFPath])//2(%d), RFPath=%d\n", Final_OFDM_Swing_Index, prf_calibrate_info->default_ofdm_index, (prf_calibrate_info->absolute_ofdm_swing_idx[RFPath])%2, RFPath));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("===========================================================================\n"));
return Final_OFDM_Swing_Index;
}
return FALSE;
}
VOID
ODM_TxPwrTrackSetPwr8814A(
IN PVOID pDM_VOID,
enum pwrtrack_method Method,
u8 RFPath,
u8 ChannelMappedIndex
)
{
struct dm_struct * pDM_Odm = (struct dm_struct *)pDM_VOID;
PADAPTER Adapter = pDM_Odm->adapter;
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
struct dm_rf_calibration_struct * prf_calibrate_info = &(pDM_Odm->rf_calibrate_info);
u8 Final_OFDM_Swing_Index = 0;
if (Method == MIX_MODE)
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("prf_calibrate_info->default_ofdm_index=%d, prf_calibrate_info->absolute_ofdm_swing_idx[RFPath]=%d, RF_Path = %d\n",
prf_calibrate_info->default_ofdm_index, prf_calibrate_info->absolute_ofdm_swing_idx[RFPath], RFPath));
Final_OFDM_Swing_Index = CheckRFGainOffset(pDM_Odm, MIX_MODE, RFPath);
}
else if(Method == TSSI_MODE)
{
odm_set_rf_reg(pDM_Odm, RFPath, rRF_TxGainOffset, BIT18|BIT17|BIT16|BIT15, 0);
}
else if(Method == BBSWING) // use for mp driver clean power tracking status
{
prf_calibrate_info->absolute_ofdm_swing_idx[RFPath] = prf_calibrate_info->absolute_ofdm_swing_idx[RFPath] + prf_calibrate_info->kfree_offset[RFPath];
Final_OFDM_Swing_Index = prf_calibrate_info->default_ofdm_index + (prf_calibrate_info->absolute_ofdm_swing_idx[RFPath]);
odm_set_rf_reg(pDM_Odm, RFPath, rRF_TxGainOffset, BIT18|BIT17|BIT16|BIT15, 0);
}
if((Method == MIX_MODE) || (Method == BBSWING))
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("=========================== [Path-%d] BBSWING Offset============================\n", RFPath));
switch(RFPath)
{
case RF_PATH_A:
odm_set_bb_reg(pDM_Odm, rA_TxScale_Jaguar, 0xFFE00000, tx_scaling_table_jaguar[Final_OFDM_Swing_Index]); //set BBswing
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("******Path_A Compensate with BBSwing , Final_OFDM_Swing_Index = %d \n", Final_OFDM_Swing_Index));
break;
case RF_PATH_B:
odm_set_bb_reg(pDM_Odm, rB_TxScale_Jaguar, 0xFFE00000, tx_scaling_table_jaguar[Final_OFDM_Swing_Index]); //set BBswing
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("******Path_B Compensate with BBSwing , Final_OFDM_Swing_Index = %d \n", Final_OFDM_Swing_Index));
break;
case RF_PATH_C:
odm_set_bb_reg(pDM_Odm, rC_TxScale_Jaguar2, 0xFFE00000, tx_scaling_table_jaguar[Final_OFDM_Swing_Index]); //set BBswing
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("******Path_C Compensate with BBSwing , Final_OFDM_Swing_Index = %d \n", Final_OFDM_Swing_Index));
break;
case RF_PATH_D:
odm_set_bb_reg(pDM_Odm, rD_TxScale_Jaguar2, 0xFFE00000, tx_scaling_table_jaguar[Final_OFDM_Swing_Index]); //set BBswing
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("******Path_D Compensate with BBSwing , Final_OFDM_Swing_Index = %d \n", Final_OFDM_Swing_Index));
break;
default:
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("Wrong Path name!!!! \n"));
break;
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("===========================================================================\n"));
}
return;
} // ODM_TxPwrTrackSetPwr8814A
VOID
GetDeltaSwingTable_8814A(
IN PVOID pDM_VOID,
u8* *TemperatureUP_A,
u8* *TemperatureDOWN_A,
u8* *TemperatureUP_B,
u8* *TemperatureDOWN_B
)
{
struct dm_struct * pDM_Odm = (struct dm_struct *)pDM_VOID;
PADAPTER Adapter = pDM_Odm->adapter;
struct dm_rf_calibration_struct * prf_calibrate_info = &(pDM_Odm->rf_calibrate_info);
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
u8 TxRate = 0xFF;
u8 channel = pHalData->current_channel;
if (*(pDM_Odm->mp_mode) == TRUE) {
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
#if (MP_DRIVER == 1)
PMPT_CONTEXT pMptCtx = &(Adapter->mpt_ctx);
TxRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
#endif
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.mpt_ctx);
TxRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
#endif
#endif
} else {
u2Byte rate = *(pDM_Odm->forced_data_rate);
if (!rate) { /*auto rate*/
if (pDM_Odm->tx_rate != 0xFF) {
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->tx_rate);
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
TxRate = hw_rate_to_m_rate(pDM_Odm->tx_rate);
#endif
}
} else { /*force rate*/
TxRate = (u8)rate;
}
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate));
if (1 <= channel && channel <= 14) {
if (IS_CCK_RATE(TxRate)) {
*TemperatureUP_A = prf_calibrate_info->delta_swing_table_idx_2g_cck_a_p;
*TemperatureDOWN_A = prf_calibrate_info->delta_swing_table_idx_2g_cck_a_n;
*TemperatureUP_B = prf_calibrate_info->delta_swing_table_idx_2g_cck_b_p;
*TemperatureDOWN_B = prf_calibrate_info->delta_swing_table_idx_2g_cck_b_n;
} else {
*TemperatureUP_A = prf_calibrate_info->delta_swing_table_idx_2ga_p;
*TemperatureDOWN_A = prf_calibrate_info->delta_swing_table_idx_2ga_n;
*TemperatureUP_B = prf_calibrate_info->delta_swing_table_idx_2gb_p;
*TemperatureDOWN_B = prf_calibrate_info->delta_swing_table_idx_2gb_n;
}
} else if (36 <= channel && channel <= 64) {
*TemperatureUP_A = prf_calibrate_info->delta_swing_table_idx_5ga_p[0];
*TemperatureDOWN_A = prf_calibrate_info->delta_swing_table_idx_5ga_n[0];
*TemperatureUP_B = prf_calibrate_info->delta_swing_table_idx_5gb_p[0];
*TemperatureDOWN_B = prf_calibrate_info->delta_swing_table_idx_5gb_n[0];
} else if (100 <= channel && channel <= 144) {
*TemperatureUP_A = prf_calibrate_info->delta_swing_table_idx_5ga_p[1];
*TemperatureDOWN_A = prf_calibrate_info->delta_swing_table_idx_5ga_n[1];
*TemperatureUP_B = prf_calibrate_info->delta_swing_table_idx_5gb_p[1];
*TemperatureDOWN_B = prf_calibrate_info->delta_swing_table_idx_5gb_n[1];
} else if (149 <= channel && channel <= 173) {
*TemperatureUP_A = prf_calibrate_info->delta_swing_table_idx_5ga_p[2];
*TemperatureDOWN_A = prf_calibrate_info->delta_swing_table_idx_5ga_n[2];
*TemperatureUP_B = prf_calibrate_info->delta_swing_table_idx_5gb_p[2];
*TemperatureDOWN_B = prf_calibrate_info->delta_swing_table_idx_5gb_n[2];
} else {
*TemperatureUP_A = (u8*)delta_swing_table_idx_2ga_p_8188e;
*TemperatureDOWN_A = (u8*)delta_swing_table_idx_2ga_n_8188e;
*TemperatureUP_B = (u8*)delta_swing_table_idx_2ga_p_8188e;
*TemperatureDOWN_B = (u8*)delta_swing_table_idx_2ga_n_8188e;
}
return;
}
VOID
GetDeltaSwingTable_8814A_PathCD(
IN PVOID pDM_VOID,
u8* *TemperatureUP_C,
u8* *TemperatureDOWN_C,
u8* *TemperatureUP_D,
u8* *TemperatureDOWN_D
)
{
struct dm_struct * pDM_Odm = (struct dm_struct *)pDM_VOID;
PADAPTER Adapter = pDM_Odm->adapter;
struct dm_rf_calibration_struct * prf_calibrate_info = &(pDM_Odm->rf_calibrate_info);
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
u8 TxRate = 0xFF;
u8 channel = pHalData->current_channel;
if (*(pDM_Odm->mp_mode) == TRUE) {
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
#if (MP_DRIVER == 1)
PMPT_CONTEXT pMptCtx = &(Adapter->mpt_ctx);
TxRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
#endif
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.mpt_ctx);
TxRate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
#endif
#endif
} else {
u2Byte rate = *(pDM_Odm->forced_data_rate);
if (!rate) { /*auto rate*/
if (pDM_Odm->tx_rate != 0xFF) {
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->tx_rate);
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
TxRate = hw_rate_to_m_rate(pDM_Odm->tx_rate);
#endif
}
} else { /*force rate*/
TxRate = (u8)rate;
}
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate));
if ( 1 <= channel && channel <= 14) {
if (IS_CCK_RATE(TxRate)) {
*TemperatureUP_C = prf_calibrate_info->delta_swing_table_idx_2g_cck_c_p;
*TemperatureDOWN_C = prf_calibrate_info->delta_swing_table_idx_2g_cck_c_n;
*TemperatureUP_D = prf_calibrate_info->delta_swing_table_idx_2g_cck_d_p;
*TemperatureDOWN_D = prf_calibrate_info->delta_swing_table_idx_2g_cck_d_n;
} else {
*TemperatureUP_C = prf_calibrate_info->delta_swing_table_idx_2gc_p;
*TemperatureDOWN_C = prf_calibrate_info->delta_swing_table_idx_2gc_n;
*TemperatureUP_D = prf_calibrate_info->delta_swing_table_idx_2gd_p;
*TemperatureDOWN_D = prf_calibrate_info->delta_swing_table_idx_2gd_n;
}
} else if (36 <= channel && channel <= 64) {
*TemperatureUP_C = prf_calibrate_info->delta_swing_table_idx_5gc_p[0];
*TemperatureDOWN_C = prf_calibrate_info->delta_swing_table_idx_5gc_n[0];
*TemperatureUP_D = prf_calibrate_info->delta_swing_table_idx_5gd_p[0];
*TemperatureDOWN_D = prf_calibrate_info->delta_swing_table_idx_5gd_n[0];
} else if (100 <= channel && channel <= 144) {
*TemperatureUP_C = prf_calibrate_info->delta_swing_table_idx_5gc_p[1];
*TemperatureDOWN_C = prf_calibrate_info->delta_swing_table_idx_5gc_n[1];
*TemperatureUP_D = prf_calibrate_info->delta_swing_table_idx_5gd_p[1];
*TemperatureDOWN_D = prf_calibrate_info->delta_swing_table_idx_5gd_n[1];
} else if (149 <= channel && channel <= 173) {
*TemperatureUP_C = prf_calibrate_info->delta_swing_table_idx_5gc_p[2];
*TemperatureDOWN_C = prf_calibrate_info->delta_swing_table_idx_5gc_n[2];
*TemperatureUP_D = prf_calibrate_info->delta_swing_table_idx_5gd_p[2];
*TemperatureDOWN_D = prf_calibrate_info->delta_swing_table_idx_5gd_n[2];
} else {
*TemperatureUP_C = (u8*)delta_swing_table_idx_2ga_p_8188e;
*TemperatureDOWN_C = (u8*)delta_swing_table_idx_2ga_n_8188e;
*TemperatureUP_D = (u8*)delta_swing_table_idx_2ga_p_8188e;
*TemperatureDOWN_D = (u8*)delta_swing_table_idx_2ga_n_8188e;
}
return;
}
void configure_txpower_track_8814a(
struct txpwrtrack_cfg *pConfig
)
{
pConfig->swing_table_size_cck = CCK_TABLE_SIZE;
pConfig->swing_table_size_ofdm = OFDM_TABLE_SIZE;
pConfig->threshold_iqk = 8;
pConfig->average_thermal_num = AVG_THERMAL_NUM_8814A;
pConfig->rf_path_count = MAX_PATH_NUM_8814A;
pConfig->thermal_reg_addr = RF_T_METER_88E;
pConfig->odm_tx_pwr_track_set_pwr = ODM_TxPwrTrackSetPwr8814A;
pConfig->do_iqk = DoIQK_8814A;
pConfig->phy_lc_calibrate = phy_lc_calibrate_8814a;
pConfig->get_delta_swing_table = GetDeltaSwingTable_8814A;
pConfig->get_delta_swing_table8814only = GetDeltaSwingTable_8814A_PathCD;
}
VOID
_phy_lc_calibrate_8814a(
IN struct dm_struct * pDM_Odm,
IN BOOLEAN is2T
)
{
u32 /*RF_Amode=0, RF_Bmode=0,*/ LC_Cal = 0, tmp = 0, cnt;
//Check continuous TX and Packet TX
u32 reg0x914 = odm_read_4byte(pDM_Odm, rSingleTone_ContTx_Jaguar);;
// Backup RF reg18.
if((reg0x914 & 0x70000) == 0)
odm_write_1byte(pDM_Odm, REG_TXPAUSE, 0xFF);
//3 3. Read RF reg18
LC_Cal = odm_get_rf_reg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask);
//3 4. Set LC calibration begin bit15
odm_set_rf_reg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, 0x1b126);
ODM_delay_ms(100);
for (cnt = 0; cnt < 100; cnt++) {
if (odm_get_rf_reg(pDM_Odm, RF_PATH_A, RF_CHNLBW, 0x8000) != 0x1)
break;
ODM_delay_ms(10);
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("retry cnt = %d\n", cnt));
odm_set_rf_reg( pDM_Odm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, 0x13126);
odm_set_rf_reg( pDM_Odm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, 0x13124);
//3 Restore original situation
if((reg0x914 & 70000) == 0)
odm_write_1byte(pDM_Odm, REG_TXPAUSE, 0x00);
// Recover channel number
odm_set_rf_reg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, LC_Cal);
//DbgPrint("Call %s\n", __FUNCTION__);
}
VOID
phy_APCalibrate_8814A(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN struct dm_struct * pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN s1Byte delta,
IN BOOLEAN is2T
)
{
}
VOID
phy_lc_calibrate_8814a(
IN PVOID pDM_VOID
)
{
BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE;
struct dm_struct * pDM_Odm = (struct dm_struct *)pDM_VOID;
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
PADAPTER pAdapter = pDM_Odm->adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
#if (MP_DRIVER == 1)
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
PMPT_CONTEXT pMptCtx = &(pAdapter->mpt_ctx);
bStartContTx = pMptCtx->bStartContTx;
bSingleTone = pMptCtx->bSingleTone;
bCarrierSuppression = pMptCtx->bCarrierSuppression;
#else
PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
#endif
#endif
#endif
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> PHY_LCCalibrate_8814A\n"));
//#if (MP_DRIVER == 1)
_phy_lc_calibrate_8814a(pDM_Odm, TRUE);
//#endif
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== PHY_LCCalibrate_8814A\n"));
}
VOID
PHY_APCalibrate_8814A(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN struct dm_struct * pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN s1Byte delta
)
{
}
VOID
PHY_DPCalibrate_8814A(
IN struct dm_struct * pDM_Odm
)
{
}
BOOLEAN
phy_QueryRFPathSwitch_8814A(
IN PADAPTER pAdapter
)
{
return TRUE;
}
BOOLEAN PHY_QueryRFPathSwitch_8814A(
IN PADAPTER pAdapter
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
#if DISABLE_BB_RF
return TRUE;
#endif
return phy_QueryRFPathSwitch_8814A(pAdapter);
}
VOID _phy_SetRFPathSwitch_8814A(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN struct dm_struct * pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN BOOLEAN bMain,
IN BOOLEAN is2T
)
{
}
VOID phy_set_rf_path_switch_8814a(
#if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE))
IN struct dm_struct * pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN boolean bMain
)
{
}

112
hal/phydm/halrf/rtl8814a/halrf_8814a_ce.h 100644
View File

@ -0,0 +1,112 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HAL_PHY_RF_8814A_H__
#define __HAL_PHY_RF_8814A_H__
/*--------------------------Define Parameters-------------------------------*/
#define AVG_THERMAL_NUM_8814A 4
#define RF_T_METER_8814A 0x42
#include "../halphyrf_ce.h"
void configure_txpower_track_8814a(
struct txpwrtrack_cfg *pConfig
);
VOID
GetDeltaSwingTable_8814A(
IN PVOID pDM_VOID,
u8* *TemperatureUP_A,
u8* *TemperatureDOWN_A,
u8* *TemperatureUP_B,
u8* *TemperatureDOWN_B
);
VOID
GetDeltaSwingTable_8814A_PathCD(
IN PVOID pDM_VOID,
u8* *TemperatureUP_C,
u8* *TemperatureDOWN_C,
u8* *TemperatureUP_D,
u8* *TemperatureDOWN_D
);
VOID
ODM_TxPwrTrackSetPwr8814A(
IN PVOID pDM_VOID,
enum pwrtrack_method Method,
u8 RFPath,
u8 ChannelMappedIndex
);
u8
CheckRFGainOffset(
struct dm_struct *pDM_Odm,
enum pwrtrack_method Method,
u8 RFPath
);
VOID
phy_iq_calibrate_8814a(
IN PVOID pDM_VOID,
boolean bReCovery
);
//
// LC calibrate
//
void
phy_lc_calibrate_8814a(
IN PVOID pDM_VOID
);
//
// AP calibrate
//
void
PHY_APCalibrate_8814A(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
struct dm_struct * pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN s1Byte delta
);
VOID
PHY_DPCalibrate_8814A(
struct dm_struct * pDM_Odm
);
VOID phy_set_rf_path_switch_8814a(
#if ((DM_ODM_SUPPORT_TYPE & ODM_AP) || (DM_ODM_SUPPORT_TYPE == ODM_CE))
struct dm_struct * pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
boolean bMain
);
#endif // #ifndef __HAL_PHY_RF_8188E_H__

528
hal/phydm/halrf/rtl8814a/halrf_8814a_win.c 100644
View File

@ -0,0 +1,528 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#include "mp_precomp.h"
#include "../phydm_precomp.h"
#if (RTL8814A_SUPPORT == 1)
/*---------------------------Define Local Constant---------------------------*/
// 2010/04/25 MH Define the max tx power tracking tx agc power.
#define ODM_TXPWRTRACK_MAX_IDX_8814A 6
/*---------------------------Define Local Constant---------------------------*/
//3============================================================
//3 Tx Power Tracking
//3============================================================
// Add CheckRFGainOffset By YuChen to make sure that RF gain offset will not over upperbound 4'b1010
u1Byte
CheckRFGainOffset(
PDM_ODM_T pDM_Odm,
u1Byte RFPath
)
{
u1Byte UpperBound = 10; // 4'b1010 = 10
u1Byte Final_RF_Index = 0;
BOOLEAN bPositive = FALSE;
PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
if( pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] >= 0) // check if RF_Index is positive or not
{
Final_RF_Index = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] >> 1;
bPositive = TRUE;
ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)RFPath, rRF_TxGainOffset, BIT15, bPositive);
}
else
{
Final_RF_Index = (-1)*pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] >> 1;
bPositive = FALSE;
ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)RFPath, rRF_TxGainOffset, BIT15, bPositive);
}
if(bPositive == TRUE)
{
if(Final_RF_Index >= UpperBound)
{
ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)RFPath, rRF_TxGainOffset, 0xF0000, UpperBound); //set RF Reg0x55 per path
return UpperBound;
}
else
{
ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)RFPath, rRF_TxGainOffset, 0xF0000, Final_RF_Index); //set RF Reg0x55 per path
return Final_RF_Index;
}
}
else
{
ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)RFPath, rRF_TxGainOffset, 0xF0000, Final_RF_Index); //set RF Reg0x55 per path
return Final_RF_Index;
}
return FALSE;
}
VOID
ODM_TxPwrTrackSetPwr8814A(
PDM_ODM_T pDM_Odm,
PWRTRACK_METHOD Method,
u1Byte RFPath,
u1Byte ChannelMappedIndex
)
{
u1Byte Final_OFDM_Swing_Index = 0;
u1Byte Final_CCK_Swing_Index = 0;
u1Byte Final_RF_Index = 0;
u1Byte UpperBound = 10, TxScalingUpperBound = 28; // Upperbound = 4'b1010, TxScalingUpperBound = +2 dB
PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
if (Method == MIX_MODE)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("pRFCalibrateInfo->DefaultOfdmIndex=%d, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d, RF_Path = %d\n",
pRFCalibrateInfo->DefaultOfdmIndex, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], RFPath));
Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath];
Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath])%2;
Final_RF_Index = CheckRFGainOffset(pDM_Odm, RFPath); // check if Final_RF_Index >= 10
if((Final_RF_Index == UpperBound) && (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] >= 0)) // check BBSW is not over +2dB
{
Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] - (UpperBound << 1));
if(Final_OFDM_Swing_Index > TxScalingUpperBound)
Final_OFDM_Swing_Index = TxScalingUpperBound;
}
switch(RFPath)
{
case ODM_RF_PATH_A:
ODM_SetBBReg(pDM_Odm, rA_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[Final_OFDM_Swing_Index]); //set BBswing
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("******Path_A Compensate with BBSwing , Final_OFDM_Swing_Index = %d, Final_RF_Index = %d \n", Final_OFDM_Swing_Index, Final_RF_Index));
break;
case ODM_RF_PATH_B:
ODM_SetBBReg(pDM_Odm, rB_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[Final_OFDM_Swing_Index]); //set BBswing
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("******Path_B Compensate with BBSwing , Final_OFDM_Swing_Index = %d, Final_RF_Index = %d \n", Final_OFDM_Swing_Index, Final_RF_Index));
break;
case ODM_RF_PATH_C:
ODM_SetBBReg(pDM_Odm, rC_TxScale_Jaguar2, 0xFFE00000, TxScalingTable_Jaguar[Final_OFDM_Swing_Index]); //set BBswing
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("******Path_C Compensate with BBSwing , Final_OFDM_Swing_Index = %d, Final_RF_Index = %d \n", Final_OFDM_Swing_Index, Final_RF_Index));
break;
case ODM_RF_PATH_D:
ODM_SetBBReg(pDM_Odm, rD_TxScale_Jaguar2, 0xFFE00000, TxScalingTable_Jaguar[Final_OFDM_Swing_Index]); //set BBswing
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("******Path_D Compensate with BBSwing , Final_OFDM_Swing_Index = %d, Final_RF_Index = %d \n", Final_OFDM_Swing_Index, Final_RF_Index));
break;
default:
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("Wrong Path name!!!! \n"));
break;
}
}
return;
} // ODM_TxPwrTrackSetPwr8814A
VOID
GetDeltaSwingTable_8814A(
IN PDM_ODM_T pDM_Odm,
OUT pu1Byte *TemperatureUP_A,
OUT pu1Byte *TemperatureDOWN_A,
OUT pu1Byte *TemperatureUP_B,
OUT pu1Byte *TemperatureDOWN_B
)
{
PADAPTER Adapter = pDM_Odm->Adapter;
PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
u1Byte TxRate = 0xFF;
u1Byte channel = pHalData->CurrentChannel;
if (pDM_Odm->mp_mode == TRUE) {
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
#if (MP_DRIVER == 1)
PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx);
TxRate = MptToMgntRate(pMptCtx->MptRateIndex);
#endif
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx);
TxRate = MptToMgntRate(pMptCtx->MptRateIndex);
#endif
#endif
} else {
u2Byte rate = *(pDM_Odm->pForcedDataRate);
if (!rate) { /*auto rate*/
if (rate != 0xFF) {
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate);
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
TxRate = HwRateToMRate(pDM_Odm->TxRate);
#endif
}
} else { /*force rate*/
TxRate = (u1Byte)rate;
}
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate));
if (1 <= channel && channel <= 14) {
if (IS_CCK_RATE(TxRate)) {
*TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P;
*TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N;
*TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P;
*TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N;
} else {
*TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P;
*TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N;
*TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P;
*TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N;
}
} else if (36 <= channel && channel <= 64) {
*TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[0];
*TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[0];
*TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[0];
*TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[0];
} else if (100 <= channel && channel <= 144) {
*TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[1];
*TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[1];
*TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[1];
*TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[1];
} else if (149 <= channel && channel <= 173) {
*TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[2];
*TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[2];
*TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[2];
*TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[2];
} else {
*TemperatureUP_A = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E;
*TemperatureDOWN_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E;
*TemperatureUP_B = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E;
*TemperatureDOWN_B = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E;
}
return;
}
VOID
GetDeltaSwingTable_8814A_PathCD(
IN PDM_ODM_T pDM_Odm,
OUT pu1Byte *TemperatureUP_C,
OUT pu1Byte *TemperatureDOWN_C,
OUT pu1Byte *TemperatureUP_D,
OUT pu1Byte *TemperatureDOWN_D
)
{
PADAPTER Adapter = pDM_Odm->Adapter;
PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
u1Byte TxRate = 0xFF;
u1Byte channel = pHalData->CurrentChannel;
if (pDM_Odm->mp_mode == TRUE) {
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
#if (MP_DRIVER == 1)
PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx);
TxRate = MptToMgntRate(pMptCtx->MptRateIndex);
#endif
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx);
TxRate = MptToMgntRate(pMptCtx->MptRateIndex);
#endif
#endif
} else {
u2Byte rate = *(pDM_Odm->pForcedDataRate);
if (!rate) { /*auto rate*/
if (rate != 0xFF) {
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate);
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
TxRate = HwRateToMRate(pDM_Odm->TxRate);
#endif
}
} else { /*force rate*/
TxRate = (u1Byte)rate;
}
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate));
if ( 1 <= channel && channel <= 14) {
if (IS_CCK_RATE(TxRate)) {
*TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_P;
*TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_N;
*TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_P;
*TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_N;
} else {
*TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_2GC_P;
*TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_2GC_N;
*TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_2GD_P;
*TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_2GD_N;
}
} else if (36 <= channel && channel <= 64) {
*TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P[0];
*TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N[0];
*TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P[0];
*TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N[0];
} else if (100 <= channel && channel <= 144) {
*TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P[1];
*TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N[1];
*TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P[1];
*TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N[1];
} else if (149 <= channel && channel <= 173) {
*TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P[2];
*TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N[2];
*TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P[2];
*TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N[2];
} else {
*TemperatureUP_C = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E;
*TemperatureDOWN_C = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E;
*TemperatureUP_D = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E;
*TemperatureDOWN_D = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E;
}
return;
}
void ConfigureTxpowerTrack_8814A(
PTXPWRTRACK_CFG pConfig
)
{
pConfig->SwingTableSize_CCK = CCK_TABLE_SIZE;
pConfig->SwingTableSize_OFDM = OFDM_TABLE_SIZE;
pConfig->Threshold_IQK = 8;
pConfig->AverageThermalNum = AVG_THERMAL_NUM_8814A;
pConfig->RfPathCount = MAX_PATH_NUM_8814A;
pConfig->ThermalRegAddr = RF_T_METER_88E;
pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr8814A;
pConfig->DoIQK = DoIQK_8814A;
pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8814A;
pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8814A;
pConfig->GetDeltaSwingTable8814only = GetDeltaSwingTable_8814A_PathCD;
}
VOID
phy_LCCalibrate_8814A(
IN PDM_ODM_T pDM_Odm,
IN BOOLEAN is2T
)
{
u4Byte LC_Cal = 0, cnt;
//Check continuous TX and Packet TX
u4Byte reg0x914 = ODM_Read4Byte(pDM_Odm, rSingleTone_ContTx_Jaguar);;
// Backup RF reg18.
LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask);
if((reg0x914 & 0x70000) == 0)
ODM_Write1Byte(pDM_Odm, REG_TXPAUSE_8812A, 0xFF);
//3 3. Read RF reg18
LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask);
//3 4. Set LC calibration begin bit15
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, LC_Cal|0x08000);
ODM_delay_ms(100);
for (cnt = 0; cnt < 100; cnt++) {
if (ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x8000) != 0x1)
break;
ODM_delay_ms(10);
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("retry cnt = %d\n", cnt));
//3 Restore original situation
if((reg0x914 & 70000) == 0)
ODM_Write1Byte(pDM_Odm, REG_TXPAUSE_8812A, 0x00);
// Recover channel number
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, LC_Cal);
DbgPrint("Call %s\n", __FUNCTION__);
}
VOID
phy_APCalibrate_8814A(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN s1Byte delta,
IN BOOLEAN is2T
)
{
}
VOID
PHY_LCCalibrate_8814A(
IN PDM_ODM_T pDM_Odm
)
{
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
PADAPTER pAdapter = pDM_Odm->Adapter;
#if (MP_DRIVER == 1)
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx);
#else
PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
#endif
#endif
#endif
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> PHY_LCCalibrate_8814A\n"));
//#if (MP_DRIVER == 1)
phy_LCCalibrate_8814A(pDM_Odm, TRUE);
//#endif
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== PHY_LCCalibrate_8814A\n"));
}
VOID
PHY_APCalibrate_8814A(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN s1Byte delta
)
{
}
VOID
PHY_DPCalibrate_8814A(
IN PDM_ODM_T pDM_Odm
)
{
}
BOOLEAN
phy_QueryRFPathSwitch_8814A(
IN PADAPTER pAdapter
)
{
return TRUE;
}
BOOLEAN PHY_QueryRFPathSwitch_8814A(
IN PADAPTER pAdapter
)
{
#if DISABLE_BB_RF
return TRUE;
#endif
return phy_QueryRFPathSwitch_8814A(pAdapter);
}
VOID phy_SetRFPathSwitch_8814A(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN BOOLEAN bMain,
IN BOOLEAN is2T
)
{
}
VOID PHY_SetRFPathSwitch_8814A(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN BOOLEAN bMain
)
{
}
#else /* (RTL8814A_SUPPORT == 0)*/
VOID
PHY_LCCalibrate_8814A(
IN PDM_ODM_T pDM_Odm
){}
VOID
PHY_IQCalibrate_8814A(
IN PDM_ODM_T pDM_Odm,
IN BOOLEAN bReCovery
){}
#endif /* (RTL8814A_SUPPORT == 0)*/

106
hal/phydm/halrf/rtl8814a/halrf_8814a_win.h 100644
View File

@ -0,0 +1,106 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HAL_PHY_RF_8814A_H__
#define __HAL_PHY_RF_8814A_H__
/*--------------------------Define Parameters-------------------------------*/
#define AVG_THERMAL_NUM_8814A 4
#include "halphyrf_win.h"
void ConfigureTxpowerTrack_8814A(
PTXPWRTRACK_CFG pConfig
);
VOID
GetDeltaSwingTable_8814A(
IN PDM_ODM_T pDM_Odm,
OUT pu1Byte *TemperatureUP_A,
OUT pu1Byte *TemperatureDOWN_A,
OUT pu1Byte *TemperatureUP_B,
OUT pu1Byte *TemperatureDOWN_B
);
VOID
GetDeltaSwingTable_8814A_PathCD(
IN PDM_ODM_T pDM_Odm,
OUT pu1Byte *TemperatureUP_C,
OUT pu1Byte *TemperatureDOWN_C,
OUT pu1Byte *TemperatureUP_D,
OUT pu1Byte *TemperatureDOWN_D
);
VOID
ODM_TxPwrTrackSetPwr8814A(
PDM_ODM_T pDM_Odm,
PWRTRACK_METHOD Method,
u1Byte RFPath,
u1Byte ChannelMappedIndex
);
u1Byte
CheckRFGainOffset(
PDM_ODM_T pDM_Odm,
u1Byte RFPath
);
//
// LC calibrate
//
void
PHY_LCCalibrate_8814A(
IN PDM_ODM_T pDM_Odm
);
//
// AP calibrate
//
void
PHY_APCalibrate_8814A(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN s1Byte delta
);
VOID
PHY_DPCalibrate_8814A(
IN PDM_ODM_T pDM_Odm
);
VOID PHY_SetRFPathSwitch_8814A(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN BOOLEAN bMain
);
#endif // #ifndef __HAL_PHY_RF_8188E_H__

557
hal/phydm/halrf/rtl8814a/halrf_iqk_8814a.c 100644
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@ -0,0 +1,557 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#include "mp_precomp.h"
#include "../../phydm_precomp.h"
/*---------------------------Define Local Constant---------------------------*/
/*---------------------------Define Local Constant---------------------------*/
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
void DoIQK_8814A(
void* pDM_VOID,
u8 DeltaThermalIndex,
u8 ThermalValue,
u8 Threshold
)
{
struct dm_struct * pDM_Odm = (struct dm_struct *)pDM_VOID;
odm_reset_iqk_result(pDM_Odm);
pDM_Odm->rf_calibrate_info.thermal_value_iqk= ThermalValue;
phy_iq_calibrate_8814a(pDM_Odm, FALSE);
}
#else
/*Originally pConfig->DoIQK is hooked PHY_IQCalibrate_8814A, but DoIQK_8814A and PHY_IQCalibrate_8814A have different arguments*/
void DoIQK_8814A(
void* pDM_VOID,
u8 DeltaThermalIndex,
u8 ThermalValue,
u8 Threshold
)
{
struct dm_struct * pDM_Odm = (struct dm_struct *)pDM_VOID;
boolean bReCovery = (boolean) DeltaThermalIndex;
phy_iq_calibrate_8814a(pDM_Odm, bReCovery);
}
#endif
//1 7. IQK
VOID
_IQK_BackupMacBB_8814A(
IN struct dm_struct * pDM_Odm,
u32* MAC_backup,
u32* BB_backup,
u32* Backup_MAC_REG,
u32* Backup_BB_REG
)
{
u32 i;
//save MACBB default value
for (i = 0; i < MAC_REG_NUM_8814; i++){
MAC_backup[i] = odm_read_4byte(pDM_Odm, Backup_MAC_REG[i]);
}
for (i = 0; i < BB_REG_NUM_8814; i++){
BB_backup[i] = odm_read_4byte(pDM_Odm, Backup_BB_REG[i]);
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupMacBB Success!!!!\n"));
}
VOID
_IQK_BackupRF_8814A(
IN struct dm_struct * pDM_Odm,
u32 RF_backup[][4],
u32* Backup_RF_REG
)
{
u32 i;
//Save RF Parameters
for (i = 0; i < RF_REG_NUM_8814; i++){
RF_backup[i][RF_PATH_A] = odm_get_rf_reg(pDM_Odm, RF_PATH_A, Backup_RF_REG[i], bRFRegOffsetMask);
RF_backup[i][RF_PATH_B] = odm_get_rf_reg(pDM_Odm, RF_PATH_B, Backup_RF_REG[i], bRFRegOffsetMask);
RF_backup[i][RF_PATH_C] = odm_get_rf_reg(pDM_Odm, RF_PATH_C, Backup_RF_REG[i], bRFRegOffsetMask);
RF_backup[i][RF_PATH_D] = odm_get_rf_reg(pDM_Odm, RF_PATH_D, Backup_RF_REG[i], bRFRegOffsetMask);
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BackupRF Success!!!!\n"));
}
VOID
_IQK_AFESetting_8814A(
IN struct dm_struct * pDM_Odm,
IN boolean Do_IQK
)
{
if(Do_IQK)
{
// IQK AFE Setting RX_WAIT_CCA mode
odm_write_4byte(pDM_Odm, 0xc60, 0x0e808003);
odm_write_4byte(pDM_Odm, 0xe60, 0x0e808003);
odm_write_4byte(pDM_Odm, 0x1860, 0x0e808003);
odm_write_4byte(pDM_Odm, 0x1a60, 0x0e808003);
odm_set_bb_reg(pDM_Odm, 0x90c, BIT(13), 0x1);
odm_set_bb_reg(pDM_Odm, 0x764, BIT(10)|BIT(9), 0x3);
odm_set_bb_reg(pDM_Odm, 0x764, BIT(10)|BIT(9), 0x0);
odm_set_bb_reg(pDM_Odm, 0x804, BIT(2), 0x1);
odm_set_bb_reg(pDM_Odm, 0x804, BIT(2), 0x0);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("AFE IQK mode Success!!!!\n"));
}
else
{
odm_write_4byte(pDM_Odm, 0xc60, 0x07808003);
odm_write_4byte(pDM_Odm, 0xe60, 0x07808003);
odm_write_4byte(pDM_Odm, 0x1860, 0x07808003);
odm_write_4byte(pDM_Odm, 0x1a60, 0x07808003);
odm_set_bb_reg(pDM_Odm, 0x90c, BIT(13), 0x1);
odm_set_bb_reg(pDM_Odm, 0x764, BIT(10)|BIT(9), 0x3);
odm_set_bb_reg(pDM_Odm, 0x764, BIT(10)|BIT(9), 0x0);
odm_set_bb_reg(pDM_Odm, 0x804, BIT(2), 0x1);
odm_set_bb_reg(pDM_Odm, 0x804, BIT(2), 0x0);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("AFE Normal mode Success!!!!\n"));
}
}
VOID
_IQK_RestoreMacBB_8814A(
IN struct dm_struct * pDM_Odm,
u32* MAC_backup,
u32* BB_backup,
u32* Backup_MAC_REG,
u32* Backup_BB_REG
)
{
u32 i;
//Reload MacBB Parameters
for (i = 0; i < MAC_REG_NUM_8814; i++){
odm_write_4byte(pDM_Odm, Backup_MAC_REG[i], MAC_backup[i]);
}
for (i = 0; i < BB_REG_NUM_8814; i++){
odm_write_4byte(pDM_Odm, Backup_BB_REG[i], BB_backup[i]);
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreMacBB Success!!!!\n"));
}
VOID
_IQK_RestoreRF_8814A(
IN struct dm_struct * pDM_Odm,
u32* Backup_RF_REG,
u32 RF_backup[][4]
)
{
u32 i;
odm_set_rf_reg(pDM_Odm, RF_PATH_A, 0xef, bRFRegOffsetMask, 0x0);
odm_set_rf_reg(pDM_Odm, RF_PATH_B, 0xef, bRFRegOffsetMask, 0x0);
odm_set_rf_reg(pDM_Odm, RF_PATH_C, 0xef, bRFRegOffsetMask, 0x0);
odm_set_rf_reg(pDM_Odm, RF_PATH_D, 0xef, bRFRegOffsetMask, 0x0);
for (i = 0; i < RF_REG_NUM_8814; i++){
odm_set_rf_reg(pDM_Odm, RF_PATH_A, Backup_RF_REG[i], bRFRegOffsetMask, RF_backup[i][RF_PATH_A]);
odm_set_rf_reg(pDM_Odm, RF_PATH_B, Backup_RF_REG[i], bRFRegOffsetMask, RF_backup[i][RF_PATH_B]);
odm_set_rf_reg(pDM_Odm, RF_PATH_C, Backup_RF_REG[i], bRFRegOffsetMask, RF_backup[i][RF_PATH_C]);
odm_set_rf_reg(pDM_Odm, RF_PATH_D, Backup_RF_REG[i], bRFRegOffsetMask, RF_backup[i][RF_PATH_D]);
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("RestoreRF Success!!!!\n"));
}
VOID
PHY_ResetIQKResult_8814A(
IN struct dm_struct * pDM_Odm
)
{
odm_write_4byte(pDM_Odm, 0x1b00, 0xf8000000);
odm_write_4byte(pDM_Odm, 0x1b38, 0x20000000);
odm_write_4byte(pDM_Odm, 0x1b00, 0xf8000002);
odm_write_4byte(pDM_Odm, 0x1b38, 0x20000000);
odm_write_4byte(pDM_Odm, 0x1b00, 0xf8000004);
odm_write_4byte(pDM_Odm, 0x1b38, 0x20000000);
odm_write_4byte(pDM_Odm, 0x1b00, 0xf8000006);
odm_write_4byte(pDM_Odm, 0x1b38, 0x20000000);
odm_write_4byte(pDM_Odm, 0xc10, 0x100);
odm_write_4byte(pDM_Odm, 0xe10, 0x100);
odm_write_4byte(pDM_Odm, 0x1810, 0x100);
odm_write_4byte(pDM_Odm, 0x1a10, 0x100);
}
VOID
_IQK_ResetNCTL_8814A(
IN struct dm_struct * pDM_Odm
)
{
odm_write_4byte(pDM_Odm, 0x1b00, 0xf8000000);
odm_write_4byte(pDM_Odm, 0x1b80, 0x00000006);
odm_write_4byte(pDM_Odm, 0x1b00, 0xf8000000);
odm_write_4byte(pDM_Odm, 0x1b80, 0x00000002);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("ResetNCTL Success!!!!\n"));
}
VOID
_IQK_ConfigureMAC_8814A(
IN struct dm_struct * pDM_Odm
)
{
// ========MAC register setting========
odm_write_1byte(pDM_Odm, 0x522, 0x3f);
odm_set_bb_reg(pDM_Odm, 0x550, BIT(11)|BIT(3), 0x0);
odm_write_1byte(pDM_Odm, 0x808, 0x00); // RX ante off
odm_set_bb_reg(pDM_Odm, 0x838, 0xf, 0xe); // CCA off
odm_set_bb_reg(pDM_Odm, 0xa14, BIT(9)|BIT(8), 0x3); // CCK RX Path off
odm_write_4byte(pDM_Odm, 0xcb0, 0x77777777);
odm_write_4byte(pDM_Odm, 0xeb0, 0x77777777);
odm_write_4byte(pDM_Odm, 0x18b4, 0x77777777);
odm_write_4byte(pDM_Odm, 0x1ab4, 0x77777777);
odm_set_bb_reg(pDM_Odm, 0x1abc, 0x0ff00000, 0x77);
/*by YN*/
odm_set_bb_reg(pDM_Odm, 0xcbc, 0xf, 0x0);
}
VOID
_LOK_One_Shot(
IN void* pDM_VOID
)
{
struct dm_struct * pDM_Odm = (struct dm_struct *)pDM_VOID;
struct dm_iqk_info * pIQK_info = &pDM_Odm->IQK_info;
u8 Path = 0, delay_count = 0, ii;
boolean LOK_notready = FALSE;
u32 LOK_temp1 = 0, LOK_temp2 = 0;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("============ LOK ============\n"));
for(Path =0; Path <=3; Path++){
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
("==========S%d LOK ==========\n", Path));
odm_set_bb_reg(pDM_Odm, 0x9a4, BIT(21)|BIT(20), Path); // ADC Clock source
odm_write_4byte(pDM_Odm, 0x1b00, (0xf8000001|(1<<(4+Path)))); // LOK: CMD ID = 0 {0xf8000011, 0xf8000021, 0xf8000041, 0xf8000081}
ODM_delay_ms(LOK_delay);
delay_count = 0;
LOK_notready = TRUE;
while(LOK_notready){
LOK_notready = (boolean) odm_get_bb_reg(pDM_Odm, 0x1b00, BIT(0));
ODM_delay_ms(1);
delay_count++;
if(delay_count >= 10){
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
("S%d LOK timeout!!!\n", Path));
_IQK_ResetNCTL_8814A(pDM_Odm);
break;
}
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
("S%d ==> delay_count = 0x%d\n", Path, delay_count));
if(!LOK_notready){
odm_write_4byte(pDM_Odm, 0x1b00, 0xf8000000|(Path<<1));
odm_write_4byte(pDM_Odm, 0x1bd4, 0x003f0001);
LOK_temp2 = (odm_get_bb_reg(pDM_Odm, 0x1bfc, 0x003e0000)+0x10)&0x1f;
LOK_temp1 = (odm_get_bb_reg(pDM_Odm, 0x1bfc, 0x0000003e)+0x10)&0x1f;
for(ii = 1; ii<5; ii++){
LOK_temp1 = LOK_temp1 + ((LOK_temp1 & BIT(4-ii))<<(ii*2));
LOK_temp2 = LOK_temp2 + ((LOK_temp2 & BIT(4-ii))<<(ii*2));
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
("LOK_temp1 = 0x%x, LOK_temp2 = 0x%x\n", LOK_temp1>>4, LOK_temp2>>4));
odm_set_rf_reg(pDM_Odm, Path, 0x8, 0x07c00, LOK_temp1>>4);
odm_set_rf_reg(pDM_Odm, Path, 0x8, 0xf8000, LOK_temp2>>4);
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
("==>S%d fill LOK\n", Path));
}
else{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
("==>S%d LOK Fail!!!\n", Path));
odm_set_rf_reg(pDM_Odm, Path, 0x8, bRFRegOffsetMask, 0x08400);
}
pIQK_info->lok_fail[Path] = LOK_notready;
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
("LOK0_notready = %d, LOK1_notready = %d, LOK2_notready = %d, LOK3_notready = %d\n",
pIQK_info->lok_fail[0], pIQK_info->lok_fail[1], pIQK_info->lok_fail[2], pIQK_info->lok_fail[3]));
}
VOID
_IQK_One_Shot(
IN void* pDM_VOID
)
{
struct dm_struct * pDM_Odm = (struct dm_struct *)pDM_VOID;
struct dm_iqk_info * pIQK_info = &pDM_Odm->IQK_info;
u8 Path = 0, delay_count = 0, cal_retry = 0, idx;
boolean notready = TRUE, fail = TRUE;
u32 IQK_CMD;
u16 IQK_Apply[4] = {0xc94, 0xe94, 0x1894, 0x1a94};
for(idx = 0; idx <= 1; idx++){ // ii = 0:TXK , 1: RXK
if(idx == TX_IQK){
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
("============ WBTXIQK ============\n"));
}
else if(idx == RX_IQK){
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
("============ WBRXIQK ============\n"));
}
for(Path =0; Path <=3; Path++){
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
("==========S%d IQK ==========\n", Path));
cal_retry = 0;
fail = TRUE;
while(fail){
odm_set_bb_reg(pDM_Odm, 0x9a4, BIT(21)|BIT(20), Path);
if(idx == TX_IQK){
IQK_CMD = (0xf8000001|(*pDM_Odm->band_width+3)<<8|(1<<(4+Path)));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
("TXK_Trigger = 0x%x\n", IQK_CMD));
/*
{0xf8000311, 0xf8000321, 0xf8000341, 0xf8000381} ==> 20 WBTXK (CMD = 3)
{0xf8000411, 0xf8000421, 0xf8000441, 0xf8000481} ==> 40 WBTXK (CMD = 4)
{0xf8000511, 0xf8000521, 0xf8000541, 0xf8000581} ==> 80 WBTXK (CMD = 5)
*/
odm_write_4byte(pDM_Odm, 0x1b00, IQK_CMD);
}
else if(idx == RX_IQK){
IQK_CMD = (0xf8000001|(9-*pDM_Odm->band_width)<<8|(1<<(4+Path)));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
("TXK_Trigger = 0x%x\n", IQK_CMD));
/*
{0xf8000911, 0xf8000921, 0xf8000941, 0xf8000981} ==> 20 WBRXK (CMD = 9)
{0xf8000811, 0xf8000821, 0xf8000841, 0xf8000881} ==> 40 WBRXK (CMD = 8)
{0xf8000711, 0xf8000721, 0xf8000741, 0xf8000781} ==> 80 WBRXK (CMD = 7)
*/
odm_write_4byte(pDM_Odm, 0x1b00, IQK_CMD);
}
ODM_delay_ms(WBIQK_delay);
delay_count = 0;
notready = TRUE;
while(notready){
notready = (boolean) odm_get_bb_reg(pDM_Odm, 0x1b00, BIT(0));
if(!notready){
fail = (boolean) odm_get_bb_reg(pDM_Odm, 0x1b08, BIT(26));
break;
}
ODM_delay_ms(1);
delay_count++;
if(delay_count >= 20){
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
("S%d IQK timeout!!!\n", Path));
_IQK_ResetNCTL_8814A(pDM_Odm);
break;
}
}
if(fail)
cal_retry++;
if(cal_retry >3 )
break;
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
("S%d ==> 0x1b00 = 0x%x\n", Path, odm_read_4byte(pDM_Odm, 0x1b00)));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
("S%d ==> 0x1b08 = 0x%x\n", Path, odm_read_4byte(pDM_Odm, 0x1b08)));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
("S%d ==> delay_count = 0x%d, cal_retry = %x\n", Path, delay_count, cal_retry));
odm_write_4byte(pDM_Odm, 0x1b00, 0xf8000000|(Path<<1));
if(!fail){
if(idx == TX_IQK){
pIQK_info->iqc_matrix[idx][Path] = odm_read_4byte(pDM_Odm, 0x1b38);
}
else if(idx == RX_IQK){
odm_write_4byte(pDM_Odm, 0x1b3c, 0x20000000);
pIQK_info->iqc_matrix[idx][Path] = odm_read_4byte(pDM_Odm, 0x1b3c);
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_TRACE,
("S%d_IQC = 0x%x\n", Path, pIQK_info->iqc_matrix[idx][Path]));
}
if(idx == RX_IQK){
if(pIQK_info->iqk_fail[TX_IQK][Path] == FALSE) // TXIQK success in RXIQK
odm_write_4byte( pDM_Odm, 0x1b38, pIQK_info->iqc_matrix[TX_IQK][Path]);
else
odm_set_bb_reg(pDM_Odm, IQK_Apply[Path], BIT0, 0x0);
if(fail) // RXIQK Fail
odm_set_bb_reg(pDM_Odm, IQK_Apply[Path], (BIT11|BIT10), 0x0);
}
pIQK_info->iqk_fail[idx][Path] = fail;
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
("IQK0_fail = %d, IQK1_fail = %d, IQK2_fail = %d, IQK3_fail = %d\n",
pIQK_info->iqk_fail[idx][0], pIQK_info->iqk_fail[idx][1], pIQK_info->iqk_fail[idx][2], pIQK_info->iqk_fail[idx][3]));
}
}
VOID
_IQK_Tx_8814A(
IN struct dm_struct * pDM_Odm,
IN u8 chnlIdx
)
{
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BandWidth = %d, ExtPA2G = %d\n", *pDM_Odm->p_band_width, pDM_Odm->ext_pa));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Interface = %d, pBandType = %d\n", pDM_Odm->support_interface, *pDM_Odm->p_band_type));
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("CutVersion = %x\n", pDM_Odm->cut_version));
odm_set_rf_reg(pDM_Odm, RF_PATH_A, 0x58, BIT(19), 0x1);
odm_set_rf_reg(pDM_Odm, RF_PATH_B, 0x58, BIT(19), 0x1);
odm_set_rf_reg(pDM_Odm, RF_PATH_C, 0x58, BIT(19), 0x1);
odm_set_rf_reg(pDM_Odm, RF_PATH_D, 0x58, BIT(19), 0x1);
odm_set_bb_reg(pDM_Odm, 0xc94, (BIT11|BIT10|BIT0), 0x401);
odm_set_bb_reg(pDM_Odm, 0xe94, (BIT11|BIT10|BIT0), 0x401);
odm_set_bb_reg(pDM_Odm, 0x1894, (BIT11|BIT10|BIT0), 0x401);
odm_set_bb_reg(pDM_Odm, 0x1a94, (BIT11|BIT10|BIT0), 0x401);
if(*pDM_Odm->band_type == ODM_BAND_5G)
odm_write_4byte(pDM_Odm, 0x1b00, 0xf8000ff1);
else
odm_write_4byte(pDM_Odm, 0x1b00, 0xf8000ef1);
ODM_delay_ms(1);
odm_write_4byte(pDM_Odm, 0x810, 0x20101063);
odm_write_4byte(pDM_Odm, 0x90c, 0x0B00C000);
_LOK_One_Shot(pDM_Odm);
_IQK_One_Shot(pDM_Odm);
}
VOID
_phy_iq_calibrate_8814a(
IN struct dm_struct * pDM_Odm,
IN u8 Channel
)
{
u32 MAC_backup[MAC_REG_NUM_8814], BB_backup[BB_REG_NUM_8814], RF_backup[RF_REG_NUM_8814][4];
u32 Backup_MAC_REG[MAC_REG_NUM_8814] = {0x520, 0x550};
u32 Backup_BB_REG[BB_REG_NUM_8814] = {0xa14, 0x808, 0x838, 0x90c, 0x810, 0xcb0, 0xeb0,
0x18b4, 0x1ab4, 0x1abc, 0x9a4, 0x764, 0xcbc};
u32 Backup_RF_REG[RF_REG_NUM_8814] = {0x0, 0x8f};
u8 chnlIdx = odm_get_right_chnl_place_for_iqk(Channel);
_IQK_BackupMacBB_8814A(pDM_Odm, MAC_backup, BB_backup, Backup_MAC_REG, Backup_BB_REG);
_IQK_AFESetting_8814A(pDM_Odm,TRUE);
_IQK_BackupRF_8814A(pDM_Odm, RF_backup, Backup_RF_REG);
_IQK_ConfigureMAC_8814A(pDM_Odm);
_IQK_Tx_8814A(pDM_Odm, chnlIdx);
_IQK_ResetNCTL_8814A(pDM_Odm); //for 3-wire to BB use
_IQK_AFESetting_8814A(pDM_Odm,FALSE);
_IQK_RestoreMacBB_8814A(pDM_Odm, MAC_backup, BB_backup, Backup_MAC_REG, Backup_BB_REG);
_IQK_RestoreRF_8814A(pDM_Odm, Backup_RF_REG, RF_backup);
}
/*IQK version:v1.1*/
/*update 0xcbc setting*/
VOID
phy_iq_calibrate_8814a(
IN void* pDM_VOID,
IN boolean bReCovery
)
{
struct dm_struct * pDM_Odm = (struct dm_struct *)pDM_VOID;
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
PADAPTER pAdapter = pDM_Odm->adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
#if (MP_DRIVER == 1)
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx);
#else// (DM_ODM_SUPPORT_TYPE == ODM_CE)
PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.mpt_ctx);
#endif
#endif//(MP_DRIVER == 1)
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
if (odm_check_power_status(pAdapter) == FALSE)
return;
#endif
#if MP_DRIVER == 1
if( pMptCtx->is_single_tone || pMptCtx->is_carrier_suppression )
return;
#endif
#endif
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
_phy_iq_calibrate_8814a(pDM_Odm, pHalData->current_channel);
/*DBG_871X("%s,%d, do IQK %u ms\n", __func__, __LINE__, rtw_get_passing_time_ms(time_iqk));*/
#else
_phy_iq_calibrate_8814a(pDM_Odm, *pDM_Odm->pChannel);
#endif
}
VOID
PHY_IQCalibrate_8814A_Init(
IN void* pDM_VOID
)
{
struct dm_struct * pDM_Odm = (struct dm_struct *)pDM_VOID;
struct dm_iqk_info *pIQK_info = &pDM_Odm->IQK_info;
u8 ii, jj;
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("=====>PHY_IQCalibrate_8814A_Init\n"));
for(jj = 0; jj < 2; jj++){
for(ii = 0; ii < NUM; ii++){
pIQK_info->lok_fail[ii] = TRUE;
pIQK_info->iqk_fail[jj][ii] = TRUE;
pIQK_info->iqc_matrix[jj][ii] = 0x20000000;
}
}
}

58
hal/phydm/halrf/rtl8814a/halrf_iqk_8814a.h 100644
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@ -0,0 +1,58 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDM_IQK_8814A_H__
#define __PHYDM_IQK_8814A_H__
/*--------------------------Define Parameters-------------------------------*/
#define MAC_REG_NUM_8814 2
#define BB_REG_NUM_8814 13
#define RF_REG_NUM_8814 2
/*---------------------------End Define Parameters-------------------------------*/
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
VOID
DoIQK_8814A(
PVOID pDM_VOID,
u8 DeltaThermalIndex,
u8 ThermalValue,
u8 Threshold
);
#else
VOID
DoIQK_8814A(
PVOID pDM_VOID,
u8 DeltaThermalIndex,
u8 ThermalValue,
u8 Threshold
);
#endif
VOID
phy_iq_calibrate_8814a(
IN PVOID pDM_VOID,
boolean bReCovery
);
VOID
PHY_IQCalibrate_8814A_Init(
IN PVOID pDM_VOID
);
#endif /* #ifndef __PHYDM_IQK_8814A_H__*/

316
hal/phydm/halrf/rtl8821a/halrf_8821a_ce.c 100644
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@ -0,0 +1,316 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#include "mp_precomp.h"
#include "../../phydm_precomp.h"
/*---------------------------Define Local Constant---------------------------*/
/* 2010/04/25 MH Define the max tx power tracking tx agc power. */
#define ODM_TXPWRTRACK_MAX_IDX8821A 6
/*---------------------------Define Local Constant---------------------------*/
/* 3 ============================================================
* 3 Tx Power Tracking
* 3 ============================================================ */
void halrf_rf_lna_setting_8821a(
struct dm_struct *dm,
enum halrf_lna_set type
)
{
/*phydm_disable_lna*/
if (type == HALRF_LNA_DISABLE) {
odm_set_rf_reg(dm, RF_PATH_A, 0xef, 0x80000, 0x1);
odm_set_rf_reg(dm, RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
odm_set_rf_reg(dm, RF_PATH_A, 0x31, 0xfffff, 0x0002f);
odm_set_rf_reg(dm, RF_PATH_A, 0x32, 0xfffff, 0xfb09b); /*disable LNA*/
odm_set_rf_reg(dm, RF_PATH_A, 0xef, 0x80000, 0x0);
} else if (type == HALRF_LNA_ENABLE) {
odm_set_rf_reg(dm, RF_PATH_A, 0xef, 0x80000, 0x1);
odm_set_rf_reg(dm, RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/
odm_set_rf_reg(dm, RF_PATH_A, 0x31, 0xfffff, 0x0002f);
odm_set_rf_reg(dm, RF_PATH_A, 0x32, 0xfffff, 0xfb0bb); /*disable LNA*/
odm_set_rf_reg(dm, RF_PATH_A, 0xef, 0x80000, 0x0);
}
}
void
odm_tx_pwr_track_set_pwr8821a(
void *dm_void,
enum pwrtrack_method method,
u8 rf_path,
u8 channel_mapped_index
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _ADAPTER *adapter = dm->adapter;
PHAL_DATA_TYPE hal_data = GET_HAL_DATA(adapter);
u8 pwr_tracking_limit = 26; /* +1.0dB */
u8 tx_rate = 0xFF;
u8 final_ofdm_swing_index = 0;
u8 final_cck_swing_index = 0;
u8 i = 0;
u32 final_bb_swing_idx[1];
struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
struct _hal_rf_ *rf = &(dm->rf_table);
if (*(dm->mp_mode) == true) {
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
#if (MP_DRIVER == 1)
PMPT_CONTEXT p_mpt_ctx = &(adapter->mpt_ctx);
tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index);
#endif
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
#ifdef CONFIG_MP_INCLUDED
PMPT_CONTEXT p_mpt_ctx = &(adapter->mppriv.mpt_ctx);
tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index);
#endif
#endif
#endif
} else {
u16 rate = *(dm->forced_data_rate);
if (!rate) { /*auto rate*/
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
tx_rate = adapter->HalFunc.GetHwRateFromMRateHandler(dm->tx_rate);
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
if (dm->number_linked_client != 0)
tx_rate = hw_rate_to_m_rate(dm->tx_rate);
else
tx_rate = rf->p_rate_index;
#endif
} else /*force rate*/
tx_rate = (u8)rate;
}
//PHYDM_DBG(dm, DBG_COMP_MCC, "Power Tracking tx_rate=0x%X\n", tx_rate);
//PHYDM_DBG(dm, DBG_COMP_MCC, "===>odm_tx_pwr_track_set_pwr8821a\n");
if (tx_rate != 0xFF) {
/* 2 CCK */
if (((tx_rate >= MGN_1M) && (tx_rate <= MGN_5_5M)) || (tx_rate == MGN_11M))
pwr_tracking_limit = 32; /* +4dB */
/* 2 OFDM */
else if ((tx_rate >= MGN_6M) && (tx_rate <= MGN_48M))
pwr_tracking_limit = 30; /* +3dB */
else if (tx_rate == MGN_54M)
pwr_tracking_limit = 28; /* +2dB */
/* 2 HT */
else if ((tx_rate >= MGN_MCS0) && (tx_rate <= MGN_MCS2)) /* QPSK/BPSK */
pwr_tracking_limit = 34; /* +5dB */
else if ((tx_rate >= MGN_MCS3) && (tx_rate <= MGN_MCS4)) /* 16QAM */
pwr_tracking_limit = 30; /* +3dB */
else if ((tx_rate >= MGN_MCS5) && (tx_rate <= MGN_MCS7)) /* 64QAM */
pwr_tracking_limit = 28; /* +2dB */
/* 2 VHT */
else if ((tx_rate >= MGN_VHT1SS_MCS0) && (tx_rate <= MGN_VHT1SS_MCS2)) /* QPSK/BPSK */
pwr_tracking_limit = 34; /* +5dB */
else if ((tx_rate >= MGN_VHT1SS_MCS3) && (tx_rate <= MGN_VHT1SS_MCS4)) /* 16QAM */
pwr_tracking_limit = 30; /* +3dB */
else if ((tx_rate >= MGN_VHT1SS_MCS5) && (tx_rate <= MGN_VHT1SS_MCS6)) /* 64QAM */
pwr_tracking_limit = 28; /* +2dB */
else if (tx_rate == MGN_VHT1SS_MCS7) /* 64QAM */
pwr_tracking_limit = 26; /* +1dB */
else if (tx_rate == MGN_VHT1SS_MCS8) /* 256QAM */
pwr_tracking_limit = 24; /* +0dB */
else if (tx_rate == MGN_VHT1SS_MCS9) /* 256QAM */
pwr_tracking_limit = 22; /* -1dB */
else
pwr_tracking_limit = 24;
}
//PHYDM_DBG(dm, DBG_COMP_MCC, "tx_rate=0x%x, pwr_tracking_limit=%d\n", tx_rate, pwr_tracking_limit);
if (method == BBSWING) {
if (rf_path == RF_PATH_A) {
final_bb_swing_idx[RF_PATH_A] = (dm->rf_calibrate_info.OFDM_index[RF_PATH_A] > pwr_tracking_limit) ? pwr_tracking_limit : dm->rf_calibrate_info.OFDM_index[RF_PATH_A];
/*PHYDM_DBG(dm, DBG_COMP_MCC, "dm->rf_calibrate_info.OFDM_index[RF_PATH_A]=%d, dm->RealBbSwingIdx[RF_PATH_A]=%d\n",
dm->rf_calibrate_info.OFDM_index[RF_PATH_A], final_bb_swing_idx[RF_PATH_A]);*/
odm_set_bb_reg(dm, REG_A_TX_SCALE_JAGUAR, 0xFFE00000, tx_scaling_table_jaguar[final_bb_swing_idx[RF_PATH_A]]);
}
} else if (method == MIX_MODE) {
/*PHYDM_DBG(dm, DBG_COMP_MCC, "cali_info->default_ofdm_index=%d, cali_info->absolute_ofdm_swing_idx[rf_path]=%d, rf_path = %d\n",
cali_info->default_ofdm_index, cali_info->absolute_ofdm_swing_idx[rf_path], rf_path);*/
final_cck_swing_index = cali_info->default_cck_index + cali_info->absolute_ofdm_swing_idx[rf_path];
final_ofdm_swing_index = cali_info->default_ofdm_index + cali_info->absolute_ofdm_swing_idx[rf_path];
if (rf_path == RF_PATH_A) {
if (final_ofdm_swing_index > pwr_tracking_limit) { /*BBSwing higher then Limit*/
cali_info->remnant_cck_swing_idx = final_cck_swing_index - pwr_tracking_limit;
cali_info->remnant_ofdm_swing_idx[rf_path] = final_ofdm_swing_index - pwr_tracking_limit;
odm_set_bb_reg(dm, REG_A_TX_SCALE_JAGUAR, 0xFFE00000, tx_scaling_table_jaguar[pwr_tracking_limit]);
cali_info->modify_tx_agc_flag_path_a = true;
phy_set_tx_power_level_by_path(adapter, *dm->channel, RF_PATH_A);
//PHYDM_DBG(dm, DBG_COMP_MCC, "******Path_A Over BBSwing Limit, pwr_tracking_limit = %d, Remnant tx_agc value = %d\n", pwr_tracking_limit, cali_info->remnant_ofdm_swing_idx[rf_path]);
} else if (final_ofdm_swing_index <= 0) {
cali_info->remnant_cck_swing_idx = final_cck_swing_index;
cali_info->remnant_ofdm_swing_idx[rf_path] = final_ofdm_swing_index;
odm_set_bb_reg(dm, REG_A_TX_SCALE_JAGUAR, 0xFFE00000, tx_scaling_table_jaguar[0]);
cali_info->modify_tx_agc_flag_path_a = true;
phy_set_tx_power_level_by_path(adapter, *dm->channel, RF_PATH_A);
//PHYDM_DBG(dm, DBG_COMP_MCC, "******Path_A Lower then BBSwing lower bound 0, Remnant tx_agc value = %d\n", cali_info->remnant_ofdm_swing_idx[rf_path]);
} else {
odm_set_bb_reg(dm, REG_A_TX_SCALE_JAGUAR, 0xFFE00000, tx_scaling_table_jaguar[final_ofdm_swing_index]);
//PHYDM_DBG(dm, DBG_COMP_MCC, "******Path_A Compensate with BBSwing, final_ofdm_swing_index = %d\n", final_ofdm_swing_index);
if (cali_info->modify_tx_agc_flag_path_a) { /*If tx_agc has changed, reset tx_agc again*/
cali_info->remnant_cck_swing_idx = 0;
cali_info->remnant_ofdm_swing_idx[rf_path] = 0;
phy_set_tx_power_level_by_path(adapter, *dm->channel, RF_PATH_A);
cali_info->modify_tx_agc_flag_path_a = false;
PHYDM_DBG(dm, DBG_COMP_MCC, "******Path_A dm->Modify_TxAGC_Flag = false\n");
}
}
}
} else
return;
} /* odm_TxPwrTrackSetPwr88E */
void
get_delta_swing_table_8821a(
void *dm_void,
u8 **temperature_up_a,
u8 **temperature_down_a,
u8 **temperature_up_b,
u8 **temperature_down_b
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
struct _ADAPTER *adapter = dm->adapter;
struct dm_rf_calibration_struct *cali_info = &(dm->rf_calibrate_info);
struct _hal_rf_ *rf = &(dm->rf_table);
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
u8 tx_rate = 0xFF;
u8 channel = *dm->channel;
if (*(dm->mp_mode) == true) {
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
#if (MP_DRIVER == 1)
PMPT_CONTEXT p_mpt_ctx = &(adapter->mpt_ctx);
tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index);
#endif
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
#ifdef CONFIG_MP_INCLUDED
PMPT_CONTEXT p_mpt_ctx = &(adapter->mppriv.mpt_ctx);
tx_rate = mpt_to_mgnt_rate(p_mpt_ctx->mpt_rate_index);
#endif
#endif
#endif
} else {
u16 rate = *(dm->forced_data_rate);
if (!rate) { /*auto rate*/
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
tx_rate = adapter->HalFunc.GetHwRateFromMRateHandler(dm->tx_rate);
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
if (dm->number_linked_client != 0)
tx_rate = hw_rate_to_m_rate(dm->tx_rate);
else
tx_rate = rf->p_rate_index;
#endif
} else /*force rate*/
tx_rate = (u8)rate;
}
//PHYDM_DBG(dm, DBG_COMP_MCC, "Power Tracking tx_rate=0x%X\n", tx_rate);
if (1 <= channel && channel <= 14) {
if (IS_CCK_RATE(tx_rate)) {
*temperature_up_a = cali_info->delta_swing_table_idx_2g_cck_a_p;
*temperature_down_a = cali_info->delta_swing_table_idx_2g_cck_a_n;
*temperature_up_b = cali_info->delta_swing_table_idx_2g_cck_b_p;
*temperature_down_b = cali_info->delta_swing_table_idx_2g_cck_b_n;
} else {
*temperature_up_a = cali_info->delta_swing_table_idx_2ga_p;
*temperature_down_a = cali_info->delta_swing_table_idx_2ga_n;
*temperature_up_b = cali_info->delta_swing_table_idx_2gb_p;
*temperature_down_b = cali_info->delta_swing_table_idx_2gb_n;
}
} else if (36 <= channel && channel <= 64) {
*temperature_up_a = cali_info->delta_swing_table_idx_5ga_p[0];
*temperature_down_a = cali_info->delta_swing_table_idx_5ga_n[0];
*temperature_up_b = cali_info->delta_swing_table_idx_5gb_p[0];
*temperature_down_b = cali_info->delta_swing_table_idx_5gb_n[0];
} else if (100 <= channel && channel <= 144) {
*temperature_up_a = cali_info->delta_swing_table_idx_5ga_p[1];
*temperature_down_a = cali_info->delta_swing_table_idx_5ga_n[1];
*temperature_up_b = cali_info->delta_swing_table_idx_5gb_p[1];
*temperature_down_b = cali_info->delta_swing_table_idx_5gb_n[1];
} else if (149 <= channel && channel <= 177) {
*temperature_up_a = cali_info->delta_swing_table_idx_5ga_p[2];
*temperature_down_a = cali_info->delta_swing_table_idx_5ga_n[2];
*temperature_up_b = cali_info->delta_swing_table_idx_5gb_p[2];
*temperature_down_b = cali_info->delta_swing_table_idx_5gb_n[2];
} else {
*temperature_up_a = (u8 *)delta_swing_table_idx_2ga_p_8188e;
*temperature_down_a = (u8 *)delta_swing_table_idx_2ga_n_8188e;
*temperature_up_b = (u8 *)delta_swing_table_idx_2ga_p_8188e;
*temperature_down_b = (u8 *)delta_swing_table_idx_2ga_n_8188e;
}
return;
}
void configure_txpower_track_8821a(
struct txpwrtrack_cfg *config
)
{
config->swing_table_size_cck = TXSCALE_TABLE_SIZE;
config->swing_table_size_ofdm = TXSCALE_TABLE_SIZE;
config->threshold_iqk = IQK_THRESHOLD;
config->average_thermal_num = AVG_THERMAL_NUM_8812A;
config->rf_path_count = MAX_PATH_NUM_8821A;
config->thermal_reg_addr = RF_T_METER_8812A;
config->odm_tx_pwr_track_set_pwr = odm_tx_pwr_track_set_pwr8821a;
config->do_iqk = do_iqk_8821a;
config->phy_lc_calibrate = halrf_lck_trigger;
config->get_delta_swing_table = get_delta_swing_table_8821a;
}
void
phy_lc_calibrate_8821a(
void *dm_void
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
phy_lc_calibrate_8812a(dm);
}

53
hal/phydm/halrf/rtl8821a/halrf_8821a_ce.h 100644
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@ -0,0 +1,53 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __HAL_PHY_RF_8821A_H__
#define __HAL_PHY_RF_8821A_H__
/*--------------------------Define Parameters-------------------------------*/
void configure_txpower_track_8821a(
struct txpwrtrack_cfg *config
);
void
odm_tx_pwr_track_set_pwr8821a(
void *dm_void,
enum pwrtrack_method method,
u8 rf_path,
u8 channel_mapped_index
);
void
phy_lc_calibrate_8821a(
void *dm_void
);
void
get_delta_swing_table_8821a(
void *dm_void,
u8 **temperature_up_a,
u8 **temperature_down_a,
u8 **temperature_up_b,
u8 **temperature_down_b
);
void
halrf_rf_lna_setting_8821a(
struct dm_struct *dm,
enum halrf_lna_set type
);
#endif /* #ifndef __HAL_PHY_RF_8821A_H__ */

1046
hal/phydm/halrf/rtl8821a/halrf_8821a_win.c 100644
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File diff suppressed because it is too large Load Diff

72
hal/phydm/halrf/rtl8821a/halrf_8821a_win.h 100644
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@ -0,0 +1,72 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __HAL_PHY_RF_8821A_H__
#define __HAL_PHY_RF_8821A_H__
/*--------------------------Define Parameters-------------------------------*/
#define IQK_DELAY_TIME_8821A 10 /* ms */
#define index_mapping_NUM_8821A 15
#define AVG_THERMAL_NUM_8821A 4
#define RF_T_METER_8821A 0x42
void configure_txpower_track_8821a(
struct txpwrtrack_cfg *config
);
void do_iqk_8821a(
void *dm_void,
u8 delta_thermal_index,
u8 thermal_value,
u8 threshold
);
void
odm_tx_pwr_track_set_pwr8821a(
void *dm_void,
enum pwrtrack_method method,
u8 rf_path,
u8 channel_mapped_index
);
/* 1 7. IQK */
void
phy_iq_calibrate_8821a(
void *dm_void,
boolean is_recovery
);
void
phy_lc_calibrate_8821a(
IN void *dm_void
);
void
get_delta_swing_table_8821a(
void *dm_void,
u8 **temperature_up_a,
u8 **temperature_down_a,
u8 **temperature_up_b,
u8 **temperature_down_b
);
void
halrf_rf_lna_setting_8821a(
struct dm_struct *dm,
enum phydm_lna_set type
);
#endif /* #ifndef __HAL_PHY_RF_8821A_H__ */

731
hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ap.c 100644
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@ -0,0 +1,731 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#include "mp_precomp.h"
#include "../../phydm_precomp.h"
/*---------------------------Define Local Constant---------------------------*/
#define cal_num_8821A 3
#define MACBB_REG_NUM_8821A 8
#define AFE_REG_NUM_8821A 4
#define RF_REG_NUM_8821A 3
/*---------------------------Define Local Constant---------------------------*/
void _iqk_rx_fill_iqc_8821a(
struct dm_struct *dm,
enum rf_path path,
unsigned int RX_X,
unsigned int RX_Y
)
{
switch (path) {
case RF_PATH_A:
{
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
odm_set_bb_reg(dm, 0xc10, 0x000003ff, RX_X >> 1);
odm_set_bb_reg(dm, 0xc10, 0x03ff0000, (RX_Y >> 1) & 0x000003ff);
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "RX_X = %x;;RX_Y = %x ====>fill to IQC\n", RX_X >> 1, RX_Y >> 1);
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "0xc10 = %x ====>fill to IQC\n", odm_read_4byte(dm, 0xc10));
}
break;
default:
break;
};
}
void _iqk_tx_fill_iqc_8821a(
struct dm_struct *dm,
enum rf_path path,
unsigned int TX_X,
unsigned int TX_Y
)
{
switch (path) {
case RF_PATH_A:
{
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
odm_write_4byte(dm, 0xc90, 0x00000080);
odm_write_4byte(dm, 0xcc4, 0x20040000);
odm_write_4byte(dm, 0xcc8, 0x20000000);
odm_set_bb_reg(dm, 0xccc, 0x000007ff, TX_Y);
odm_set_bb_reg(dm, 0xcd4, 0x000007ff, TX_X);
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "TX_X = %x;;TX_Y = %x =====> fill to IQC\n", TX_X, TX_Y);
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "0xcd4 = %x;;0xccc = %x ====>fill to IQC\n", odm_get_bb_reg(dm, 0xcd4, 0x000007ff), odm_get_bb_reg(dm, 0xccc, 0x000007ff));
}
break;
default:
break;
};
}
void _iqk_backup_mac_bb_8821a(
struct dm_struct *dm,
u32 *MACBB_backup,
u32 *backup_macbb_reg,
u32 MACBB_NUM
)
{
u32 i;
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
/* save MACBB default value */
for (i = 0; i < MACBB_NUM; i++)
MACBB_backup[i] = odm_read_4byte(dm, backup_macbb_reg[i]);
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "BackupMacBB Success!!!!\n");
}
void _iqk_backup_rf_8821a(
struct dm_struct *dm,
u32 *RFA_backup,
u32 *RFB_backup,
u32 *backup_rf_reg,
u32 RF_NUM
)
{
u32 i;
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
/* Save RF Parameters */
for (i = 0; i < RF_NUM; i++)
RFA_backup[i] = odm_get_rf_reg(dm, RF_PATH_A, backup_rf_reg[i], MASKDWORD);
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "BackupRF Success!!!!\n");
}
void _iqk_backup_afe_8821a(
struct dm_struct *dm,
u32 *AFE_backup,
u32 *backup_afe_reg,
u32 AFE_NUM
)
{
u32 i;
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
/* Save AFE Parameters */
for (i = 0; i < AFE_NUM; i++)
AFE_backup[i] = odm_read_4byte(dm, backup_afe_reg[i]);
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "BackupAFE Success!!!!\n");
}
void _iqk_restore_mac_bb_8821a(
struct dm_struct *dm,
u32 *MACBB_backup,
u32 *backup_macbb_reg,
u32 MACBB_NUM
)
{
u32 i;
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
/* Reload MacBB Parameters */
for (i = 0; i < MACBB_NUM; i++)
odm_write_4byte(dm, backup_macbb_reg[i], MACBB_backup[i]);
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "RestoreMacBB Success!!!!\n");
}
void _iqk_restore_rf_8821a(
struct dm_struct *dm,
enum rf_path path,
u32 *backup_rf_reg,
u32 *RF_backup,
u32 RF_REG_NUM
)
{
u32 i;
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
for (i = 0; i < RF_REG_NUM; i++)
odm_set_rf_reg(dm, (enum rf_path)path, backup_rf_reg[i], RFREGOFFSETMASK, RF_backup[i]);
switch (path) {
case RF_PATH_A:
{
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "RestoreRF path A Success!!!!\n");
}
break;
default:
break;
}
}
void _iqk_restore_afe_8821a(
struct dm_struct *dm,
u32 *AFE_backup,
u32 *backup_afe_reg,
u32 AFE_NUM
)
{
u32 i;
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
/* Reload AFE Parameters */
for (i = 0; i < AFE_NUM; i++)
odm_write_4byte(dm, backup_afe_reg[i], AFE_backup[i]);
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
odm_write_4byte(dm, 0xc80, 0x0);
odm_write_4byte(dm, 0xc84, 0x0);
odm_write_4byte(dm, 0xc88, 0x0);
odm_write_4byte(dm, 0xc8c, 0x3c000000);
odm_write_4byte(dm, 0xc90, 0x00000080);
odm_write_4byte(dm, 0xc94, 0x00000000);
odm_write_4byte(dm, 0xcc4, 0x20040000);
odm_write_4byte(dm, 0xcc8, 0x20000000);
odm_write_4byte(dm, 0xcb8, 0x0);
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "RestoreAFE Success!!!!\n");
}
void _iqk_configure_mac_8821a(
struct dm_struct *dm
)
{
/* ========MAC register setting======== */
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
odm_write_1byte(dm, 0x522, 0x3f);
odm_set_bb_reg(dm, 0x550, BIT(11) | BIT(3), 0x0);
odm_write_1byte(dm, 0x808, 0x00); /* RX ante off */
odm_set_bb_reg(dm, 0x838, 0xf, 0xc); /* CCA off */
odm_write_1byte(dm, 0xa07, 0xf); /* CCK RX path off */
}
void _iqk_tx_8821a(
struct dm_struct *dm,
enum rf_path path
)
{
u32 TX_fail, RX_fail, delay_count, IQK_ready, cal_retry, cal = 0;
int TX_X = 0, TX_Y = 0, RX_X = 0, RX_Y = 0, tx_average = 0, rx_average = 0, rx_iqk_loop = 0, RX_X_temp = 0, RX_Y_temp = 0;
int TX_X0[cal_num_8821A], TX_Y0[cal_num_8821A], RX_X0[2][cal_num_8821A], RX_Y0[2][cal_num_8821A];
boolean TX0IQKOK = false, RX0IQKOK = false;
boolean VDF_enable = false;
int i, k, VDF_Y[3], VDF_X[3], tx_dt[3], ii, dx = 0, dy = 0, TX_finish = 0, RX_finish1 = 0, RX_finish2 = 0;
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "band_width = %d, support_interface = %d, ext_pa = %d, ext_pa_5g = %d\n", *dm->band_width, dm->support_interface, dm->ext_pa, dm->ext_pa_5g);
if (*dm->band_width == 2)
VDF_enable = true;
while (cal < cal_num_8821A) {
switch (path) {
case RF_PATH_A:
{
/* path-A LOK */
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
/* ========path-A AFE all on======== */
/* Port 0 DAC/ADC on */
odm_write_4byte(dm, 0xc60, 0x77777777);
odm_write_4byte(dm, 0xc64, 0x77777777);
odm_write_4byte(dm, 0xc68, 0x19791979);
odm_set_bb_reg(dm, 0xc00, 0xf, 0x4);/* hardware 3-wire off */
/* LOK setting */
/* ====== LOK ====== */
/* 1. DAC/ADC sampling rate (160 MHz) */
odm_set_bb_reg(dm, 0xc5c, BIT(26) | BIT(25) | BIT(24), 0x7);
/* 2. LoK RF setting (at BW = 20M) */
odm_set_rf_reg(dm, (enum rf_path)path, 0xef, RFREGOFFSETMASK, 0x80002);
odm_set_rf_reg(dm, (enum rf_path)path, 0x18, 0x00c00, 0x3);
odm_set_rf_reg(dm, (enum rf_path)path, 0x30, RFREGOFFSETMASK, 0x20000);
odm_set_rf_reg(dm, (enum rf_path)path, 0x31, RFREGOFFSETMASK, 0x0003f);
odm_set_rf_reg(dm, (enum rf_path)path, 0x32, RFREGOFFSETMASK, 0xf3fc3);
odm_set_rf_reg(dm, (enum rf_path)path, 0x65, RFREGOFFSETMASK, 0x931d5);
odm_set_rf_reg(dm, (enum rf_path)path, 0x8f, RFREGOFFSETMASK, 0x8a001);
odm_write_4byte(dm, 0x90c, 0x00008000);
odm_set_bb_reg(dm, 0xc94, BIT(0), 0x1);
odm_write_4byte(dm, 0x978, 0x29002000);/* TX (X,Y) */
odm_write_4byte(dm, 0x97c, 0xa9002000);/* RX (X,Y) */
odm_write_4byte(dm, 0x984, 0x00462910);/* [0]:AGC_en, [15]:idac_K_Mask */
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
if (dm->ext_pa_5g)
odm_write_4byte(dm, 0xc88, 0x821403f7);
else
odm_write_4byte(dm, 0xc88, 0x821403f4);
if (*dm->band_type == ODM_BAND_5G)
odm_write_4byte(dm, 0xc8c, 0x68163e96);
else
odm_write_4byte(dm, 0xc8c, 0x28163e96);
odm_write_4byte(dm, 0xc80, 0x18008c10);/* TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
odm_write_4byte(dm, 0xc84, 0x38008c10);/* RX_Tone_idx[9:0], RxK_Mask[29] */
odm_write_4byte(dm, 0xcb8, 0x00100000);/* cb8[20] 將 SI/PI 使用權切給 iqk_dpk module */
odm_write_4byte(dm, 0x980, 0xfa000000);
odm_write_4byte(dm, 0x980, 0xf8000000);
ODM_delay_ms(10); /* delay 10ms */
odm_write_4byte(dm, 0xcb8, 0x00000000);
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
odm_set_rf_reg(dm, (enum rf_path)path, 0x58, 0x7fe00,
odm_get_rf_reg(dm, (enum rf_path)path, 0x8, 0xffc00));
switch (*dm->band_width) {
case 1:
{
odm_set_rf_reg(dm, (enum rf_path)path, 0x18, 0x00c00, 0x1);
}
break;
case 2:
{
odm_set_rf_reg(dm, (enum rf_path)path, 0x18, 0x00c00, 0x0);
}
break;
default:
break;
}
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
/* 3. TX RF setting */
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
odm_set_rf_reg(dm, (enum rf_path)path, 0xef, RFREGOFFSETMASK, 0x80000);
odm_set_rf_reg(dm, (enum rf_path)path, 0x30, RFREGOFFSETMASK, 0x20000);
odm_set_rf_reg(dm, (enum rf_path)path, 0x31, RFREGOFFSETMASK, 0x0003f);
odm_set_rf_reg(dm, (enum rf_path)path, 0x32, RFREGOFFSETMASK, 0xf3fc3);
odm_set_rf_reg(dm, (enum rf_path)path, 0x65, RFREGOFFSETMASK, 0x931d5);
odm_set_rf_reg(dm, (enum rf_path)path, 0x8f, RFREGOFFSETMASK, 0x8a001);
odm_set_rf_reg(dm, (enum rf_path)path, 0xef, RFREGOFFSETMASK, 0x00000);
odm_write_4byte(dm, 0x90c, 0x00008000);
odm_set_bb_reg(dm, 0xc94, BIT(0), 0x1);
odm_write_4byte(dm, 0x978, 0x29002000);/* TX (X,Y) */
odm_write_4byte(dm, 0x97c, 0xa9002000);/* RX (X,Y) */
odm_write_4byte(dm, 0x984, 0x0046a910);/* [0]:AGC_en, [15]:idac_K_Mask */
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
if (dm->ext_pa_5g)
odm_write_4byte(dm, 0xc88, 0x821403f7);
else
odm_write_4byte(dm, 0xc88, 0x821403e3);
if (*dm->band_type == ODM_BAND_5G)
odm_write_4byte(dm, 0xc8c, 0x40163e96);
else
odm_write_4byte(dm, 0xc8c, 0x00163e96);
if (VDF_enable == 1) {
for (k = 0; k <= 2; k++) {
switch (k) {
case 0:
{
odm_write_4byte(dm, 0xc80, 0x18008c38);/* TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
odm_write_4byte(dm, 0xc84, 0x38008c38);/* RX_Tone_idx[9:0], RxK_Mask[29] */
odm_set_bb_reg(dm, 0xce8, BIT(31), 0x0);
}
break;
case 1:
{
odm_set_bb_reg(dm, 0xc80, BIT(28), 0x0);
odm_set_bb_reg(dm, 0xc84, BIT(28), 0x0);
odm_set_bb_reg(dm, 0xce8, BIT(31), 0x0);
}
break;
case 2:
{
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "VDF_Y[1] = %x;;;VDF_Y[0] = %x\n", VDF_Y[1] >> 21 & 0x00007ff, VDF_Y[0] >> 21 & 0x00007ff);
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "VDF_X[1] = %x;;;VDF_X[0] = %x\n", VDF_X[1] >> 21 & 0x00007ff, VDF_X[0] >> 21 & 0x00007ff);
tx_dt[cal] = (VDF_Y[1] >> 20) - (VDF_Y[0] >> 20);
tx_dt[cal] = ((16 * tx_dt[cal]) * 10000 / 15708);
tx_dt[cal] = (tx_dt[cal] >> 1) + (tx_dt[cal] & BIT(0));
odm_write_4byte(dm, 0xc80, 0x18008c20);/* TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
odm_write_4byte(dm, 0xc84, 0x38008c20);/* RX_Tone_idx[9:0], RxK_Mask[29] */
odm_set_bb_reg(dm, 0xce8, BIT(31), 0x1);
odm_set_bb_reg(dm, 0xce8, 0x3fff0000, tx_dt[cal] & 0x00003fff);
}
break;
}
odm_write_4byte(dm, 0xcb8, 0x00100000);/* cb8[20] 將 SI/PI 使用權切給 iqk_dpk module */
cal_retry = 0;
while (1) {
/* one shot */
odm_write_4byte(dm, 0x980, 0xfa000000);
odm_write_4byte(dm, 0x980, 0xf8000000);
ODM_delay_ms(10); /* delay 10ms */
odm_write_4byte(dm, 0xcb8, 0x00000000);
delay_count = 0;
while (1) {
IQK_ready = odm_get_bb_reg(dm, 0xd00, BIT(10));
if ((~IQK_ready) || (delay_count > 20))
break;
else {
ODM_delay_ms(1);
delay_count++;
}
}
if (delay_count < 20) { /* If 20ms No Result, then cal_retry++ */
/* ============TXIQK Check============== */
TX_fail = odm_get_bb_reg(dm, 0xd00, BIT(12));
if (~TX_fail) {
odm_write_4byte(dm, 0xcb8, 0x02000000);
VDF_X[k] = odm_get_bb_reg(dm, 0xd00, 0x07ff0000) << 21;
odm_write_4byte(dm, 0xcb8, 0x04000000);
VDF_Y[k] = odm_get_bb_reg(dm, 0xd00, 0x07ff0000) << 21;
TX0IQKOK = true;
break;
} else {
odm_set_bb_reg(dm, 0xccc, 0x000007ff, 0x0);
odm_set_bb_reg(dm, 0xcd4, 0x000007ff, 0x200);
TX0IQKOK = false;
cal_retry++;
if (cal_retry == 10)
break;
}
} else {
TX0IQKOK = false;
cal_retry++;
if (cal_retry == 10)
break;
}
}
}
if (k == 3) {
TX_X0[cal] = VDF_X[k - 1] ;
TX_Y0[cal] = VDF_Y[k - 1];
}
} else {
odm_write_4byte(dm, 0xc80, 0x18008c10);/* TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
odm_write_4byte(dm, 0xc84, 0x38008c10);/* RX_Tone_idx[9:0], RxK_Mask[29] */
odm_write_4byte(dm, 0xcb8, 0x00100000);/* cb8[20] 將 SI/PI 使用權切給 iqk_dpk module */
cal_retry = 0;
while (1) {
/* one shot */
odm_write_4byte(dm, 0x980, 0xfa000000);
odm_write_4byte(dm, 0x980, 0xf8000000);
ODM_delay_ms(10); /* delay 10ms */
odm_write_4byte(dm, 0xcb8, 0x00000000);
delay_count = 0;
while (1) {
IQK_ready = odm_get_bb_reg(dm, 0xd00, BIT(10));
if ((~IQK_ready) || (delay_count > 20))
break;
else {
ODM_delay_ms(1);
delay_count++;
}
}
if (delay_count < 20) { /* If 20ms No Result, then cal_retry++ */
/* ============TXIQK Check============== */
TX_fail = odm_get_bb_reg(dm, 0xd00, BIT(12));
if (~TX_fail) {
odm_write_4byte(dm, 0xcb8, 0x02000000);
TX_X0[cal] = odm_get_bb_reg(dm, 0xd00, 0x07ff0000) << 21;
odm_write_4byte(dm, 0xcb8, 0x04000000);
TX_Y0[cal] = odm_get_bb_reg(dm, 0xd00, 0x07ff0000) << 21;
TX0IQKOK = true;
break;
} else {
odm_set_bb_reg(dm, 0xccc, 0x000007ff, 0x0);
odm_set_bb_reg(dm, 0xcd4, 0x000007ff, 0x200);
TX0IQKOK = false;
cal_retry++;
if (cal_retry == 10)
break;
}
} else {
TX0IQKOK = false;
cal_retry++;
if (cal_retry == 10)
break;
}
}
}
if (TX0IQKOK == false)
break; /* TXK fail, Don't do RXK */
/* ====== RX IQK ====== */
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
/* 1. RX RF setting */
odm_set_rf_reg(dm, (enum rf_path)path, 0xef, RFREGOFFSETMASK, 0x80000);
odm_set_rf_reg(dm, (enum rf_path)path, 0x30, RFREGOFFSETMASK, 0x30000);
odm_set_rf_reg(dm, (enum rf_path)path, 0x31, RFREGOFFSETMASK, 0x0002f);
odm_set_rf_reg(dm, (enum rf_path)path, 0x32, RFREGOFFSETMASK, 0xfffbb);
odm_set_rf_reg(dm, (enum rf_path)path, 0x8f, RFREGOFFSETMASK, 0x88001);
odm_set_rf_reg(dm, (enum rf_path)path, 0x65, RFREGOFFSETMASK, 0x931d8);
odm_set_rf_reg(dm, (enum rf_path)path, 0xef, RFREGOFFSETMASK, 0x00000);
if ((get_bonding_type_8881A() == BOND_8881AM) && (dm->ext_pa_5g) && (dm->ext_lna_5g)) {
odm_set_rf_reg(dm, (enum rf_path)path, 0xdf, 0x00800, 0x1);
odm_set_rf_reg(dm, (enum rf_path)path, 0x56, 0x003e0, 0x1);
}
odm_set_bb_reg(dm, 0x978, 0x03FF8000, (TX_X0[cal]) >> 21 & 0x000007ff);
odm_set_bb_reg(dm, 0x978, 0x000007FF, (TX_Y0[cal]) >> 21 & 0x000007ff);
odm_set_bb_reg(dm, 0x978, BIT(31), 0x1);
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "0x978 = 0x%x\n", odm_get_bb_reg(dm, 0x978, MASKDWORD));
odm_set_bb_reg(dm, 0x97c, BIT(31), 0x0);
odm_write_4byte(dm, 0x90c, 0x00008000);
odm_write_4byte(dm, 0x984, 0x0046a911);
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
odm_write_4byte(dm, 0xc80, 0x38008c10);/* TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
odm_write_4byte(dm, 0xc84, 0x18008c10);/* RX_Tone_idx[9:0], RxK_Mask[29] */
odm_write_4byte(dm, 0xc88, 0x02140119);
if (dm->support_interface == 1) {
rx_iqk_loop = 2; /* for 2% fail; */
} else
rx_iqk_loop = 1;
for (i = 0; i < rx_iqk_loop; i++) {
if (dm->support_interface == 1)
if (i == 0) {
if ((get_bonding_type_8881A() == BOND_8881AM) && (dm->ext_pa_5g) && (dm->ext_lna_5g))
odm_write_4byte(dm, 0xc8c, 0x28161800); /* Good */
else
odm_write_4byte(dm, 0xc8c, 0x28161100);
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "0xc8c (i=0) = 0x%x\n", odm_get_bb_reg(dm, 0xc8c, MASKDWORD));
} else {
if ((get_bonding_type_8881A() == BOND_8881AM) && (dm->ext_pa_5g) && (dm->ext_lna_5g))
odm_write_4byte(dm, 0xc8c, 0x28160c00);
else
odm_write_4byte(dm, 0xc8c, 0x28160d00);
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "0xc8c = 0x%x\n", odm_get_bb_reg(dm, 0xc8c, MASKDWORD));
}
else
odm_write_4byte(dm, 0xc8c, 0x28160d00);
odm_write_4byte(dm, 0xcb8, 0x00100000);/* cb8[20] 將 SI/PI 使用權切給 iqk_dpk module */
cal_retry = 0;
while (1) {
/* one shot */
odm_write_4byte(dm, 0x980, 0xfa000000);
odm_write_4byte(dm, 0x980, 0xf8000000);
ODM_delay_ms(10); /* delay 10ms */
odm_write_4byte(dm, 0xcb8, 0x00000000);
delay_count = 0;
while (1) {
IQK_ready = odm_get_bb_reg(dm, 0xd00, BIT(10));
if ((~IQK_ready) || (delay_count > 20))
break;
else {
ODM_delay_ms(1);
delay_count++;
}
}
odm_set_rf_reg(dm, RF_PATH_A, 0xdf, 0x00800, 0x0);
if (delay_count < 20) { /* If 20ms No Result, then cal_retry++ */
/* ============RXIQK Check============== */
RX_fail = odm_get_bb_reg(dm, 0xd00, BIT(11));
if (RX_fail == 0) {
/*
dbg_print("====== RXIQK (%d) ======", i);
odm_write_4byte(dm, 0xcb8, 0x05000000);
reg1 = odm_get_bb_reg(dm, 0xd00, 0xffffffff);
odm_write_4byte(dm, 0xcb8, 0x06000000);
reg2 = odm_get_bb_reg(dm, 0xd00, 0x0000001f);
dbg_print("reg1 = %d, reg2 = %d", reg1, reg2);
image_power = (reg2<<32)+reg1;
dbg_print("Before PW = %d\n", image_power);
odm_write_4byte(dm, 0xcb8, 0x07000000);
reg1 = odm_get_bb_reg(dm, 0xd00, 0xffffffff);
odm_write_4byte(dm, 0xcb8, 0x08000000);
reg2 = odm_get_bb_reg(dm, 0xd00, 0x0000001f);
image_power = (reg2<<32)+reg1;
dbg_print("After PW = %d\n", image_power);
*/
odm_write_4byte(dm, 0xcb8, 0x06000000);
RX_X0[i][cal] = odm_get_bb_reg(dm, 0xd00, 0x07ff0000) << 21;
odm_write_4byte(dm, 0xcb8, 0x08000000);
RX_Y0[i][cal] = odm_get_bb_reg(dm, 0xd00, 0x07ff0000) << 21;
RX0IQKOK = true;
break;
} else {
odm_set_bb_reg(dm, 0xc10, 0x000003ff, 0x200 >> 1);
odm_set_bb_reg(dm, 0xc10, 0x03ff0000, 0x0 >> 1);
RX0IQKOK = false;
cal_retry++;
if (cal_retry == 10)
break;
}
} else {
RX0IQKOK = false;
cal_retry++;
if (cal_retry == 10)
break;
}
}
}
if (TX0IQKOK)
tx_average++;
if (RX0IQKOK)
rx_average++;
}
break;
default:
break;
}
cal++;
}
/* FillIQK Result */
switch (path) {
case RF_PATH_A:
{
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "========Path_A =======\n");
if (tx_average == 0)
break;
for (i = 0; i < tx_average; i++)
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "TX_X0[%d] = %x ;; TX_Y0[%d] = %x\n", i, (TX_X0[i]) >> 21 & 0x000007ff, i, (TX_Y0[i]) >> 21 & 0x000007ff);
for (i = 0; i < tx_average; i++) {
for (ii = i + 1; ii < tx_average; ii++) {
dx = (TX_X0[i] >> 21) - (TX_X0[ii] >> 21);
if (dx < 3 && dx > -3) {
dy = (TX_Y0[i] >> 21) - (TX_Y0[ii] >> 21);
if (dy < 3 && dy > -3) {
TX_X = ((TX_X0[i] >> 21) + (TX_X0[ii] >> 21)) / 2;
TX_Y = ((TX_Y0[i] >> 21) + (TX_Y0[ii] >> 21)) / 2;
TX_finish = 1;
break;
}
}
}
if (TX_finish == 1)
break;
}
if (TX_finish == 1)
_iqk_tx_fill_iqc_8821a(dm, path, TX_X, TX_Y);
else
_iqk_tx_fill_iqc_8821a(dm, path, 0x200, 0x0);
if (rx_average == 0)
break;
for (i = 0; i < rx_average; i++) {
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "RX_X0[0][%d] = %x ;; RX_Y0[0][%d] = %x\n", i, (RX_X0[0][i]) >> 21 & 0x000007ff, i, (RX_Y0[0][i]) >> 21 & 0x000007ff);
if (rx_iqk_loop == 2)
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "RX_X0[1][%d] = %x ;; RX_Y0[1][%d] = %x\n", i, (RX_X0[1][i]) >> 21 & 0x000007ff, i, (RX_Y0[1][i]) >> 21 & 0x000007ff);
}
for (i = 0; i < rx_average; i++) {
for (ii = i + 1; ii < rx_average; ii++) {
dx = (RX_X0[0][i] >> 21) - (RX_X0[0][ii] >> 21);
if (dx < 4 && dx > -4) {
dy = (RX_Y0[0][i] >> 21) - (RX_Y0[0][ii] >> 21);
if (dy < 4 && dy > -4) {
RX_X_temp = ((RX_X0[0][i] >> 21) + (RX_X0[0][ii] >> 21)) / 2;
RX_Y_temp = ((RX_Y0[0][i] >> 21) + (RX_Y0[0][ii] >> 21)) / 2;
RX_finish1 = 1;
break;
}
}
}
if (RX_finish1 == 1) {
RX_X = RX_X_temp;
RX_Y = RX_Y_temp;
break;
}
}
if (rx_iqk_loop == 2) {
for (i = 0; i < rx_average; i++) {
for (ii = i + 1; ii < rx_average; ii++) {
dx = (RX_X0[1][i] >> 21) - (RX_X0[1][ii] >> 21);
if (dx < 4 && dx > -4) {
dy = (RX_Y0[1][i] >> 21) - (RX_Y0[1][ii] >> 21);
if (dy < 4 && dy > -4) {
RX_X = ((RX_X0[1][i] >> 21) + (RX_X0[1][ii] >> 21)) / 2;
RX_Y = ((RX_Y0[1][i] >> 21) + (RX_Y0[1][ii] >> 21)) / 2;
RX_finish2 = 1;
break;
}
}
}
if (RX_finish2 == 1)
break;
}
if (RX_finish1 && RX_finish2) {
RX_X = (RX_X + RX_X_temp) / 2;
RX_Y = (RX_Y + RX_Y_temp) / 2;
}
}
if (RX_finish1 || RX_finish2)
_iqk_rx_fill_iqc_8821a(dm, path, RX_X, RX_Y);
else
_iqk_rx_fill_iqc_8821a(dm, path, 0x200, 0x0);
}
break;
default:
break;
}
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
if (!TX0IQKOK)
panic_printk("[IQK] please check TXIQK\n");
if (!RX0IQKOK)
panic_printk("[IQK] please check RXIQK\n");
#endif
}
/*IQK: 0x1*/
/*1. add IQK debug message*/
void
_phy_iq_calibrate_8821a(
struct dm_struct *dm
)
{
u32 MACBB_backup[MACBB_REG_NUM_8821A], AFE_backup[AFE_REG_NUM_8821A], RFA_backup[RF_REG_NUM_8821A], RFB_backup[RF_REG_NUM_8821A];
u32 backup_macbb_reg[MACBB_REG_NUM_8821A] = {0x520, 0x550, 0x808, 0xa04, 0x90c, 0xc00, 0x838, 0x82c};
u32 backup_afe_reg[AFE_REG_NUM_8821A] = {0xc5c, 0xc60, 0xc64, 0xc68};
u32 backup_rf_reg[RF_REG_NUM_8821A] = {0x65, 0x8f, 0x0};
_iqk_backup_mac_bb_8821a(dm, MACBB_backup, backup_macbb_reg, MACBB_REG_NUM_8821A);
_iqk_backup_afe_8821a(dm, AFE_backup, backup_afe_reg, AFE_REG_NUM_8821A);
_iqk_backup_rf_8821a(dm, RFA_backup, RFB_backup, backup_rf_reg, RF_REG_NUM_8821A);
_iqk_configure_mac_8821a(dm);
_iqk_tx_8821a(dm, RF_PATH_A);
_iqk_restore_rf_8821a(dm, RF_PATH_A, backup_rf_reg, RFA_backup, RF_REG_NUM_8821A);
_iqk_restore_afe_8821a(dm, AFE_backup, backup_afe_reg, AFE_REG_NUM_8821A);
_iqk_restore_mac_bb_8821a(dm, MACBB_backup, backup_macbb_reg, MACBB_REG_NUM_8821A);
}
void
phy_reset_iqk_result_8821a(
struct dm_struct *dm
)
{
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
odm_set_bb_reg(dm, 0xccc, 0x000007ff, 0x0);
odm_set_bb_reg(dm, 0xcd4, 0x000007ff, 0x200);
odm_write_4byte(dm, 0xce8, 0x0);
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
odm_set_bb_reg(dm, 0xc10, 0x000003ff, 0x100);
odm_set_bb_reg(dm, 0xc10, 0x03ff0000, 0x0);
}
void
phy_iq_calibrate_8821a(
void *dm_void,
boolean is_recovery
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u32 counter = 0;
_phy_iq_calibrate_8821a(dm);
}

42
hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ap.h 100644
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@ -0,0 +1,42 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __PHYDM_IQK_8821A_H__
#define __PHYDM_IQK_8821A_H__
/*--------------------------Define Parameters-------------------------------*/
/*---------------------------End Define Parameters-------------------------------*/
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
void
do_iqk_8821a(
struct dm_struct *dm,
u8 delta_thermal_index,
u8 thermal_value,
u8 threshold
);
void
phy_iq_calibrate_8821a(
struct dm_struct *dm,
boolean is_recovery
);
#else
void
_phy_iq_calibrate_8821a(
struct dm_struct *dm
);
#endif
#endif /* #ifndef __PHYDM_IQK_8821A_H__ */

773
hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ce.c 100644
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@ -0,0 +1,773 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#include "mp_precomp.h"
#include "../../phydm_precomp.h"
/*---------------------------Define Local Constant---------------------------*/
#define cal_num_8821A 3
#define MACBB_REG_NUM_8821A 8
#define AFE_REG_NUM_8821A 4
#define RF_REG_NUM_8821A 3
/*---------------------------Define Local Constant---------------------------*/
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
void do_iqk_8821a(
void *dm_void,
u8 delta_thermal_index,
u8 thermal_value,
u8 threshold
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
dm->rf_calibrate_info.thermal_value_iqk = thermal_value;
halrf_iqk_trigger(dm, false);
}
#endif
void _iqk_rx_fill_iqc_8821a(
struct dm_struct *dm,
enum rf_path path,
unsigned int RX_X,
unsigned int RX_Y
)
{
switch (path) {
case RF_PATH_A:
{
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
odm_set_bb_reg(dm, 0xc10, 0x000003ff, RX_X >> 1);
odm_set_bb_reg(dm, 0xc10, 0x03ff0000, (RX_Y >> 1) & 0x000003ff);
PHYDM_DBG(dm, DBG_COMP_MCC, "RX_X = %x;;RX_Y = %x ====>fill to IQC\n", RX_X >> 1, RX_Y >> 1);
PHYDM_DBG(dm, DBG_COMP_MCC, "0xc10 = %x ====>fill to IQC\n", odm_read_4byte(dm, 0xc10));
}
break;
default:
break;
};
}
void _iqk_tx_fill_iqc_8821a(
struct dm_struct *dm,
enum rf_path path,
unsigned int TX_X,
unsigned int TX_Y
)
{
switch (path) {
case RF_PATH_A:
{
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
odm_write_4byte(dm, 0xc90, 0x00000080);
odm_write_4byte(dm, 0xcc4, 0x20040000);
odm_write_4byte(dm, 0xcc8, 0x20000000);
odm_set_bb_reg(dm, 0xccc, 0x000007ff, TX_Y);
odm_set_bb_reg(dm, 0xcd4, 0x000007ff, TX_X);
PHYDM_DBG(dm, DBG_COMP_MCC, "TX_X = %x;;TX_Y = %x =====> fill to IQC\n", TX_X, TX_Y);
PHYDM_DBG(dm, DBG_COMP_MCC, "0xcd4 = %x;;0xccc = %x ====>fill to IQC\n", odm_get_bb_reg(dm, 0xcd4, 0x000007ff), odm_get_bb_reg(dm, 0xccc, 0x000007ff));
}
break;
default:
break;
};
}
void _iqk_backup_mac_bb_8821a(
struct dm_struct *dm,
u32 *MACBB_backup,
u32 *backup_macbb_reg,
u32 MACBB_NUM
)
{
u32 i;
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
/* save MACBB default value */
for (i = 0; i < MACBB_NUM; i++)
MACBB_backup[i] = odm_read_4byte(dm, backup_macbb_reg[i]);
PHYDM_DBG(dm, DBG_COMP_MCC, "BackupMacBB Success!!!!\n");
}
void _iqk_backup_rf_8821a(
struct dm_struct *dm,
u32 *RFA_backup,
u32 *RFB_backup,
u32 *backup_rf_reg,
u32 RF_NUM
)
{
u32 i;
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
/* Save RF Parameters */
for (i = 0; i < RF_NUM; i++)
RFA_backup[i] = odm_get_rf_reg(dm, RF_PATH_A, backup_rf_reg[i], MASKDWORD);
PHYDM_DBG(dm, DBG_COMP_MCC, "BackupRF Success!!!!\n");
}
void _iqk_backup_afe_8821a(
struct dm_struct *dm,
u32 *AFE_backup,
u32 *backup_afe_reg,
u32 AFE_NUM
)
{
u32 i;
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
/* Save AFE Parameters */
for (i = 0; i < AFE_NUM; i++)
AFE_backup[i] = odm_read_4byte(dm, backup_afe_reg[i]);
PHYDM_DBG(dm, DBG_COMP_MCC, "BackupAFE Success!!!!\n");
}
void _iqk_restore_mac_bb_8821a(
struct dm_struct *dm,
u32 *MACBB_backup,
u32 *backup_macbb_reg,
u32 MACBB_NUM
)
{
u32 i;
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
/* Reload MacBB Parameters */
for (i = 0; i < MACBB_NUM; i++)
odm_write_4byte(dm, backup_macbb_reg[i], MACBB_backup[i]);
PHYDM_DBG(dm, DBG_COMP_MCC, "RestoreMacBB Success!!!!\n");
}
void _iqk_restore_rf_8821a(
struct dm_struct *dm,
enum rf_path path,
u32 *backup_rf_reg,
u32 *RF_backup,
u32 RF_REG_NUM
)
{
u32 i;
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
for (i = 0; i < RF_REG_NUM; i++)
odm_set_rf_reg(dm, (enum rf_path)path, backup_rf_reg[i], RFREGOFFSETMASK, RF_backup[i]);
switch (path) {
case RF_PATH_A:
{
PHYDM_DBG(dm, DBG_COMP_MCC, "RestoreRF path A Success!!!!\n");
}
break;
default:
break;
}
}
void _iqk_restore_afe_8821a(
struct dm_struct *dm,
u32 *AFE_backup,
u32 *backup_afe_reg,
u32 AFE_NUM
)
{
u32 i;
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
/* Reload AFE Parameters */
for (i = 0; i < AFE_NUM; i++)
odm_write_4byte(dm, backup_afe_reg[i], AFE_backup[i]);
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
odm_write_4byte(dm, 0xc80, 0x0);
odm_write_4byte(dm, 0xc84, 0x0);
odm_write_4byte(dm, 0xc88, 0x0);
odm_write_4byte(dm, 0xc8c, 0x3c000000);
odm_write_4byte(dm, 0xc90, 0x00000080);
odm_write_4byte(dm, 0xc94, 0x00000000);
odm_write_4byte(dm, 0xcc4, 0x20040000);
odm_write_4byte(dm, 0xcc8, 0x20000000);
odm_write_4byte(dm, 0xcb8, 0x0);
PHYDM_DBG(dm, DBG_COMP_MCC, "RestoreAFE Success!!!!\n");
}
void _iqk_configure_mac_8821a(
struct dm_struct *dm
)
{
/* ========MAC register setting======== */
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
odm_write_1byte(dm, 0x522, 0x3f);
odm_set_bb_reg(dm, 0x550, BIT(11) | BIT(3), 0x0);
odm_write_1byte(dm, 0x808, 0x00); /* RX ante off */
odm_set_bb_reg(dm, 0x838, 0xf, 0xc); /* CCA off */
odm_write_1byte(dm, 0xa07, 0xf); /* CCK RX path off */
}
void _iqk_tx_8821a(
struct dm_struct *dm,
enum rf_path path
)
{
u32 TX_fail, RX_fail, delay_count, IQK_ready, cal_retry, cal = 0;
int TX_X = 0, TX_Y = 0, RX_X = 0, RX_Y = 0, tx_average = 0, rx_average = 0, rx_iqk_loop = 0, RX_X_temp = 0, RX_Y_temp = 0;
int TX_X0[cal_num_8821A], TX_Y0[cal_num_8821A], RX_X0[2][cal_num_8821A], RX_Y0[2][cal_num_8821A];
boolean TX0IQKOK = false, RX0IQKOK = false;
boolean VDF_enable = false;
int i, k, VDF_Y[3], VDF_X[3], tx_dt[3], ii, dx = 0, dy = 0, TX_finish = 0, RX_finish1 = 0, RX_finish2 = 0;
PHYDM_DBG(dm, DBG_COMP_MCC, "band_width = %d, support_interface = %d, ext_pa = %d, ext_pa_5g = %d\n", *dm->band_width, dm->support_interface, dm->ext_pa, dm->ext_pa_5g);
if (*dm->band_width == 2)
VDF_enable = true;
while (cal < cal_num_8821A) {
switch (path) {
case RF_PATH_A:
{
/* path-A LOK */
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
/* ========path-A AFE all on======== */
/* Port 0 DAC/ADC on */
odm_write_4byte(dm, 0xc60, 0x77777777);
odm_write_4byte(dm, 0xc64, 0x77777777);
odm_write_4byte(dm, 0xc68, 0x19791979);
odm_set_bb_reg(dm, 0xc00, 0xf, 0x4);/* hardware 3-wire off */
/* LOK setting */
/* ====== LOK ====== */
/* 1. DAC/ADC sampling rate (160 MHz) */
odm_set_bb_reg(dm, 0xc5c, BIT(26) | BIT(25) | BIT(24), 0x7);
/* 2. LoK RF setting (at BW = 20M) */
odm_set_rf_reg(dm, (enum rf_path)path, 0xef, RFREGOFFSETMASK, 0x80002);
odm_set_rf_reg(dm, (enum rf_path)path, 0x18, 0x00c00, 0x3);
odm_set_rf_reg(dm, (enum rf_path)path, 0x30, RFREGOFFSETMASK, 0x20000);
odm_set_rf_reg(dm, (enum rf_path)path, 0x31, RFREGOFFSETMASK, 0x0003f);
if (dm->rf_calibrate_info.is_iqk_pa_off == 1)
odm_set_rf_reg(dm, (enum rf_path)path, 0x32, RFREGOFFSETMASK, 0xf3ec3);
else
odm_set_rf_reg(dm, (enum rf_path)path, 0x32, RFREGOFFSETMASK, 0xf3fc3);
odm_set_rf_reg(dm, (enum rf_path)path, 0x65, RFREGOFFSETMASK, 0x931d5);
odm_set_rf_reg(dm, (enum rf_path)path, 0x8f, RFREGOFFSETMASK, 0x8a001);
odm_write_4byte(dm, 0x90c, 0x00008000);
odm_set_bb_reg(dm, 0xc94, BIT(0), 0x1);
odm_write_4byte(dm, 0x978, 0x29002000);/* TX (X,Y) */
odm_write_4byte(dm, 0x97c, 0xa9002000);/* RX (X,Y) */
odm_write_4byte(dm, 0x984, 0x00462910);/* [0]:AGC_en, [15]:idac_K_Mask */
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
if (dm->ext_pa_5g)
odm_write_4byte(dm, 0xc88, 0x821403f7);
else
odm_write_4byte(dm, 0xc88, 0x821403f4);
if (*dm->band_type == ODM_BAND_5G)
odm_write_4byte(dm, 0xc8c, 0x68163e96);
else
odm_write_4byte(dm, 0xc8c, 0x28163e96);
odm_write_4byte(dm, 0xc80, 0x18008c10);/* TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
odm_write_4byte(dm, 0xc84, 0x38008c10);/* RX_Tone_idx[9:0], RxK_Mask[29] */
odm_write_4byte(dm, 0xcb8, 0x00100000);/* cb8[20]iqk_dpk module */
odm_write_4byte(dm, 0x980, 0xfa000000);
odm_write_4byte(dm, 0x980, 0xf8000000);
ODM_delay_ms(10); /* delay 10ms */
odm_write_4byte(dm, 0xcb8, 0x00000000);
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
odm_set_rf_reg(dm, (enum rf_path)path, 0x58, 0x7fe00, odm_get_rf_reg(dm, (enum rf_path)path, 0x8, 0xffc00));
switch (*dm->band_width) {
case 1:
{
odm_set_rf_reg(dm, (enum rf_path)path, 0x18, 0x00c00, 0x1);
}
break;
case 2:
{
odm_set_rf_reg(dm, (enum rf_path)path, 0x18, 0x00c00, 0x0);
}
break;
default:
break;
}
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
/* 3. TX RF setting */
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
odm_set_rf_reg(dm, (enum rf_path)path, 0xef, RFREGOFFSETMASK, 0x80000);
odm_set_rf_reg(dm, (enum rf_path)path, 0x30, RFREGOFFSETMASK, 0x20000);
odm_set_rf_reg(dm, (enum rf_path)path, 0x31, RFREGOFFSETMASK, 0x0003f);
if (dm->rf_calibrate_info.is_iqk_pa_off == 1)
odm_set_rf_reg(dm, (enum rf_path)path, 0x32, RFREGOFFSETMASK, 0xf3ec3);
else
odm_set_rf_reg(dm, (enum rf_path)path, 0x32, RFREGOFFSETMASK, 0xf3fc3);
odm_set_rf_reg(dm, (enum rf_path)path, 0x65, RFREGOFFSETMASK, 0x931d5);
odm_set_rf_reg(dm, (enum rf_path)path, 0x8f, RFREGOFFSETMASK, 0x8a001);
odm_set_rf_reg(dm, (enum rf_path)path, 0xef, RFREGOFFSETMASK, 0x00000);
odm_write_4byte(dm, 0x90c, 0x00008000);
odm_set_bb_reg(dm, 0xc94, BIT(0), 0x1);
odm_write_4byte(dm, 0x978, 0x29002000);/* TX (X,Y) */
odm_write_4byte(dm, 0x97c, 0xa9002000);/* RX (X,Y) */
odm_write_4byte(dm, 0x984, 0x0046a910);/* [0]:AGC_en, [15]:idac_K_Mask */
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
if (dm->ext_pa_5g)
odm_write_4byte(dm, 0xc88, 0x821403f7);
else
odm_write_4byte(dm, 0xc88, 0x821403e3);
if (*dm->band_type == ODM_BAND_5G)
odm_write_4byte(dm, 0xc8c, 0x40163e96);
else
odm_write_4byte(dm, 0xc8c, 0x00163e96);
if (VDF_enable == 1) {
for (k = 0; k <= 2; k++) {
switch (k) {
case 0:
{
odm_write_4byte(dm, 0xc80, 0x18008c38);/* TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
odm_write_4byte(dm, 0xc84, 0x38008c38);/* RX_Tone_idx[9:0], RxK_Mask[29] */
odm_set_bb_reg(dm, 0xce8, BIT(31), 0x0);
}
break;
case 1:
{
odm_set_bb_reg(dm, 0xc80, BIT(28), 0x0);
odm_set_bb_reg(dm, 0xc84, BIT(28), 0x0);
odm_set_bb_reg(dm, 0xce8, BIT(31), 0x0);
}
break;
case 2:
{
PHYDM_DBG(dm, DBG_COMP_MCC, "VDF_Y[1] = %x;;;VDF_Y[0] = %x\n", VDF_Y[1] >> 21 & 0x00007ff, VDF_Y[0] >> 21 & 0x00007ff);
PHYDM_DBG(dm, DBG_COMP_MCC, "VDF_X[1] = %x;;;VDF_X[0] = %x\n", VDF_X[1] >> 21 & 0x00007ff, VDF_X[0] >> 21 & 0x00007ff);
tx_dt[cal] = (VDF_Y[1] >> 20) - (VDF_Y[0] >> 20);
tx_dt[cal] = ((16 * tx_dt[cal]) * 10000 / 15708);
tx_dt[cal] = (tx_dt[cal] >> 1) + (tx_dt[cal] & BIT(0));
odm_write_4byte(dm, 0xc80, 0x18008c20);/* TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
odm_write_4byte(dm, 0xc84, 0x38008c20);/* RX_Tone_idx[9:0], RxK_Mask[29] */
odm_set_bb_reg(dm, 0xce8, BIT(31), 0x1);
odm_set_bb_reg(dm, 0xce8, 0x3fff0000, tx_dt[cal] & 0x00003fff);
}
break;
}
odm_write_4byte(dm, 0xcb8, 0x00100000);/* cb8[20] iqk_dpk module */
cal_retry = 0;
while (1) {
/* one shot */
odm_write_4byte(dm, 0x980, 0xfa000000);
odm_write_4byte(dm, 0x980, 0xf8000000);
ODM_delay_ms(10); /* delay 10ms */
odm_write_4byte(dm, 0xcb8, 0x00000000);
delay_count = 0;
while (1) {
IQK_ready = odm_get_bb_reg(dm, 0xd00, BIT(10));
if ((~IQK_ready) || (delay_count > 20))
break;
else {
ODM_delay_ms(1);
delay_count++;
}
}
if (delay_count < 20) { /* If 20ms No Result, then cal_retry++ */
/* ============TXIQK Check============== */
TX_fail = odm_get_bb_reg(dm, 0xd00, BIT(12));
if (~TX_fail) {
odm_write_4byte(dm, 0xcb8, 0x02000000);
VDF_X[k] = odm_get_bb_reg(dm, 0xd00, 0x07ff0000) << 21;
odm_write_4byte(dm, 0xcb8, 0x04000000);
VDF_Y[k] = odm_get_bb_reg(dm, 0xd00, 0x07ff0000) << 21;
TX0IQKOK = true;
break;
} else {
odm_set_bb_reg(dm, 0xccc, 0x000007ff, 0x0);
odm_set_bb_reg(dm, 0xcd4, 0x000007ff, 0x200);
TX0IQKOK = false;
cal_retry++;
if (cal_retry == 10)
break;
}
} else {
TX0IQKOK = false;
cal_retry++;
if (cal_retry == 10)
break;
}
}
}
if (k == 3) {
TX_X0[cal] = VDF_X[k - 1] ;
TX_Y0[cal] = VDF_Y[k - 1];
}
} else {
odm_write_4byte(dm, 0xc80, 0x18008c10);/* TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
odm_write_4byte(dm, 0xc84, 0x38008c10);/* RX_Tone_idx[9:0], RxK_Mask[29] */
odm_write_4byte(dm, 0xcb8, 0x00100000);/* cb8[20] iqk_dpk module */
cal_retry = 0;
while (1) {
/* one shot */
odm_write_4byte(dm, 0x980, 0xfa000000);
odm_write_4byte(dm, 0x980, 0xf8000000);
ODM_delay_ms(10); /* delay 10ms */
odm_write_4byte(dm, 0xcb8, 0x00000000);
delay_count = 0;
while (1) {
IQK_ready = odm_get_bb_reg(dm, 0xd00, BIT(10));
if ((~IQK_ready) || (delay_count > 20))
break;
else {
ODM_delay_ms(1);
delay_count++;
}
}
if (delay_count < 20) { /* If 20ms No Result, then cal_retry++ */
/* ============TXIQK Check============== */
TX_fail = odm_get_bb_reg(dm, 0xd00, BIT(12));
if (~TX_fail) {
odm_write_4byte(dm, 0xcb8, 0x02000000);
TX_X0[cal] = odm_get_bb_reg(dm, 0xd00, 0x07ff0000) << 21;
odm_write_4byte(dm, 0xcb8, 0x04000000);
TX_Y0[cal] = odm_get_bb_reg(dm, 0xd00, 0x07ff0000) << 21;
TX0IQKOK = true;
break;
} else {
odm_set_bb_reg(dm, 0xccc, 0x000007ff, 0x0);
odm_set_bb_reg(dm, 0xcd4, 0x000007ff, 0x200);
TX0IQKOK = false;
cal_retry++;
if (cal_retry == 10)
break;
}
} else {
TX0IQKOK = false;
cal_retry++;
if (cal_retry == 10)
break;
}
}
}
if (TX0IQKOK == false)
break; /* TXK fail, Don't do RXK */
/* ====== RX IQK ====== */
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
/* 1. RX RF setting */
odm_set_rf_reg(dm, (enum rf_path)path, 0xef, RFREGOFFSETMASK, 0x80000);
odm_set_rf_reg(dm, (enum rf_path)path, 0x30, RFREGOFFSETMASK, 0x30000);
odm_set_rf_reg(dm, (enum rf_path)path, 0x31, RFREGOFFSETMASK, 0x0002f);
odm_set_rf_reg(dm, (enum rf_path)path, 0x32, RFREGOFFSETMASK, 0xfffbb);
odm_set_rf_reg(dm, (enum rf_path)path, 0x8f, RFREGOFFSETMASK, 0x88001);
odm_set_rf_reg(dm, (enum rf_path)path, 0x65, RFREGOFFSETMASK, 0x931d8);
odm_set_rf_reg(dm, (enum rf_path)path, 0xef, RFREGOFFSETMASK, 0x00000);
odm_set_bb_reg(dm, 0x978, 0x03FF8000, (TX_X0[cal]) >> 21 & 0x000007ff);
odm_set_bb_reg(dm, 0x978, 0x000007FF, (TX_Y0[cal]) >> 21 & 0x000007ff);
odm_set_bb_reg(dm, 0x978, BIT(31), 0x1);
odm_set_bb_reg(dm, 0x97c, BIT(31), 0x0);
odm_write_4byte(dm, 0x90c, 0x00008000);
odm_write_4byte(dm, 0x984, 0x0046a911);
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
odm_write_4byte(dm, 0xc80, 0x38008c10);/* TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
odm_write_4byte(dm, 0xc84, 0x18008c10);/* RX_Tone_idx[9:0], RxK_Mask[29] */
odm_write_4byte(dm, 0xc88, 0x02140119);
if (dm->support_interface == 1) {
rx_iqk_loop = 2; /* for 2% fail; */
} else
rx_iqk_loop = 1;
for (i = 0; i < rx_iqk_loop; i++) {
if (dm->support_interface == 1)
if (i == 0)
odm_write_4byte(dm, 0xc8c, 0x28161100); /* Good */
else
odm_write_4byte(dm, 0xc8c, 0x28160d00);
else
odm_write_4byte(dm, 0xc8c, 0x28160d00);
odm_write_4byte(dm, 0xcb8, 0x00100000);/* cb8[20] iqk_dpk module */
cal_retry = 0;
while (1) {
/* one shot */
odm_write_4byte(dm, 0x980, 0xfa000000);
odm_write_4byte(dm, 0x980, 0xf8000000);
ODM_delay_ms(10); /* delay 10ms */
odm_write_4byte(dm, 0xcb8, 0x00000000);
delay_count = 0;
while (1) {
IQK_ready = odm_get_bb_reg(dm, 0xd00, BIT(10));
if ((~IQK_ready) || (delay_count > 20))
break;
else {
ODM_delay_ms(1);
delay_count++;
}
}
if (delay_count < 20) { /* If 20ms No Result, then cal_retry++ */
/* ============RXIQK Check============== */
RX_fail = odm_get_bb_reg(dm, 0xd00, BIT(11));
if (RX_fail == 0) {
/*
dbg_print("====== RXIQK (%d) ======", i);
odm_write_4byte(dm, 0xcb8, 0x05000000);
reg1 = odm_get_bb_reg(dm, 0xd00, 0xffffffff);
odm_write_4byte(dm, 0xcb8, 0x06000000);
reg2 = odm_get_bb_reg(dm, 0xd00, 0x0000001f);
dbg_print("reg1 = %d, reg2 = %d", reg1, reg2);
image_power = (reg2<<32)+reg1;
dbg_print("Before PW = %d\n", image_power);
odm_write_4byte(dm, 0xcb8, 0x07000000);
reg1 = odm_get_bb_reg(dm, 0xd00, 0xffffffff);
odm_write_4byte(dm, 0xcb8, 0x08000000);
reg2 = odm_get_bb_reg(dm, 0xd00, 0x0000001f);
image_power = (reg2<<32)+reg1;
dbg_print("After PW = %d\n", image_power);
*/
odm_write_4byte(dm, 0xcb8, 0x06000000);
RX_X0[i][cal] = odm_get_bb_reg(dm, 0xd00, 0x07ff0000) << 21;
odm_write_4byte(dm, 0xcb8, 0x08000000);
RX_Y0[i][cal] = odm_get_bb_reg(dm, 0xd00, 0x07ff0000) << 21;
RX0IQKOK = true;
break;
} else {
odm_set_bb_reg(dm, 0xc10, 0x000003ff, 0x200 >> 1);
odm_set_bb_reg(dm, 0xc10, 0x03ff0000, 0x0 >> 1);
RX0IQKOK = false;
cal_retry++;
if (cal_retry == 10)
break;
}
} else {
RX0IQKOK = false;
cal_retry++;
if (cal_retry == 10)
break;
}
}
}
if (TX0IQKOK)
tx_average++;
if (RX0IQKOK)
rx_average++;
}
break;
default:
break;
}
cal++;
}
/* FillIQK Result */
switch (path) {
case RF_PATH_A:
{
PHYDM_DBG(dm, DBG_COMP_MCC, "========Path_A =======\n");
if (tx_average == 0)
break;
for (i = 0; i < tx_average; i++)
PHYDM_DBG(dm, DBG_COMP_MCC, "TX_X0[%d] = %x ;; TX_Y0[%d] = %x\n", i, (TX_X0[i]) >> 21 & 0x000007ff, i, (TX_Y0[i]) >> 21 & 0x000007ff);
for (i = 0; i < tx_average; i++) {
for (ii = i + 1; ii < tx_average; ii++) {
dx = (TX_X0[i] >> 21) - (TX_X0[ii] >> 21);
if (dx < 3 && dx > -3) {
dy = (TX_Y0[i] >> 21) - (TX_Y0[ii] >> 21);
if (dy < 3 && dy > -3) {
TX_X = ((TX_X0[i] >> 21) + (TX_X0[ii] >> 21)) / 2;
TX_Y = ((TX_Y0[i] >> 21) + (TX_Y0[ii] >> 21)) / 2;
TX_finish = 1;
break;
}
}
}
if (TX_finish == 1)
break;
}
if (TX_finish == 1)
_iqk_tx_fill_iqc_8821a(dm, path, TX_X, TX_Y);
else
_iqk_tx_fill_iqc_8821a(dm, path, 0x200, 0x0);
if (rx_average == 0)
break;
for (i = 0; i < rx_average; i++) {
PHYDM_DBG(dm, DBG_COMP_MCC, "RX_X0[0][%d] = %x ;; RX_Y0[0][%d] = %x\n", i, (RX_X0[0][i]) >> 21 & 0x000007ff, i, (RX_Y0[0][i]) >> 21 & 0x000007ff);
if (rx_iqk_loop == 2) {
PHYDM_DBG(dm, DBG_COMP_MCC, "RX_X0[1][%d] = %x ;; RX_Y0[1][%d] = %x\n", i, (RX_X0[1][i]) >> 21 & 0x000007ff, i, (RX_Y0[1][i]) >> 21 & 0x000007ff);
}
}
for (i = 0; i < rx_average; i++) {
for (ii = i + 1; ii < rx_average; ii++) {
dx = (RX_X0[0][i] >> 21) - (RX_X0[0][ii] >> 21);
if (dx < 4 && dx > -4) {
dy = (RX_Y0[0][i] >> 21) - (RX_Y0[0][ii] >> 21);
if (dy < 4 && dy > -4) {
RX_X_temp = ((RX_X0[0][i] >> 21) + (RX_X0[0][ii] >> 21)) / 2;
RX_Y_temp = ((RX_Y0[0][i] >> 21) + (RX_Y0[0][ii] >> 21)) / 2;
RX_finish1 = 1;
break;
}
}
}
if (RX_finish1 == 1) {
RX_X = RX_X_temp;
RX_Y = RX_Y_temp;
break;
}
}
if (rx_iqk_loop == 2) {
for (i = 0; i < rx_average; i++) {
for (ii = i + 1; ii < rx_average; ii++) {
dx = (RX_X0[1][i] >> 21) - (RX_X0[1][ii] >> 21);
if (dx < 4 && dx > -4) {
dy = (RX_Y0[1][i] >> 21) - (RX_Y0[1][ii] >> 21);
if (dy < 4 && dy > -4) {
RX_X = ((RX_X0[1][i] >> 21) + (RX_X0[1][ii] >> 21)) / 2;
RX_Y = ((RX_Y0[1][i] >> 21) + (RX_Y0[1][ii] >> 21)) / 2;
RX_finish2 = 1;
break;
}
}
}
if (RX_finish2 == 1)
break;
}
if (RX_finish1 && RX_finish2) {
RX_X = (RX_X + RX_X_temp) / 2;
RX_Y = (RX_Y + RX_Y_temp) / 2;
}
}
if (RX_finish1 || RX_finish2)
_iqk_rx_fill_iqc_8821a(dm, path, RX_X, RX_Y);
else
_iqk_rx_fill_iqc_8821a(dm, path, 0x200, 0x0);
}
break;
default:
break;
}
}
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
void
_phy_iq_calibrate_by_fw_8821a(
struct dm_struct *dm
)
{
u8 iqk_cmd[3] = { *dm->channel, 0x0, 0x0};
u8 buf1 = 0x0;
u8 buf2 = 0x0;
PHYDM_DBG(dm, DBG_COMP_MCC, "channel: %d\n", *dm->channel);
/* Byte 2, Bit 4 ~ Bit 5 : band_type */
if (*dm->band_type == ODM_BAND_5G)
buf1 = 0x2 << 4;
else
buf1 = 0x1 << 4;
/* Byte 2, Bit 0 ~ Bit 3 : bandwidth */
if (*dm->band_width == CHANNEL_WIDTH_20)
buf2 = 0x1;
else if (*dm->band_width == CHANNEL_WIDTH_40)
buf2 = 0x1 << 1;
else if (*dm->band_width == CHANNEL_WIDTH_80)
buf2 = 0x1 << 2;
else
buf2 = 0x1 << 3;
iqk_cmd[1] = buf1 | buf2;
iqk_cmd[2] = dm->ext_pa_5g | dm->ext_lna_5g << 1;
odm_fill_h2c_cmd(dm, ODM_H2C_IQ_CALIBRATION, 3, iqk_cmd);
}
#endif
void
_phy_iq_calibrate_8821a(
struct dm_struct *dm
)
{
u32 MACBB_backup[MACBB_REG_NUM_8821A], AFE_backup[AFE_REG_NUM_8821A], RFA_backup[RF_REG_NUM_8821A], RFB_backup[RF_REG_NUM_8821A];
u32 backup_macbb_reg[MACBB_REG_NUM_8821A] = {0x520, 0x550, 0x808, 0xa04, 0x90c, 0xc00, 0x838, 0x82c};
u32 backup_afe_reg[AFE_REG_NUM_8821A] = {0xc5c, 0xc60, 0xc64, 0xc68};
u32 backup_rf_reg[RF_REG_NUM_8821A] = {0x65, 0x8f, 0x0};
_iqk_backup_mac_bb_8821a(dm, MACBB_backup, backup_macbb_reg, MACBB_REG_NUM_8821A);
_iqk_backup_afe_8821a(dm, AFE_backup, backup_afe_reg, AFE_REG_NUM_8821A);
_iqk_backup_rf_8821a(dm, RFA_backup, RFB_backup, backup_rf_reg, RF_REG_NUM_8821A);
_iqk_configure_mac_8821a(dm);
_iqk_tx_8821a(dm, RF_PATH_A);
_iqk_restore_rf_8821a(dm, RF_PATH_A, backup_rf_reg, RFA_backup, RF_REG_NUM_8821A);
_iqk_restore_afe_8821a(dm, AFE_backup, backup_afe_reg, AFE_REG_NUM_8821A);
_iqk_restore_mac_bb_8821a(dm, MACBB_backup, backup_macbb_reg, MACBB_REG_NUM_8821A);
}
void
phy_reset_iqk_result_8821a(
struct dm_struct *dm
)
{
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
odm_set_bb_reg(dm, 0xccc, 0x000007ff, 0x0);
odm_set_bb_reg(dm, 0xcd4, 0x000007ff, 0x200);
odm_write_4byte(dm, 0xce8, 0x0);
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
odm_set_bb_reg(dm, 0xc10, 0x000003ff, 0x100);
}
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
/*IQK: 0x1*/
void
phy_iq_calibrate_8821a(
void *dm_void,
boolean is_recovery
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u32 counter = 0;
if ((dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) && !(*(dm->mp_mode))) {
_phy_iq_calibrate_by_fw_8821a(dm);
phydm_iqk_wait(dm, 500);
if (dm->rf_calibrate_info.is_iqk_in_progress) {
PHYDM_DBG(dm, DBG_COMP_MCC, "== FW IQK TIMEOUT (Still in progress after 500ms) ==\n");
}
} else
_phy_iq_calibrate_8821a(dm);
}
#endif

41
hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_ce.h 100644
View File

@ -0,0 +1,41 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __PHYDM_IQK_8821A_H__
#define __PHYDM_IQK_8821A_H__
/*--------------------------Define Parameters-------------------------------*/
/*---------------------------End Define Parameters-------------------------------*/
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
void
do_iqk_8821a(
void *dm_void,
u8 delta_thermal_index,
u8 thermal_value,
u8 threshold
);
void
phy_iq_calibrate_8821a(
void *dm_void,
boolean is_recovery
);
#else
void
_phy_iq_calibrate_8821a(
struct dm_struct *dm
);
#endif
#endif /* #ifndef __PHYDM_IQK_8821A_H__ */

774
hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_win.c 100644
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@ -0,0 +1,774 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#include "mp_precomp.h"
#include "../phydm_precomp.h"
/*---------------------------Define Local Constant---------------------------*/
#define cal_num_8821A 3
#define MACBB_REG_NUM_8821A 8
#define AFE_REG_NUM_8821A 4
#define RF_REG_NUM_8821A 3
/*---------------------------Define Local Constant---------------------------*/
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
void do_iqk_8821a(
struct dm_struct *dm,
u8 delta_thermal_index,
u8 thermal_value,
u8 threshold
)
{
dm->rf_calibrate_info.thermal_value_iqk = thermal_value;
halrf_iqk_trigger(dm, false);
}
#endif
void _iqk_rx_fill_iqc_8821a(
struct dm_struct *dm,
enum rf_path path,
unsigned int RX_X,
unsigned int RX_Y
)
{
switch (path) {
case RF_PATH_A:
{
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
odm_set_bb_reg(dm, 0xc10, 0x000003ff, RX_X >> 1);
odm_set_bb_reg(dm, 0xc10, 0x03ff0000, (RX_Y >> 1) & 0x000003ff);
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "RX_X = %x;;RX_Y = %x ====>fill to IQC\n", RX_X >> 1, RX_Y >> 1);
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "0xc10 = %x ====>fill to IQC\n", odm_read_4byte(dm, 0xc10));
}
break;
default:
break;
};
}
void _iqk_tx_fill_iqc_8821a(
struct dm_struct *dm,
enum rf_path path,
unsigned int TX_X,
unsigned int TX_Y
)
{
switch (path) {
case RF_PATH_A:
{
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
odm_write_4byte(dm, 0xc90, 0x00000080);
odm_write_4byte(dm, 0xcc4, 0x20040000);
odm_write_4byte(dm, 0xcc8, 0x20000000);
odm_set_bb_reg(dm, 0xccc, 0x000007ff, TX_Y);
odm_set_bb_reg(dm, 0xcd4, 0x000007ff, TX_X);
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "TX_X = %x;;TX_Y = %x =====> fill to IQC\n", TX_X, TX_Y);
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "0xcd4 = %x;;0xccc = %x ====>fill to IQC\n", odm_get_bb_reg(dm, 0xcd4, 0x000007ff), odm_get_bb_reg(dm, 0xccc, 0x000007ff));
}
break;
default:
break;
};
}
void _iqk_backup_mac_bb_8821a(
struct dm_struct *dm,
u32 *MACBB_backup,
u32 *backup_macbb_reg,
u32 MACBB_NUM
)
{
u32 i;
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
/* save MACBB default value */
for (i = 0; i < MACBB_NUM; i++)
MACBB_backup[i] = odm_read_4byte(dm, backup_macbb_reg[i]);
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "BackupMacBB Success!!!!\n");
}
void _iqk_backup_rf_8821a(
struct dm_struct *dm,
u32 *RFA_backup,
u32 *RFB_backup,
u32 *backup_rf_reg,
u32 RF_NUM
)
{
u32 i;
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
/* Save RF Parameters */
for (i = 0; i < RF_NUM; i++)
RFA_backup[i] = odm_get_rf_reg(dm, RF_PATH_A, backup_rf_reg[i], MASKDWORD);
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "BackupRF Success!!!!\n");
}
void _iqk_backup_afe_8821a(
struct dm_struct *dm,
u32 *AFE_backup,
u32 *backup_afe_reg,
u32 AFE_NUM
)
{
u32 i;
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
/* Save AFE Parameters */
for (i = 0; i < AFE_NUM; i++)
AFE_backup[i] = odm_read_4byte(dm, backup_afe_reg[i]);
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "BackupAFE Success!!!!\n");
}
void _iqk_restore_mac_bb_8821a(
struct dm_struct *dm,
u32 *MACBB_backup,
u32 *backup_macbb_reg,
u32 MACBB_NUM
)
{
u32 i;
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
/* Reload MacBB Parameters */
for (i = 0; i < MACBB_NUM; i++)
odm_write_4byte(dm, backup_macbb_reg[i], MACBB_backup[i]);
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "RestoreMacBB Success!!!!\n");
}
void _iqk_restore_rf_8821a(
struct dm_struct *dm,
enum rf_path path,
u32 *backup_rf_reg,
u32 *RF_backup,
u32 RF_REG_NUM
)
{
u32 i;
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
for (i = 0; i < RF_REG_NUM; i++)
odm_set_rf_reg(dm, (enum rf_path)path, backup_rf_reg[i], RFREGOFFSETMASK, RF_backup[i]);
switch (path) {
case RF_PATH_A:
{
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "RestoreRF path A Success!!!!\n");
}
break;
default:
break;
}
}
void _iqk_restore_afe_8821a(
struct dm_struct *dm,
u32 *AFE_backup,
u32 *backup_afe_reg,
u32 AFE_NUM
)
{
u32 i;
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
/* Reload AFE Parameters */
for (i = 0; i < AFE_NUM; i++)
odm_write_4byte(dm, backup_afe_reg[i], AFE_backup[i]);
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
odm_write_4byte(dm, 0xc80, 0x0);
odm_write_4byte(dm, 0xc84, 0x0);
odm_write_4byte(dm, 0xc88, 0x0);
odm_write_4byte(dm, 0xc8c, 0x3c000000);
odm_write_4byte(dm, 0xc90, 0x00000080);
odm_write_4byte(dm, 0xc94, 0x00000000);
odm_write_4byte(dm, 0xcc4, 0x20040000);
odm_write_4byte(dm, 0xcc8, 0x20000000);
odm_write_4byte(dm, 0xcb8, 0x0);
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "RestoreAFE Success!!!!\n");
}
void _iqk_configure_mac_8821a(
struct dm_struct *dm
)
{
/* ========MAC register setting======== */
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
odm_write_1byte(dm, 0x522, 0x3f);
odm_set_bb_reg(dm, 0x550, BIT(11) | BIT(3), 0x0);
odm_write_1byte(dm, 0x808, 0x00); /* RX ante off */
odm_set_bb_reg(dm, 0x838, 0xf, 0xc); /* CCA off */
odm_write_1byte(dm, 0xa07, 0xf); /* CCK RX path off */
}
void _iqk_tx_8821a(
struct dm_struct *dm,
enum rf_path path
)
{
u32 TX_fail, RX_fail, delay_count, IQK_ready, cal_retry, cal = 0;
int TX_X = 0, TX_Y = 0, RX_X = 0, RX_Y = 0, tx_average = 0, rx_average = 0, rx_iqk_loop = 0, RX_X_temp = 0, RX_Y_temp = 0;
int TX_X0[cal_num_8821A], TX_Y0[cal_num_8821A], RX_X0[2][cal_num_8821A], RX_Y0[2][cal_num_8821A];
boolean TX0IQKOK = false, RX0IQKOK = false;
boolean VDF_enable = false;
int i, k, VDF_Y[3], VDF_X[3], tx_dt[3], ii, dx = 0, dy = 0, TX_finish = 0, RX_finish1 = 0, RX_finish2 = 0;
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "band_width = %d, support_interface = %d, ext_pa = %d, ext_pa_5g = %d\n", *dm->band_width, dm->support_interface, dm->ext_pa, dm->ext_pa_5g);
if (*dm->band_width == 2)
VDF_enable = true;
while (cal < cal_num_8821A) {
switch (path) {
case RF_PATH_A:
{
/* path-A LOK */
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
/* ========path-A AFE all on======== */
/* Port 0 DAC/ADC on */
odm_write_4byte(dm, 0xc60, 0x77777777);
odm_write_4byte(dm, 0xc64, 0x77777777);
odm_write_4byte(dm, 0xc68, 0x19791979);
odm_set_bb_reg(dm, 0xc00, 0xf, 0x4);/* hardware 3-wire off */
/* LOK setting */
/* ====== LOK ====== */
/* 1. DAC/ADC sampling rate (160 MHz) */
odm_set_bb_reg(dm, 0xc5c, BIT(26) | BIT(25) | BIT(24), 0x7);
/* 2. LoK RF setting (at BW = 20M) */
odm_set_rf_reg(dm, (enum rf_path)path, 0xef, RFREGOFFSETMASK, 0x80002);
odm_set_rf_reg(dm, (enum rf_path)path, 0x18, 0x00c00, 0x3);
odm_set_rf_reg(dm, (enum rf_path)path, 0x30, RFREGOFFSETMASK, 0x20000);
odm_set_rf_reg(dm, (enum rf_path)path, 0x31, RFREGOFFSETMASK, 0x0003f);
odm_set_rf_reg(dm, (enum rf_path)path, 0x32, RFREGOFFSETMASK, 0xf3fc3);
odm_set_rf_reg(dm, (enum rf_path)path, 0x65, RFREGOFFSETMASK, 0x931d5);
odm_set_rf_reg(dm, (enum rf_path)path, 0x8f, RFREGOFFSETMASK, 0x8a001);
odm_write_4byte(dm, 0x90c, 0x00008000);
odm_set_bb_reg(dm, 0xc94, BIT(0), 0x1);
odm_write_4byte(dm, 0x978, 0x29002000);/* TX (X,Y) */
odm_write_4byte(dm, 0x97c, 0xa9002000);/* RX (X,Y) */
odm_write_4byte(dm, 0x984, 0x00462910);/* [0]:AGC_en, [15]:idac_K_Mask */
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
if (dm->ext_pa_5g)
odm_write_4byte(dm, 0xc88, 0x821403f7);
else
odm_write_4byte(dm, 0xc88, 0x821403f4);
if (*dm->band_type == ODM_BAND_5G)
odm_write_4byte(dm, 0xc8c, 0x68163e96);
else
odm_write_4byte(dm, 0xc8c, 0x28163e96);
odm_write_4byte(dm, 0xc80, 0x18008c10);/* TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
odm_write_4byte(dm, 0xc84, 0x38008c10);/* RX_Tone_idx[9:0], RxK_Mask[29] */
odm_write_4byte(dm, 0xcb8, 0x00100000);/* cb8[20] 將 SI/PI 使用權切給 iqk_dpk module */
odm_write_4byte(dm, 0x980, 0xfa000000);
odm_write_4byte(dm, 0x980, 0xf8000000);
ODM_delay_ms(10); /* delay 10ms */
odm_write_4byte(dm, 0xcb8, 0x00000000);
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
odm_set_rf_reg(dm, (enum rf_path)path, 0x58, 0x7fe00,
odm_get_rf_reg(dm, (enum rf_path)path, 0x8, 0xffc00));
switch (*dm->band_width) {
case 1:
{
odm_set_rf_reg(dm, (enum rf_path)path, 0x18, 0x00c00, 0x1);
}
break;
case 2:
{
odm_set_rf_reg(dm, (enum rf_path)path, 0x18, 0x00c00, 0x0);
}
break;
default:
break;
}
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
/* 3. TX RF setting */
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
odm_set_rf_reg(dm, (enum rf_path)path, 0xef, RFREGOFFSETMASK, 0x80000);
odm_set_rf_reg(dm, (enum rf_path)path, 0x30, RFREGOFFSETMASK, 0x20000);
odm_set_rf_reg(dm, (enum rf_path)path, 0x31, RFREGOFFSETMASK, 0x0003f);
odm_set_rf_reg(dm, (enum rf_path)path, 0x32, RFREGOFFSETMASK, 0xf3fc3);
odm_set_rf_reg(dm, (enum rf_path)path, 0x65, RFREGOFFSETMASK, 0x931d5);
odm_set_rf_reg(dm, (enum rf_path)path, 0x8f, RFREGOFFSETMASK, 0x8a001);
odm_set_rf_reg(dm, (enum rf_path)path, 0xef, RFREGOFFSETMASK, 0x00000);
odm_write_4byte(dm, 0x90c, 0x00008000);
odm_set_bb_reg(dm, 0xc94, BIT(0), 0x1);
odm_write_4byte(dm, 0x978, 0x29002000);/* TX (X,Y) */
odm_write_4byte(dm, 0x97c, 0xa9002000);/* RX (X,Y) */
odm_write_4byte(dm, 0x984, 0x0046a910);/* [0]:AGC_en, [15]:idac_K_Mask */
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
if (dm->ext_pa_5g)
odm_write_4byte(dm, 0xc88, 0x821403f7);
else
odm_write_4byte(dm, 0xc88, 0x821403e3);
if (*dm->band_type == ODM_BAND_5G)
odm_write_4byte(dm, 0xc8c, 0x40163e96);
else
odm_write_4byte(dm, 0xc8c, 0x00163e96);
if (VDF_enable == 1) {
for (k = 0; k <= 2; k++) {
switch (k) {
case 0:
{
odm_write_4byte(dm, 0xc80, 0x18008c38);/* TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
odm_write_4byte(dm, 0xc84, 0x38008c38);/* RX_Tone_idx[9:0], RxK_Mask[29] */
odm_set_bb_reg(dm, 0xce8, BIT(31), 0x0);
}
break;
case 1:
{
odm_set_bb_reg(dm, 0xc80, BIT(28), 0x0);
odm_set_bb_reg(dm, 0xc84, BIT(28), 0x0);
odm_set_bb_reg(dm, 0xce8, BIT(31), 0x0);
}
break;
case 2:
{
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "VDF_Y[1] = %x;;;VDF_Y[0] = %x\n", VDF_Y[1] >> 21 & 0x00007ff, VDF_Y[0] >> 21 & 0x00007ff);
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "VDF_X[1] = %x;;;VDF_X[0] = %x\n", VDF_X[1] >> 21 & 0x00007ff, VDF_X[0] >> 21 & 0x00007ff);
tx_dt[cal] = (VDF_Y[1] >> 20) - (VDF_Y[0] >> 20);
tx_dt[cal] = ((16 * tx_dt[cal]) * 10000 / 15708);
tx_dt[cal] = (tx_dt[cal] >> 1) + (tx_dt[cal] & BIT(0));
odm_write_4byte(dm, 0xc80, 0x18008c20);/* TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
odm_write_4byte(dm, 0xc84, 0x38008c20);/* RX_Tone_idx[9:0], RxK_Mask[29] */
odm_set_bb_reg(dm, 0xce8, BIT(31), 0x1);
odm_set_bb_reg(dm, 0xce8, 0x3fff0000, tx_dt[cal] & 0x00003fff);
}
break;
}
odm_write_4byte(dm, 0xcb8, 0x00100000);/* cb8[20] 將 SI/PI 使用權切給 iqk_dpk module */
cal_retry = 0;
while (1) {
/* one shot */
odm_write_4byte(dm, 0x980, 0xfa000000);
odm_write_4byte(dm, 0x980, 0xf8000000);
ODM_delay_ms(10); /* delay 10ms */
odm_write_4byte(dm, 0xcb8, 0x00000000);
delay_count = 0;
while (1) {
IQK_ready = odm_get_bb_reg(dm, 0xd00, BIT(10));
if ((~IQK_ready) || (delay_count > 20))
break;
else {
ODM_delay_ms(1);
delay_count++;
}
}
if (delay_count < 20) { /* If 20ms No Result, then cal_retry++ */
/* ============TXIQK Check============== */
TX_fail = odm_get_bb_reg(dm, 0xd00, BIT(12));
if (~TX_fail) {
odm_write_4byte(dm, 0xcb8, 0x02000000);
VDF_X[k] = odm_get_bb_reg(dm, 0xd00, 0x07ff0000) << 21;
odm_write_4byte(dm, 0xcb8, 0x04000000);
VDF_Y[k] = odm_get_bb_reg(dm, 0xd00, 0x07ff0000) << 21;
TX0IQKOK = true;
break;
} else {
odm_set_bb_reg(dm, 0xccc, 0x000007ff, 0x0);
odm_set_bb_reg(dm, 0xcd4, 0x000007ff, 0x200);
TX0IQKOK = false;
cal_retry++;
if (cal_retry == 10)
break;
}
} else {
TX0IQKOK = false;
cal_retry++;
if (cal_retry == 10)
break;
}
}
}
if (k == 3) {
TX_X0[cal] = VDF_X[k - 1] ;
TX_Y0[cal] = VDF_Y[k - 1];
}
} else {
odm_write_4byte(dm, 0xc80, 0x18008c10);/* TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
odm_write_4byte(dm, 0xc84, 0x38008c10);/* RX_Tone_idx[9:0], RxK_Mask[29] */
odm_write_4byte(dm, 0xcb8, 0x00100000);/* cb8[20] 將 SI/PI 使用權切給 iqk_dpk module */
cal_retry = 0;
while (1) {
/* one shot */
odm_write_4byte(dm, 0x980, 0xfa000000);
odm_write_4byte(dm, 0x980, 0xf8000000);
ODM_delay_ms(10); /* delay 10ms */
odm_write_4byte(dm, 0xcb8, 0x00000000);
delay_count = 0;
while (1) {
IQK_ready = odm_get_bb_reg(dm, 0xd00, BIT(10));
if ((~IQK_ready) || (delay_count > 20))
break;
else {
ODM_delay_ms(1);
delay_count++;
}
}
if (delay_count < 20) { /* If 20ms No Result, then cal_retry++ */
/* ============TXIQK Check============== */
TX_fail = odm_get_bb_reg(dm, 0xd00, BIT(12));
if (~TX_fail) {
odm_write_4byte(dm, 0xcb8, 0x02000000);
TX_X0[cal] = odm_get_bb_reg(dm, 0xd00, 0x07ff0000) << 21;
odm_write_4byte(dm, 0xcb8, 0x04000000);
TX_Y0[cal] = odm_get_bb_reg(dm, 0xd00, 0x07ff0000) << 21;
TX0IQKOK = true;
break;
} else {
odm_set_bb_reg(dm, 0xccc, 0x000007ff, 0x0);
odm_set_bb_reg(dm, 0xcd4, 0x000007ff, 0x200);
TX0IQKOK = false;
cal_retry++;
if (cal_retry == 10)
break;
}
} else {
TX0IQKOK = false;
cal_retry++;
if (cal_retry == 10)
break;
}
}
}
if (TX0IQKOK == false)
break; /* TXK fail, Don't do RXK */
/* ====== RX IQK ====== */
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
/* 1. RX RF setting */
odm_set_rf_reg(dm, (enum rf_path)path, 0xef, RFREGOFFSETMASK, 0x80000);
odm_set_rf_reg(dm, (enum rf_path)path, 0x30, RFREGOFFSETMASK, 0x30000);
odm_set_rf_reg(dm, (enum rf_path)path, 0x31, RFREGOFFSETMASK, 0x0002f);
odm_set_rf_reg(dm, (enum rf_path)path, 0x32, RFREGOFFSETMASK, 0xfffbb);
odm_set_rf_reg(dm, (enum rf_path)path, 0x8f, RFREGOFFSETMASK, 0x88001);
odm_set_rf_reg(dm, (enum rf_path)path, 0x65, RFREGOFFSETMASK, 0x931d8);
odm_set_rf_reg(dm, (enum rf_path)path, 0xef, RFREGOFFSETMASK, 0x00000);
odm_set_bb_reg(dm, 0x978, 0x03FF8000, (TX_X0[cal]) >> 21 & 0x000007ff);
odm_set_bb_reg(dm, 0x978, 0x000007FF, (TX_Y0[cal]) >> 21 & 0x000007ff);
odm_set_bb_reg(dm, 0x978, BIT(31), 0x1);
odm_set_bb_reg(dm, 0x97c, BIT(31), 0x0);
odm_write_4byte(dm, 0x90c, 0x00008000);
odm_write_4byte(dm, 0x984, 0x0046a911);
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
odm_write_4byte(dm, 0xc80, 0x38008c10);/* TX_Tone_idx[9:0], TxK_Mask[29] TX_Tone = 16 */
odm_write_4byte(dm, 0xc84, 0x18008c10);/* RX_Tone_idx[9:0], RxK_Mask[29] */
odm_write_4byte(dm, 0xc88, 0x02140119);
if (dm->support_interface == 1) {
rx_iqk_loop = 2; /* for 2% fail; */
} else
rx_iqk_loop = 1;
for (i = 0; i < rx_iqk_loop; i++) {
if (dm->support_interface == 1)
if (i == 0)
odm_write_4byte(dm, 0xc8c, 0x28161100); /* Good */
else
odm_write_4byte(dm, 0xc8c, 0x28160d00);
else
odm_write_4byte(dm, 0xc8c, 0x28160d00);
odm_write_4byte(dm, 0xcb8, 0x00100000);/* cb8[20] 將 SI/PI 使用權切給 iqk_dpk module */
cal_retry = 0;
while (1) {
/* one shot */
odm_write_4byte(dm, 0x980, 0xfa000000);
odm_write_4byte(dm, 0x980, 0xf8000000);
ODM_delay_ms(10); /* delay 10ms */
odm_write_4byte(dm, 0xcb8, 0x00000000);
delay_count = 0;
while (1) {
IQK_ready = odm_get_bb_reg(dm, 0xd00, BIT(10));
if ((~IQK_ready) || (delay_count > 20))
break;
else {
ODM_delay_ms(1);
delay_count++;
}
}
if (delay_count < 20) { /* If 20ms No Result, then cal_retry++ */
/* ============RXIQK Check============== */
RX_fail = odm_get_bb_reg(dm, 0xd00, BIT(11));
if (RX_fail == 0) {
/*
dbg_print("====== RXIQK (%d) ======", i);
odm_write_4byte(dm, 0xcb8, 0x05000000);
reg1 = odm_get_bb_reg(dm, 0xd00, 0xffffffff);
odm_write_4byte(dm, 0xcb8, 0x06000000);
reg2 = odm_get_bb_reg(dm, 0xd00, 0x0000001f);
dbg_print("reg1 = %d, reg2 = %d", reg1, reg2);
image_power = (reg2<<32)+reg1;
dbg_print("Before PW = %d\n", image_power);
odm_write_4byte(dm, 0xcb8, 0x07000000);
reg1 = odm_get_bb_reg(dm, 0xd00, 0xffffffff);
odm_write_4byte(dm, 0xcb8, 0x08000000);
reg2 = odm_get_bb_reg(dm, 0xd00, 0x0000001f);
image_power = (reg2<<32)+reg1;
dbg_print("After PW = %d\n", image_power);
*/
odm_write_4byte(dm, 0xcb8, 0x06000000);
RX_X0[i][cal] = odm_get_bb_reg(dm, 0xd00, 0x07ff0000) << 21;
odm_write_4byte(dm, 0xcb8, 0x08000000);
RX_Y0[i][cal] = odm_get_bb_reg(dm, 0xd00, 0x07ff0000) << 21;
RX0IQKOK = true;
break;
} else {
odm_set_bb_reg(dm, 0xc10, 0x000003ff, 0x200 >> 1);
odm_set_bb_reg(dm, 0xc10, 0x03ff0000, 0x0 >> 1);
RX0IQKOK = false;
cal_retry++;
if (cal_retry == 10)
break;
}
} else {
RX0IQKOK = false;
cal_retry++;
if (cal_retry == 10)
break;
}
}
}
if (TX0IQKOK)
tx_average++;
if (RX0IQKOK)
rx_average++;
}
break;
default:
break;
}
cal++;
}
/* FillIQK Result */
switch (path) {
case RF_PATH_A:
{
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "========Path_A =======\n");
if (tx_average == 0)
break;
for (i = 0; i < tx_average; i++)
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "TX_X0[%d] = %x ;; TX_Y0[%d] = %x\n", i, (TX_X0[i]) >> 21 & 0x000007ff, i, (TX_Y0[i]) >> 21 & 0x000007ff);
for (i = 0; i < tx_average; i++) {
for (ii = i + 1; ii < tx_average; ii++) {
dx = (TX_X0[i] >> 21) - (TX_X0[ii] >> 21);
if (dx < 3 && dx > -3) {
dy = (TX_Y0[i] >> 21) - (TX_Y0[ii] >> 21);
if (dy < 3 && dy > -3) {
TX_X = ((TX_X0[i] >> 21) + (TX_X0[ii] >> 21)) / 2;
TX_Y = ((TX_Y0[i] >> 21) + (TX_Y0[ii] >> 21)) / 2;
TX_finish = 1;
break;
}
}
}
if (TX_finish == 1)
break;
}
if (TX_finish == 1)
_iqk_tx_fill_iqc_8821a(dm, path, TX_X, TX_Y);
else
_iqk_tx_fill_iqc_8821a(dm, path, 0x200, 0x0);
if (rx_average == 0)
break;
for (i = 0; i < rx_average; i++) {
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "RX_X0[0][%d] = %x ;; RX_Y0[0][%d] = %x\n", i, (RX_X0[0][i]) >> 21 & 0x000007ff, i, (RX_Y0[0][i]) >> 21 & 0x000007ff);
if (rx_iqk_loop == 2)
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "RX_X0[1][%d] = %x ;; RX_Y0[1][%d] = %x\n", i, (RX_X0[1][i]) >> 21 & 0x000007ff, i, (RX_Y0[1][i]) >> 21 & 0x000007ff);
}
for (i = 0; i < rx_average; i++) {
for (ii = i + 1; ii < rx_average; ii++) {
dx = (RX_X0[0][i] >> 21) - (RX_X0[0][ii] >> 21);
if (dx < 4 && dx > -4) {
dy = (RX_Y0[0][i] >> 21) - (RX_Y0[0][ii] >> 21);
if (dy < 4 && dy > -4) {
RX_X_temp = ((RX_X0[0][i] >> 21) + (RX_X0[0][ii] >> 21)) / 2;
RX_Y_temp = ((RX_Y0[0][i] >> 21) + (RX_Y0[0][ii] >> 21)) / 2;
RX_finish1 = 1;
break;
}
}
}
if (RX_finish1 == 1) {
RX_X = RX_X_temp;
RX_Y = RX_Y_temp;
break;
}
}
if (rx_iqk_loop == 2) {
for (i = 0; i < rx_average; i++) {
for (ii = i + 1; ii < rx_average; ii++) {
dx = (RX_X0[1][i] >> 21) - (RX_X0[1][ii] >> 21);
if (dx < 4 && dx > -4) {
dy = (RX_Y0[1][i] >> 21) - (RX_Y0[1][ii] >> 21);
if (dy < 4 && dy > -4) {
RX_X = ((RX_X0[1][i] >> 21) + (RX_X0[1][ii] >> 21)) / 2;
RX_Y = ((RX_Y0[1][i] >> 21) + (RX_Y0[1][ii] >> 21)) / 2;
RX_finish2 = 1;
break;
}
}
}
if (RX_finish2 == 1)
break;
}
if (RX_finish1 && RX_finish2) {
RX_X = (RX_X + RX_X_temp) / 2;
RX_Y = (RX_Y + RX_Y_temp) / 2;
}
}
if (RX_finish1 || RX_finish2)
_iqk_rx_fill_iqc_8821a(dm, path, RX_X, RX_Y);
else
_iqk_rx_fill_iqc_8821a(dm, path, 0x200, 0x0);
}
break;
default:
break;
}
}
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
void
_phy_iq_calibrate_by_fw_8821a(
struct dm_struct *dm
)
{
u8 iqk_cmd[3] = { *dm->channel, 0x0, 0x0};
u8 buf1 = 0x0;
u8 buf2 = 0x0;
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "channel: %d\n", *dm->channel);
/* Byte 2, Bit 4 ~ Bit 5 : band_type */
if (*dm->band_type == ODM_BAND_5G)
buf1 = 0x2 << 4;
else
buf1 = 0x1 << 4;
/* Byte 2, Bit 0 ~ Bit 3 : bandwidth */
if (*dm->band_width == CHANNEL_WIDTH_20)
buf2 = 0x1;
else if (*dm->band_width == CHANNEL_WIDTH_40)
buf2 = 0x1 << 1;
else if (*dm->band_width == CHANNEL_WIDTH_80)
buf2 = 0x1 << 2;
else
buf2 = 0x1 << 3;
iqk_cmd[1] = buf1 | buf2;
iqk_cmd[2] = dm->ext_pa_5g | dm->ext_lna_5g << 1;
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "== FW IQK Start ==\n");
dm->rf_calibrate_info.iqk_start_time = 0;
dm->rf_calibrate_info.iqk_start_time = odm_get_current_time(dm);
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "== start_time: %lld\n", dm->rf_calibrate_info.iqk_start_time);
odm_fill_h2c_cmd(dm, ODM_H2C_IQ_CALIBRATION, 3, iqk_cmd);
}
#endif
void
_phy_iq_calibrate_8821a(
struct dm_struct *dm
)
{
u32 MACBB_backup[MACBB_REG_NUM_8821A], AFE_backup[AFE_REG_NUM_8821A], RFA_backup[RF_REG_NUM_8821A], RFB_backup[RF_REG_NUM_8821A];
u32 backup_macbb_reg[MACBB_REG_NUM_8821A] = {0x520, 0x550, 0x808, 0xa04, 0x90c, 0xc00, 0x838, 0x82c};
u32 backup_afe_reg[AFE_REG_NUM_8821A] = {0xc5c, 0xc60, 0xc64, 0xc68};
u32 backup_rf_reg[RF_REG_NUM_8821A] = {0x65, 0x8f, 0x0};
_iqk_backup_mac_bb_8821a(dm, MACBB_backup, backup_macbb_reg, MACBB_REG_NUM_8821A);
_iqk_backup_afe_8821a(dm, AFE_backup, backup_afe_reg, AFE_REG_NUM_8821A);
_iqk_backup_rf_8821a(dm, RFA_backup, RFB_backup, backup_rf_reg, RF_REG_NUM_8821A);
_iqk_configure_mac_8821a(dm);
_iqk_tx_8821a(dm, RF_PATH_A);
_iqk_restore_rf_8821a(dm, RF_PATH_A, backup_rf_reg, RFA_backup, RF_REG_NUM_8821A);
_iqk_restore_afe_8821a(dm, AFE_backup, backup_afe_reg, AFE_REG_NUM_8821A);
_iqk_restore_mac_bb_8821a(dm, MACBB_backup, backup_macbb_reg, MACBB_REG_NUM_8821A);
}
void
phy_reset_iqk_result_8821a(
struct dm_struct *dm
)
{
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x1); /* [31] = 1 --> Page C1 */
odm_set_bb_reg(dm, 0xccc, 0x000007ff, 0x0);
odm_set_bb_reg(dm, 0xcd4, 0x000007ff, 0x200);
odm_write_4byte(dm, 0xce8, 0x0);
odm_set_bb_reg(dm, 0x82c, BIT(31), 0x0); /* [31] = 0 --> Page C */
odm_set_bb_reg(dm, 0xc10, 0x000003ff, 0x100);
}
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
void
phy_iq_calibrate_8821a(
void *dm_void,
boolean is_recovery
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
u32 counter = 0;
if ((dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) && !(*(dm->mp_mode))) {
_phy_iq_calibrate_by_fw_8821a(dm);
for (counter = 0; counter < 10; counter++) {
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "== FW IQK PROGRESS == #%d\n", counter);
ODM_delay_ms(50);
if (!dm->rf_calibrate_info.is_iqk_in_progress) {
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "== FW IQK RETURN FROM WAITING ==\n");
break;
}
}
if (dm->rf_calibrate_info.is_iqk_in_progress)
PHYDM_DBG(dm, ODM_COMP_CALIBRATION, "== FW IQK TIMEOUT (Still in progress after 500ms) ==\n");
} else
_phy_iq_calibrate_8821a(dm);
}
#endif

42
hal/phydm/halrf/rtl8821a/halrf_iqk_8821a_win.h 100644
View File

@ -0,0 +1,42 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __PHYDM_IQK_8821A_H__
#define __PHYDM_IQK_8821A_H__
/*--------------------------Define Parameters-------------------------------*/
/*---------------------------End Define Parameters-------------------------------*/
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
void
do_iqk_8821a(
struct dm_struct *dm,
u8 delta_thermal_index,
u8 thermal_value,
u8 threshold
);
void
phy_iq_calibrate_8821a(
void *dm_void,
boolean is_recovery
);
#else
void
_phy_iq_calibrate_8821a(
struct dm_struct *dm
);
#endif
#endif /* #ifndef __PHYDM_IQK_8821A_H__ */

2
hal/phydm/phydm.c
View File

@ -489,10 +489,12 @@ void phydm_hw_setting(struct dm_struct *dm)
odm_hw_setting_8821a(dm);
#endif
#if 0 /* TODO: implementation done but may not work and do nothing with current flags. Commenting the code to match previous version behavior*/
#if (RTL8814A_SUPPORT == 1)
if (dm->support_ic_type & ODM_RTL8814A)
phydm_hwsetting_8814a(dm);
#endif
#endif
#if (RTL8822B_SUPPORT == 1)
if (dm->support_ic_type & ODM_RTL8822B)

4
hal/phydm/phydm_debug.h
View File

@ -276,6 +276,8 @@ static __inline void PHYDM_DBG_F(PDM_ODM_T dm, int comp, char *fmt, ...)
} while (0)
#endif
#define ODM_RT_TRACE(dm, comp, level, fmt)
#else /*@#if DBG*/
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
static __inline void PHYDM_DBG(struct dm_struct *dm, int comp, char *fmt, ...)
@ -309,7 +311,7 @@ static __inline void PHYDM_DBG_F(struct dm_struct *dm, int comp, char *fmt, ...)
#define PHYDM_DBG_F(dm, comp, fmt, args...)
#endif
#define PHYDM_PRINT_ADDR(dm, comp, title_str, ptr)
#define ODM_RT_TRACE(dm, comp, level, fmt)
#endif
#define DBGPORT_PRI_3 3 /*@Debug function (the highest priority)*/

14
hal/phydm/phydm_hwconfig.c
View File

@ -189,7 +189,7 @@ odm_config_rf_with_header_file(struct dm_struct *dm,
else if (e_rf_path == RF_PATH_D)
READ_AND_CONFIG_MP(8814a, _radiod);
} else if (config_type == CONFIG_RF_TXPWR_LMT) {
if (dm->rfe_type == 0)
/*if (dm->rfe_type == 0)
READ_AND_CONFIG_MP(8814a, _txpwr_lmt_type0);
else if (dm->rfe_type == 1)
READ_AND_CONFIG_MP(8814a, _txpwr_lmt_type1);
@ -203,7 +203,7 @@ odm_config_rf_with_header_file(struct dm_struct *dm,
READ_AND_CONFIG_MP(8814a, _txpwr_lmt_type7);
else if (dm->rfe_type == 8)
READ_AND_CONFIG_MP(8814a, _txpwr_lmt_type8);
else
else*/
READ_AND_CONFIG_MP(8814a, _txpwr_lmt);
}
}
@ -572,14 +572,14 @@ odm_config_rf_with_tx_pwr_track_header_file(struct dm_struct *dm)
READ_AND_CONFIG_MP(8814a, _txpowertrack_type2);
else if (dm->rfe_type == 5)
READ_AND_CONFIG_MP(8814a, _txpowertrack_type5);
else if (dm->rfe_type == 7)
/*else if (dm->rfe_type == 7)
READ_AND_CONFIG_MP(8814a, _txpowertrack_type7);
else if (dm->rfe_type == 8)
READ_AND_CONFIG_MP(8814a, _txpowertrack_type8);
READ_AND_CONFIG_MP(8814a, _txpowertrack_type8);*/
else
READ_AND_CONFIG_MP(8814a, _txpowertrack);
READ_AND_CONFIG_MP(8814a, _txpowertssi);
//READ_AND_CONFIG_MP(8814a, _txpowertssi);
}
#endif
#if RTL8703B_SUPPORT
@ -914,7 +914,7 @@ odm_config_bb_with_header_file(struct dm_struct *dm,
else if (config_type == CONFIG_BB_AGC_TAB)
READ_AND_CONFIG_MP(8814a, _agc_tab);
else if (config_type == CONFIG_BB_PHY_REG_PG) {
if (dm->rfe_type == 0)
/*if (dm->rfe_type == 0)
READ_AND_CONFIG_MP(8814a, _phy_reg_pg_type0);
else if (dm->rfe_type == 2)
READ_AND_CONFIG_MP(8814a, _phy_reg_pg_type2);
@ -928,7 +928,7 @@ odm_config_bb_with_header_file(struct dm_struct *dm,
READ_AND_CONFIG_MP(8814a, _phy_reg_pg_type7);
else if (dm->rfe_type == 8)
READ_AND_CONFIG_MP(8814a, _phy_reg_pg_type8);
else
else*/
READ_AND_CONFIG_MP(8814a, _phy_reg_pg);
} else if (config_type == CONFIG_BB_PHY_REG_MP)
READ_AND_CONFIG_MP(8814a, _phy_reg_mp);

47
hal/phydm/rtl8814a/hal8814areg_odm.h 100644
View File

@ -0,0 +1,47 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//============================================================
/* File Name: hal8814areg_odm.h */
//
// Description:
//
// This file is for RTL8814A register definition.
//
//
//============================================================
#ifndef __HAL_8814A_REG_H__
#define __HAL_8814A_REG_H__
//
// Register Definition
//
#define TRX_ANTDIV_PATH 0x860
#define RX_ANTDIV_PATH 0xb2c
#define ODM_R_A_AGC_CORE1_8814A 0xc50
//
// Bitmap Definition
//
#define BIT_FA_RESET_8814A BIT0
#endif

4489
hal/phydm/rtl8814a/halhwimg8814a_bb.c 100644
View File

File diff suppressed because it is too large Load Diff

99
hal/phydm/rtl8814a/halhwimg8814a_bb.h 100644
View File

@ -0,0 +1,99 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*Image2HeaderVersion: 2.19*/
#if (RTL8814A_SUPPORT == 1)
#ifndef __INC_MP_BB_HW_IMG_8814A_H
#define __INC_MP_BB_HW_IMG_8814A_H
/******************************************************************************
* AGC_TAB.TXT
******************************************************************************/
void
odm_read_and_config_mp_8814a_agc_tab(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct * pDM_Odm
);
u4Byte ODM_GetVersion_MP_8814A_AGC_TAB(void);
/******************************************************************************
* PHY_REG.TXT
******************************************************************************/
void
odm_read_and_config_mp_8814a_phy_reg(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct * pDM_Odm
);
u4Byte ODM_GetVersion_MP_8814A_PHY_REG(void);
/******************************************************************************
* PHY_REG_MP.TXT
******************************************************************************/
void
odm_read_and_config_mp_8814a_phy_reg_mp(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct * pDM_Odm
);
u4Byte ODM_GetVersion_MP_8814A_PHY_REG_MP(void);
/******************************************************************************
* PHY_REG_PG.TXT
******************************************************************************/
void
odm_read_and_config_mp_8814a_phy_reg_pg(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct * pDM_Odm
);
u4Byte ODM_GetVersion_MP_8814A_PHY_REG_PG(void);
/******************************************************************************
* PHY_REG_PG_Type2.TXT
******************************************************************************/
void
odm_read_and_config_mp_8814a_phy_reg_pg_type2(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct * pDM_Odm
);
u4Byte ODM_GetVersion_MP_8814A_PHY_REG_PG_Type2(void);
/******************************************************************************
* PHY_REG_PG_Type3.TXT
******************************************************************************/
void
odm_read_and_config_mp_8814a_phy_reg_pg_type3(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct * pDM_Odm
);
u4Byte ODM_GetVersion_MP_8814A_PHY_REG_PG_Type3(void);
/******************************************************************************
* PHY_REG_PG_Type5.TXT
******************************************************************************/
void
odm_read_and_config_mp_8814a_phy_reg_pg_type5(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct * pDM_Odm
);
u4Byte ODM_GetVersion_MP_8814A_PHY_REG_PG_Type5(void);
#endif
#endif /* end of HWIMG_SUPPORT*/

56
hal/phydm/rtl8814a/halhwimg8814a_fw.h 100644
View File

@ -0,0 +1,56 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#if (RTL8814A_SUPPORT == 1)
#ifndef __INC_MP_FW_HW_IMG_8814A_H
#define __INC_MP_FW_HW_IMG_8814A_H
/******************************************************************************
* FW_AP.TXT
******************************************************************************/
void
ODM_ReadFirmware_MP_8814A_FW_AP(
struct dm_struct *pDM_Odm,
u8 *pFirmware,
u32 *pFirmwareSize
);
u4Byte ODM_GetVersion_MP_8814A_FW_AP(void);
extern u32 array_length_mp_8814a_fw_ap;
extern u8 array_mp_8814a_fw_ap[];
/******************************************************************************
* FW_NIC.TXT
******************************************************************************/
void
ODM_ReadFirmware_MP_8814A_FW_NIC(
struct dm_struct *pDM_Odm,
u8 *pFirmware,
u32 *pFirmwareSize
);
u4Byte ODM_GetVersion_MP_8814A_FW_NIC(void);
extern u32 array_length_mp_8814a_fw_nic;
extern u8 array_mp_8814a_fw_nic[];
#endif
#endif // end of HWIMG_SUPPORT

325
hal/phydm/rtl8814a/halhwimg8814a_mac.c 100644
View File

@ -0,0 +1,325 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
/*Image2HeaderVersion: 2.19*/
#include "mp_precomp.h"
#include "../phydm_precomp.h"
#if (RTL8814A_SUPPORT == 1)
static BOOLEAN
CheckPositive(
struct dm_struct *pDM_Odm,
u32 Condition1,
u32 Condition2,
u32 Condition3,
u32 Condition4
)
{
u1Byte _BoardType = ((pDM_Odm->board_type & BIT4) >> 4) << 0 | /* _GLNA*/
((pDM_Odm->board_type & BIT3) >> 3) << 1 | /* _GPA*/
((pDM_Odm->board_type & BIT7) >> 7) << 2 | /* _ALNA*/
((pDM_Odm->board_type & BIT6) >> 6) << 3 | /* _APA */
((pDM_Odm->board_type & BIT2) >> 2) << 4; /* _BT*/
u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4;
u4Byte driver1 = pDM_Odm->cut_version << 24 |
(pDM_Odm->support_interface & 0xF0) << 16 |
pDM_Odm->support_platform << 16 |
pDM_Odm->package_type << 12 |
(pDM_Odm->support_interface & 0x0F) << 8 |
_BoardType;
u4Byte driver2 = (pDM_Odm->type_glna & 0xFF) << 0 |
(pDM_Odm->type_gpa & 0xFF) << 8 |
(pDM_Odm->type_alna & 0xFF) << 16 |
(pDM_Odm->type_apa & 0xFF) << 24;
u4Byte driver3 = 0;
u4Byte driver4 = (pDM_Odm->type_glna & 0xFF00) >> 8 |
(pDM_Odm->type_gpa & 0xFF00) |
(pDM_Odm->type_alna & 0xFF00) << 8 |
(pDM_Odm->type_apa & 0xFF00) << 16;
PHYDM_DBG(pDM_Odm, ODM_COMP_INIT,
"===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4);
PHYDM_DBG(pDM_Odm, ODM_COMP_INIT,
"===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4);
PHYDM_DBG(pDM_Odm, ODM_COMP_INIT,
" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->support_platform, pDM_Odm->support_interface);
PHYDM_DBG(pDM_Odm, ODM_COMP_INIT,
" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->board_type, pDM_Odm->package_type);
/*============== Value Defined Check ===============*/
/*QFN Type [15:12] and Cut Version [27:24] need to do value check*/
if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000)))
return FALSE;
if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000)))
return FALSE;
/*=============== Bit Defined Check ================*/
/* We don't care [31:28] */
cond1 &= 0x00FF0FFF;
driver1 &= 0x00FF0FFF;
if ((cond1 & driver1) == cond1) {
u4Byte bitMask = 0;
if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/
return TRUE;
if ((cond1 & BIT0) != 0) /*GLNA*/
bitMask |= 0x000000FF;
if ((cond1 & BIT1) != 0) /*GPA*/
bitMask |= 0x0000FF00;
if ((cond1 & BIT2) != 0) /*ALNA*/
bitMask |= 0x00FF0000;
if ((cond1 & BIT3) != 0) /*APA*/
bitMask |= 0xFF000000;
if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/
return TRUE;
else
return FALSE;
} else
return FALSE;
}
static BOOLEAN
CheckNegative(
struct dm_struct *pDM_Odm,
u32 Condition1,
u32 Condition2
)
{
return TRUE;
}
/******************************************************************************
* MAC_REG.TXT
******************************************************************************/
u4Byte Array_MP_8814A_MAC_REG[] = {
0x010, 0x0000007C,
0x014, 0x000000DB,
0x016, 0x00000002,
0x073, 0x00000010,
0x420, 0x00000080,
0x421, 0x0000000F,
0x428, 0x0000000A,
0x429, 0x00000010,
0x430, 0x00000000,
0x431, 0x00000000,
0x432, 0x00000000,
0x433, 0x00000001,
0x434, 0x00000004,
0x435, 0x00000005,
0x436, 0x00000007,
0x437, 0x00000008,
0x43C, 0x00000004,
0x43D, 0x00000005,
0x43E, 0x00000007,
0x43F, 0x00000008,
0x440, 0x0000005D,
0x441, 0x00000001,
0x442, 0x00000000,
0x444, 0x00000010,
0x445, 0x000000F0,
0x446, 0x00000001,
0x447, 0x000000FE,
0x448, 0x00000000,
0x449, 0x00000000,
0x44A, 0x00000000,
0x44B, 0x00000040,
0x44C, 0x00000010,
0x44D, 0x000000F0,
0x44E, 0x0000003F,
0x44F, 0x00000000,
0x450, 0x00000000,
0x451, 0x00000000,
0x452, 0x00000000,
0x453, 0x00000040,
0x45E, 0x00000004,
0x49C, 0x00000010,
0x49D, 0x000000F0,
0x49E, 0x00000000,
0x49F, 0x00000006,
0x4A0, 0x000000E0,
0x4A1, 0x00000003,
0x4A2, 0x00000000,
0x4A3, 0x00000040,
0x4A4, 0x00000015,
0x4A5, 0x000000F0,
0x4A6, 0x00000000,
0x4A7, 0x00000006,
0x4A8, 0x000000E0,
0x4A9, 0x00000000,
0x4AA, 0x00000000,
0x4AB, 0x00000000,
0x7DA, 0x00000008,
0x1448, 0x00000006,
0x144A, 0x00000006,
0x144C, 0x00000006,
0x144E, 0x00000006,
0x4C8, 0x000000FF,
0x4C9, 0x00000008,
0x4CA, 0x0000003C,
0x4CB, 0x0000003C,
0x4CC, 0x000000FF,
0x4CD, 0x000000FF,
0x4CE, 0x00000001,
0x4CF, 0x00000008,
0x500, 0x00000026,
0x501, 0x000000A2,
0x502, 0x0000002F,
0x503, 0x00000000,
0x504, 0x00000028,
0x505, 0x000000A3,
0x506, 0x0000005E,
0x507, 0x00000000,
0x508, 0x0000002B,
0x509, 0x000000A4,
0x50A, 0x0000005E,
0x50B, 0x00000000,
0x50C, 0x0000004F,
0x50D, 0x000000A4,
0x50E, 0x00000000,
0x50F, 0x00000000,
0x512, 0x0000001C,
0x514, 0x0000000A,
0x516, 0x0000000A,
0x521, 0x0000002F,
0x525, 0x0000004F,
0x550, 0x00000010,
0x551, 0x00000010,
0x559, 0x00000002,
0x55C, 0x00000064,
0x55D, 0x000000FF,
0x577, 0x00000003,
0x5BE, 0x00000064,
0x604, 0x00000001,
0x605, 0x00000030,
0x607, 0x00000001,
0x608, 0x0000000E,
0x609, 0x0000002A,
0x60A, 0x00000000,
0x60C, 0x00000018,
0x60D, 0x00000050,
0x6A0, 0x000000FF,
0x6A1, 0x000000FF,
0x6A2, 0x000000FF,
0x6A3, 0x000000FF,
0x6A4, 0x000000FF,
0x6A5, 0x000000FF,
0x6DE, 0x00000084,
0x620, 0x000000FF,
0x621, 0x000000FF,
0x622, 0x000000FF,
0x623, 0x000000FF,
0x624, 0x000000FF,
0x625, 0x000000FF,
0x626, 0x000000FF,
0x627, 0x000000FF,
0x638, 0x00000064,
0x63C, 0x0000000A,
0x63D, 0x0000000A,
0x63E, 0x0000000E,
0x63F, 0x0000000E,
0x640, 0x00000040,
0x642, 0x00000040,
0x643, 0x00000000,
0x652, 0x000000C8,
0x66E, 0x00000005,
0x700, 0x00000021,
0x701, 0x00000043,
0x702, 0x00000065,
0x703, 0x00000087,
0x708, 0x00000021,
0x709, 0x00000043,
0x70A, 0x00000065,
0x70B, 0x00000087,
0x718, 0x00000040,
0x7D5, 0x000000BC,
0x7D8, 0x00000028,
0x7D9, 0x00000000,
0x7DA, 0x0000000B,
};
void
odm_read_and_config_mp_8814a_mac_reg(
struct dm_struct * pDM_Odm
)
{
u4Byte i = 0;
u1Byte cCond;
BOOLEAN bMatched = TRUE, bSkipped = FALSE;
u4Byte ArrayLen = sizeof(Array_MP_8814A_MAC_REG)/sizeof(u4Byte);
pu4Byte Array = Array_MP_8814A_MAC_REG;
u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
PHYDM_DBG(pDM_Odm, ODM_COMP_INIT, "===> ODM_ReadAndConfig_MP_8814A_MAC_REG\n");
while ((i + 1) < ArrayLen) {
v1 = Array[i];
v2 = Array[i + 1];
if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/
if (v1 & BIT31) {/* positive condition*/
cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28);
if (cCond == COND_ENDIF) {/*end*/
bMatched = TRUE;
bSkipped = FALSE;
PHYDM_DBG(pDM_Odm, ODM_COMP_INIT, "ENDIF\n");
} else if (cCond == COND_ELSE) { /*else*/
bMatched = bSkipped?FALSE:TRUE;
PHYDM_DBG(pDM_Odm, ODM_COMP_INIT, "ELSE\n");
} else {/*if , else if*/
pre_v1 = v1;
pre_v2 = v2;
PHYDM_DBG(pDM_Odm, ODM_COMP_INIT, "IF or ELSE IF\n");
}
} else if (v1 & BIT30) { /*negative condition*/
if (bSkipped == FALSE) {
if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) {
bMatched = TRUE;
bSkipped = TRUE;
} else {
bMatched = FALSE;
bSkipped = FALSE;
}
} else
bMatched = FALSE;
}
} else {
if (bMatched)
odm_ConfigMAC_8814A(pDM_Odm, v1, (u1Byte)v2);
}
i = i + 2;
}
}
u4Byte
odm_get_version_mp_8814a_mac_reg(void)
{
return 85;
}
#endif /* end of HWIMG_SUPPORT*/

39
hal/phydm/rtl8814a/halhwimg8814a_mac.h 100644
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*Image2HeaderVersion: 2.19*/
#if (RTL8814A_SUPPORT == 1)
#ifndef __INC_MP_MAC_HW_IMG_8814A_H
#define __INC_MP_MAC_HW_IMG_8814A_H
/******************************************************************************
* MAC_REG.TXT
******************************************************************************/
void
odm_read_and_config_mp_8814a_mac_reg(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *pDM_Odm
);
u4Byte odm_get_version_mp_8814a_mac_reg(void);
#endif
#endif /* end of HWIMG_SUPPORT*/

8846
hal/phydm/rtl8814a/halhwimg8814a_rf.c 100644
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149
hal/phydm/rtl8814a/halhwimg8814a_rf.h 100644
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*Image2HeaderVersion: 2.19*/
#if (RTL8814A_SUPPORT == 1)
#ifndef __INC_MP_RF_HW_IMG_8814A_H
#define __INC_MP_RF_HW_IMG_8814A_H
/******************************************************************************
* RadioA.TXT
******************************************************************************/
void
odm_read_and_config_mp_8814a_radioa(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *pDM_Odm
);
u4Byte ODM_GetVersion_MP_8814A_RadioA(void);
/******************************************************************************
* RadioB.TXT
******************************************************************************/
void
odm_read_and_config_mp_8814a_radiob(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *pDM_Odm
);
u4Byte ODM_GetVersion_MP_8814A_RadioB(void);
/******************************************************************************
* RadioC.TXT
******************************************************************************/
void
odm_read_and_config_mp_8814a_radioc(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *pDM_Odm
);
u4Byte ODM_GetVersion_MP_8814A_RadioC(void);
/******************************************************************************
* RadioD.TXT
******************************************************************************/
void
odm_read_and_config_mp_8814a_radiod(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *pDM_Odm
);
u4Byte ODM_GetVersion_MP_8814A_RadioD(void);
/******************************************************************************
* TxPowerTrack.TXT
******************************************************************************/
void
odm_read_and_config_mp_8814a_txpowertrack(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *pDM_Odm
);
u4Byte ODM_GetVersion_MP_8814A_TxPowerTrack(void);
/******************************************************************************
* TxPowerTrack_Type0.TXT
******************************************************************************/
void
odm_read_and_config_mp_8814a_txpowertrack_type0(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *pDM_Odm
);
u4Byte ODM_GetVersion_MP_8814A_TxPowerTrack_Type0(void);
/******************************************************************************
* TxPowerTrack_Type2.TXT
******************************************************************************/
void
odm_read_and_config_mp_8814a_txpowertrack_type2(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *pDM_Odm
);
u4Byte ODM_GetVersion_MP_8814A_TxPowerTrack_Type2(void);
/******************************************************************************
* TxPowerTrack_Type5.TXT
******************************************************************************/
void
odm_read_and_config_mp_8814a_txpowertrack_type5(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *pDM_Odm
);
u4Byte ODM_GetVersion_MP_8814A_TxPowerTrack_Type5(void);
/******************************************************************************
* TXPWR_LMT.TXT
******************************************************************************/
void
odm_read_and_config_mp_8814a_txpwr_lmt(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *pDM_Odm
);
u4Byte ODM_GetVersion_MP_8814A_TXPWR_LMT(void);
/******************************************************************************
* TXPWR_LMT_type2.TXT
******************************************************************************/
void
odm_read_and_config_mp_8814a_txpwr_lmt_type2(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *pDM_Odm
);
u4Byte ODM_GetVersion_MP_8814A_TXPWR_LMT_type2(void);
/******************************************************************************
* TXPWR_LMT_Type3.TXT
******************************************************************************/
void
odm_read_and_config_mp_8814a_txpwr_lmt_type3(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *pDM_Odm
);
u4Byte ODM_GetVersion_MP_8814A_TXPWR_LMT_Type3(void);
/******************************************************************************
* TXPWR_LMT_Type5.TXT
******************************************************************************/
void
odm_read_and_config_mp_8814a_txpwr_lmt_type5(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *pDM_Odm
);
u4Byte ODM_GetVersion_MP_8814A_TXPWR_LMT_Type5(void);
#endif
#endif /* end of HWIMG_SUPPORT*/

1754
hal/phydm/rtl8814a/halphyrf_8814a_ap.c 100644
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164
hal/phydm/rtl8814a/halphyrf_8814a_ap.h 100644
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HAL_PHY_RF_8814A_H__
#define __HAL_PHY_RF_8814A_H__
/*--------------------------Define Parameters-------------------------------*/
#define IQK_DELAY_TIME_8814A 10 //ms
#define index_mapping_NUM_8814A 15
#define AVG_THERMAL_NUM_8814A 4
#define RF_T_METER_8814A 0x42
#define MAX_PATH_NUM_8814A 4
#include "../halphyrf_ap.h"
void ConfigureTxpowerTrack_8814A(
PTXPWRTRACK_CFG pConfig
);
VOID
GetDeltaSwingTable_8814A(
struct dm_struct *pDM_Odm,
u8* *TemperatureUP_A,
u8* *TemperatureDOWN_A,
u8* *TemperatureUP_B,
u8* *TemperatureDOWN_B
);
VOID
GetDeltaSwingTable_8814A_PathCD(
struct dm_struct *pDM_Odm,
u8* *TemperatureUP_C,
u8* *TemperatureDOWN_C,
u8* *TemperatureUP_D,
u8* *TemperatureDOWN_D
);
VOID
ConfigureTxpowerTrack_8814A(
IN PTXPWRTRACK_CFG pConfig
);
VOID
ODM_TxPwrTrackSetPwr8814A(
IN PDM_ODM_T pDM_Odm,
IN PWRTRACK_METHOD Method,
IN u1Byte RFPath,
IN u1Byte ChannelMappedIndex
);
u1Byte
CheckRFGainOffset(
PDM_ODM_T pDM_Odm,
PWRTRACK_METHOD Method,
u1Byte RFPath
);
//
// LC calibrate
//
void
PHY_LCCalibrate_8814A(
IN PDM_ODM_T pDM_Odm
);
void
phy_LCCalibrate_8814A(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN BOOLEAN is2T
);
//
// AP calibrate
//
void
PHY_APCalibrate_8814A(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN s1Byte delta);
void
PHY_DigitalPredistortion_8814A( IN PADAPTER pAdapter);
#if 0 //FOR_8814_IQK
VOID
_PHY_SaveADDARegisters(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN pu4Byte ADDAReg,
IN pu4Byte ADDABackup,
IN u4Byte RegisterNum
);
VOID
_PHY_PathADDAOn(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN pu4Byte ADDAReg,
IN BOOLEAN isPathAOn,
IN BOOLEAN is2T
);
VOID
_PHY_MACSettingCalibration(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN pu4Byte MACReg,
IN pu4Byte MACBackup
);
VOID
_PHY_PathAStandBy(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm
#else
IN PADAPTER pAdapter
#endif
);
#endif
#endif // #ifndef __HAL_PHY_RF_8814A_H__

528
hal/phydm/rtl8814a/halphyrf_8814a_win.c 100644
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@ -0,0 +1,528 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#include "mp_precomp.h"
#include "../phydm_precomp.h"
#if (RTL8814A_SUPPORT == 1)
/*---------------------------Define Local Constant---------------------------*/
// 2010/04/25 MH Define the max tx power tracking tx agc power.
#define ODM_TXPWRTRACK_MAX_IDX_8814A 6
/*---------------------------Define Local Constant---------------------------*/
//3============================================================
//3 Tx Power Tracking
//3============================================================
// Add CheckRFGainOffset By YuChen to make sure that RF gain offset will not over upperbound 4'b1010
u1Byte
CheckRFGainOffset(
PDM_ODM_T pDM_Odm,
u1Byte RFPath
)
{
u1Byte UpperBound = 10; // 4'b1010 = 10
u1Byte Final_RF_Index = 0;
BOOLEAN bPositive = FALSE;
PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
if( pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] >= 0) // check if RF_Index is positive or not
{
Final_RF_Index = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] >> 1;
bPositive = TRUE;
ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)RFPath, rRF_TxGainOffset, BIT15, bPositive);
}
else
{
Final_RF_Index = (-1)*pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] >> 1;
bPositive = FALSE;
ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)RFPath, rRF_TxGainOffset, BIT15, bPositive);
}
if(bPositive == TRUE)
{
if(Final_RF_Index >= UpperBound)
{
ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)RFPath, rRF_TxGainOffset, 0xF0000, UpperBound); //set RF Reg0x55 per path
return UpperBound;
}
else
{
ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)RFPath, rRF_TxGainOffset, 0xF0000, Final_RF_Index); //set RF Reg0x55 per path
return Final_RF_Index;
}
}
else
{
ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)RFPath, rRF_TxGainOffset, 0xF0000, Final_RF_Index); //set RF Reg0x55 per path
return Final_RF_Index;
}
return FALSE;
}
VOID
ODM_TxPwrTrackSetPwr8814A(
PDM_ODM_T pDM_Odm,
PWRTRACK_METHOD Method,
u1Byte RFPath,
u1Byte ChannelMappedIndex
)
{
u1Byte Final_OFDM_Swing_Index = 0;
u1Byte Final_CCK_Swing_Index = 0;
u1Byte Final_RF_Index = 0;
u1Byte UpperBound = 10, TxScalingUpperBound = 28; // Upperbound = 4'b1010, TxScalingUpperBound = +2 dB
PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
if (Method == MIX_MODE)
{
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("pRFCalibrateInfo->DefaultOfdmIndex=%d, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d, RF_Path = %d\n",
pRFCalibrateInfo->DefaultOfdmIndex, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath], RFPath));
Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath];
Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath])%2;
Final_RF_Index = CheckRFGainOffset(pDM_Odm, RFPath); // check if Final_RF_Index >= 10
if((Final_RF_Index == UpperBound) && (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] >= 0)) // check BBSW is not over +2dB
{
Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + (pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath] - (UpperBound << 1));
if(Final_OFDM_Swing_Index > TxScalingUpperBound)
Final_OFDM_Swing_Index = TxScalingUpperBound;
}
switch(RFPath)
{
case ODM_RF_PATH_A:
ODM_SetBBReg(pDM_Odm, rA_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[Final_OFDM_Swing_Index]); //set BBswing
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("******Path_A Compensate with BBSwing , Final_OFDM_Swing_Index = %d, Final_RF_Index = %d \n", Final_OFDM_Swing_Index, Final_RF_Index));
break;
case ODM_RF_PATH_B:
ODM_SetBBReg(pDM_Odm, rB_TxScale_Jaguar, 0xFFE00000, TxScalingTable_Jaguar[Final_OFDM_Swing_Index]); //set BBswing
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("******Path_B Compensate with BBSwing , Final_OFDM_Swing_Index = %d, Final_RF_Index = %d \n", Final_OFDM_Swing_Index, Final_RF_Index));
break;
case ODM_RF_PATH_C:
ODM_SetBBReg(pDM_Odm, rC_TxScale_Jaguar2, 0xFFE00000, TxScalingTable_Jaguar[Final_OFDM_Swing_Index]); //set BBswing
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("******Path_C Compensate with BBSwing , Final_OFDM_Swing_Index = %d, Final_RF_Index = %d \n", Final_OFDM_Swing_Index, Final_RF_Index));
break;
case ODM_RF_PATH_D:
ODM_SetBBReg(pDM_Odm, rD_TxScale_Jaguar2, 0xFFE00000, TxScalingTable_Jaguar[Final_OFDM_Swing_Index]); //set BBswing
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("******Path_D Compensate with BBSwing , Final_OFDM_Swing_Index = %d, Final_RF_Index = %d \n", Final_OFDM_Swing_Index, Final_RF_Index));
break;
default:
ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,
("Wrong Path name!!!! \n"));
break;
}
}
return;
} // ODM_TxPwrTrackSetPwr8814A
VOID
GetDeltaSwingTable_8814A(
IN PDM_ODM_T pDM_Odm,
OUT pu1Byte *TemperatureUP_A,
OUT pu1Byte *TemperatureDOWN_A,
OUT pu1Byte *TemperatureUP_B,
OUT pu1Byte *TemperatureDOWN_B
)
{
PADAPTER Adapter = pDM_Odm->Adapter;
PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
u1Byte TxRate = 0xFF;
u1Byte channel = pHalData->CurrentChannel;
if (pDM_Odm->mp_mode == TRUE) {
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
#if (MP_DRIVER == 1)
PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx);
TxRate = MptToMgntRate(pMptCtx->MptRateIndex);
#endif
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx);
TxRate = MptToMgntRate(pMptCtx->MptRateIndex);
#endif
#endif
} else {
u2Byte rate = *(pDM_Odm->pForcedDataRate);
if (!rate) { /*auto rate*/
if (rate != 0xFF) {
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate);
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
TxRate = HwRateToMRate(pDM_Odm->TxRate);
#endif
}
} else { /*force rate*/
TxRate = (u1Byte)rate;
}
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate));
if (1 <= channel && channel <= 14) {
if (IS_CCK_RATE(TxRate)) {
*TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P;
*TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N;
*TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P;
*TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N;
} else {
*TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P;
*TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N;
*TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P;
*TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N;
}
} else if (36 <= channel && channel <= 64) {
*TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[0];
*TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[0];
*TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[0];
*TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[0];
} else if (100 <= channel && channel <= 144) {
*TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[1];
*TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[1];
*TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[1];
*TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[1];
} else if (149 <= channel && channel <= 173) {
*TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[2];
*TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[2];
*TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[2];
*TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[2];
} else {
*TemperatureUP_A = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E;
*TemperatureDOWN_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E;
*TemperatureUP_B = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E;
*TemperatureDOWN_B = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E;
}
return;
}
VOID
GetDeltaSwingTable_8814A_PathCD(
IN PDM_ODM_T pDM_Odm,
OUT pu1Byte *TemperatureUP_C,
OUT pu1Byte *TemperatureDOWN_C,
OUT pu1Byte *TemperatureUP_D,
OUT pu1Byte *TemperatureDOWN_D
)
{
PADAPTER Adapter = pDM_Odm->Adapter;
PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo);
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
u1Byte TxRate = 0xFF;
u1Byte channel = pHalData->CurrentChannel;
if (pDM_Odm->mp_mode == TRUE) {
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
#if (MP_DRIVER == 1)
PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx);
TxRate = MptToMgntRate(pMptCtx->MptRateIndex);
#endif
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx);
TxRate = MptToMgntRate(pMptCtx->MptRateIndex);
#endif
#endif
} else {
u2Byte rate = *(pDM_Odm->pForcedDataRate);
if (!rate) { /*auto rate*/
if (rate != 0xFF) {
#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate);
#elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
TxRate = HwRateToMRate(pDM_Odm->TxRate);
#endif
}
} else { /*force rate*/
TxRate = (u1Byte)rate;
}
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate));
if ( 1 <= channel && channel <= 14) {
if (IS_CCK_RATE(TxRate)) {
*TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_P;
*TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKC_N;
*TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_P;
*TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKD_N;
} else {
*TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_2GC_P;
*TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_2GC_N;
*TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_2GD_P;
*TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_2GD_N;
}
} else if (36 <= channel && channel <= 64) {
*TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P[0];
*TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N[0];
*TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P[0];
*TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N[0];
} else if (100 <= channel && channel <= 144) {
*TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P[1];
*TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N[1];
*TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P[1];
*TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N[1];
} else if (149 <= channel && channel <= 173) {
*TemperatureUP_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_P[2];
*TemperatureDOWN_C = pRFCalibrateInfo->DeltaSwingTableIdx_5GC_N[2];
*TemperatureUP_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_P[2];
*TemperatureDOWN_D = pRFCalibrateInfo->DeltaSwingTableIdx_5GD_N[2];
} else {
*TemperatureUP_C = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E;
*TemperatureDOWN_C = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E;
*TemperatureUP_D = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E;
*TemperatureDOWN_D = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E;
}
return;
}
void ConfigureTxpowerTrack_8814A(
PTXPWRTRACK_CFG pConfig
)
{
pConfig->SwingTableSize_CCK = CCK_TABLE_SIZE;
pConfig->SwingTableSize_OFDM = OFDM_TABLE_SIZE;
pConfig->Threshold_IQK = 8;
pConfig->AverageThermalNum = AVG_THERMAL_NUM_8814A;
pConfig->RfPathCount = MAX_PATH_NUM_8814A;
pConfig->ThermalRegAddr = RF_T_METER_88E;
pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr8814A;
pConfig->DoIQK = DoIQK_8814A;
pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8814A;
pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8814A;
pConfig->GetDeltaSwingTable8814only = GetDeltaSwingTable_8814A_PathCD;
}
VOID
phy_LCCalibrate_8814A(
IN PDM_ODM_T pDM_Odm,
IN BOOLEAN is2T
)
{
u4Byte LC_Cal = 0, cnt;
//Check continuous TX and Packet TX
u4Byte reg0x914 = ODM_Read4Byte(pDM_Odm, rSingleTone_ContTx_Jaguar);;
// Backup RF reg18.
LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask);
if((reg0x914 & 0x70000) == 0)
ODM_Write1Byte(pDM_Odm, REG_TXPAUSE_8812A, 0xFF);
//3 3. Read RF reg18
LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask);
//3 4. Set LC calibration begin bit15
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, LC_Cal|0x08000);
ODM_delay_ms(100);
for (cnt = 0; cnt < 100; cnt++) {
if (ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x8000) != 0x1)
break;
ODM_delay_ms(10);
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("retry cnt = %d\n", cnt));
//3 Restore original situation
if((reg0x914 & 70000) == 0)
ODM_Write1Byte(pDM_Odm, REG_TXPAUSE_8812A, 0x00);
// Recover channel number
ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, LC_Cal);
DbgPrint("Call %s\n", __FUNCTION__);
}
VOID
phy_APCalibrate_8814A(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN s1Byte delta,
IN BOOLEAN is2T
)
{
}
VOID
PHY_LCCalibrate_8814A(
IN PDM_ODM_T pDM_Odm
)
{
#if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
PADAPTER pAdapter = pDM_Odm->Adapter;
#if (MP_DRIVER == 1)
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx);
#else
PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
#endif
#endif
#endif
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> PHY_LCCalibrate_8814A\n"));
//#if (MP_DRIVER == 1)
phy_LCCalibrate_8814A(pDM_Odm, TRUE);
//#endif
ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<=== PHY_LCCalibrate_8814A\n"));
}
VOID
PHY_APCalibrate_8814A(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN s1Byte delta
)
{
}
VOID
PHY_DPCalibrate_8814A(
IN PDM_ODM_T pDM_Odm
)
{
}
BOOLEAN
phy_QueryRFPathSwitch_8814A(
IN PADAPTER pAdapter
)
{
return TRUE;
}
BOOLEAN PHY_QueryRFPathSwitch_8814A(
IN PADAPTER pAdapter
)
{
#if DISABLE_BB_RF
return TRUE;
#endif
return phy_QueryRFPathSwitch_8814A(pAdapter);
}
VOID phy_SetRFPathSwitch_8814A(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN BOOLEAN bMain,
IN BOOLEAN is2T
)
{
}
VOID PHY_SetRFPathSwitch_8814A(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN BOOLEAN bMain
)
{
}
#else /* (RTL8814A_SUPPORT == 0)*/
VOID
PHY_LCCalibrate_8814A(
IN PDM_ODM_T pDM_Odm
){}
VOID
PHY_IQCalibrate_8814A(
IN PDM_ODM_T pDM_Odm,
IN BOOLEAN bReCovery
){}
#endif /* (RTL8814A_SUPPORT == 0)*/

106
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HAL_PHY_RF_8814A_H__
#define __HAL_PHY_RF_8814A_H__
/*--------------------------Define Parameters-------------------------------*/
#define AVG_THERMAL_NUM_8814A 4
#include "halphyrf_win.h"
void ConfigureTxpowerTrack_8814A(
PTXPWRTRACK_CFG pConfig
);
VOID
GetDeltaSwingTable_8814A(
IN PDM_ODM_T pDM_Odm,
OUT pu1Byte *TemperatureUP_A,
OUT pu1Byte *TemperatureDOWN_A,
OUT pu1Byte *TemperatureUP_B,
OUT pu1Byte *TemperatureDOWN_B
);
VOID
GetDeltaSwingTable_8814A_PathCD(
IN PDM_ODM_T pDM_Odm,
OUT pu1Byte *TemperatureUP_C,
OUT pu1Byte *TemperatureDOWN_C,
OUT pu1Byte *TemperatureUP_D,
OUT pu1Byte *TemperatureDOWN_D
);
VOID
ODM_TxPwrTrackSetPwr8814A(
PDM_ODM_T pDM_Odm,
PWRTRACK_METHOD Method,
u1Byte RFPath,
u1Byte ChannelMappedIndex
);
u1Byte
CheckRFGainOffset(
PDM_ODM_T pDM_Odm,
u1Byte RFPath
);
//
// LC calibrate
//
void
PHY_LCCalibrate_8814A(
IN PDM_ODM_T pDM_Odm
);
//
// AP calibrate
//
void
PHY_APCalibrate_8814A(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN s1Byte delta
);
VOID
PHY_DPCalibrate_8814A(
IN PDM_ODM_T pDM_Odm
);
VOID PHY_SetRFPathSwitch_8814A(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN BOOLEAN bMain
);
#endif // #ifndef __HAL_PHY_RF_8188E_H__

219
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#include "mp_precomp.h"
#include "../phydm_precomp.h"
#if (RTL8814A_SUPPORT == 1)
void
odm_ConfigRFReg_8814A(
struct dm_struct *pDM_Odm,
u32 Addr,
u32 Data,
enum rf_path RF_PATH,
u32 RegAddr
)
{
if(Addr == 0xfe || Addr == 0xffe)
{
#ifdef CONFIG_LONG_DELAY_ISSUE
ODM_sleep_ms(50);
#else
ODM_delay_ms(50);
#endif
}
else
{
odm_set_rf_reg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data);
// Add 1us delay between BB/RF register setting.
ODM_delay_us(1);
}
}
void
odm_ConfigRF_RadioA_8814A(
struct dm_struct *pDM_Odm,
u32 Addr,
u32 Data
)
{
u4Byte content = 0x1000; // RF_Content: radioa_txt
u4Byte maskforPhySet= (u4Byte)(content&0xE000);
odm_ConfigRFReg_8814A(pDM_Odm, Addr, Data, RF_PATH_A, Addr|maskforPhySet);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data));
}
void
odm_ConfigRF_RadioB_8814A(
struct dm_struct *pDM_Odm,
u32 Addr,
u32 Data
)
{
u4Byte content = 0x1001; // RF_Content: radiob_txt
u4Byte maskforPhySet= (u4Byte)(content&0xE000);
odm_ConfigRFReg_8814A(pDM_Odm, Addr, Data, RF_PATH_B, Addr|maskforPhySet);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioB] %08X %08X\n", Addr, Data));
}
void
odm_ConfigRF_RadioC_8814A(
struct dm_struct *pDM_Odm,
u32 Addr,
u32 Data
)
{
u4Byte content = 0x1001; // RF_Content: radiob_txt
u4Byte maskforPhySet= (u4Byte)(content&0xE000);
odm_ConfigRFReg_8814A(pDM_Odm, Addr, Data, RF_PATH_C, Addr|maskforPhySet);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioC] %08X %08X\n", Addr, Data));
}
void
odm_ConfigRF_RadioD_8814A(
struct dm_struct *pDM_Odm,
u32 Addr,
u32 Data
)
{
u4Byte content = 0x1001; // RF_Content: radiob_txt
u4Byte maskforPhySet= (u4Byte)(content&0xE000);
odm_ConfigRFReg_8814A(pDM_Odm, Addr, Data, RF_PATH_D, Addr|maskforPhySet);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioD] %08X %08X\n", Addr, Data));
}
void
odm_ConfigMAC_8814A(
struct dm_struct *pDM_Odm,
u32 Addr,
IN u1Byte Data
)
{
odm_write_1byte(pDM_Odm, Addr, Data);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data));
}
void
odm_ConfigBB_AGC_8814A(
struct dm_struct *pDM_Odm,
u32 Addr,
u32 Bitmask,
u32 Data
)
{
odm_set_bb_reg(pDM_Odm, Addr, Bitmask, Data);
// Add 1us delay between BB/RF register setting.
ODM_delay_us(1);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data));
}
void
odm_ConfigBB_PHY_REG_PG_8814A(
struct dm_struct *pDM_Odm,
u32 Band,
u32 RfPath,
u32 TxNum,
u32 Addr,
u32 Bitmask,
u32 Data
)
{
if (Addr == 0xfe || Addr == 0xffe)
#ifdef CONFIG_LONG_DELAY_ISSUE
ODM_sleep_ms(50);
#else
ODM_delay_ms(50);
#endif
else
{
#if !(DM_ODM_SUPPORT_TYPE&ODM_AP)
phy_store_tx_power_by_rate(pDM_Odm->adapter, Band, RfPath, TxNum, Addr, Bitmask, Data);
#endif
}
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", Addr, Bitmask, Data));
}
void
odm_ConfigBB_PHY_8814A(
struct dm_struct *pDM_Odm,
u32 Addr,
u32 Bitmask,
u32 Data
)
{
if (Addr == 0xfe)
#ifdef CONFIG_LONG_DELAY_ISSUE
ODM_sleep_ms(50);
#else
ODM_delay_ms(50);
#endif
else if (Addr == 0xfd)
ODM_delay_ms(5);
else if (Addr == 0xfc)
ODM_delay_ms(1);
else if (Addr == 0xfb)
ODM_delay_us(50);
else if (Addr == 0xfa)
ODM_delay_us(5);
else if (Addr == 0xf9)
ODM_delay_us(1);
else
{
odm_set_bb_reg(pDM_Odm, Addr, Bitmask, Data);
}
// Add 1us delay between BB/RF register setting.
ODM_delay_us(1);
ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data));
}
void
odm_ConfigBB_TXPWR_LMT_8814A(
struct dm_struct *pDM_Odm,
u8* Regulation,
u8* Band,
u8* Bandwidth,
u8* RateSection,
u8* RfPath,
u8* Channel,
u8* PowerLimit
)
{
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
phy_set_tx_power_limit(pDM_Odm, Regulation, Band,
Bandwidth, RateSection, RfPath, Channel, PowerLimit);
#endif
}
#endif

109
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __INC_ODM_REGCONFIG_H_8814A
#define __INC_ODM_REGCONFIG_H_8814A
#if (RTL8814A_SUPPORT == 1)
void
odm_ConfigRFReg_8814A(
struct dm_struct *pDM_Odm,
u32 Addr,
u32 Data,
enum rf_path RF_PATH,
u32 RegAddr
);
void
odm_ConfigRF_RadioA_8814A(
struct dm_struct *pDM_Odm,
u32 Addr,
u32 Data
);
void
odm_ConfigRF_RadioB_8814A(
struct dm_struct *pDM_Odm,
u32 Addr,
u32 Data
);
void
odm_ConfigRF_RadioC_8814A(
struct dm_struct *pDM_Odm,
u32 Addr,
u32 Data
);
void
odm_ConfigRF_RadioD_8814A(
struct dm_struct *pDM_Odm,
u32 Addr,
u32 Data
);
void
odm_ConfigMAC_8814A(
struct dm_struct *pDM_Odm,
u32 Addr,
IN u1Byte Data
);
void
odm_ConfigBB_AGC_8814A(
struct dm_struct *pDM_Odm,
u32 Addr,
u32 Bitmask,
u32 Data
);
void
odm_ConfigBB_PHY_REG_PG_8814A(
struct dm_struct *pDM_Odm,
u32 Band,
u32 RfPath,
u32 TxNum,
u32 Addr,
u32 Bitmask,
u32 Data
);
void
odm_ConfigBB_PHY_8814A(
struct dm_struct *pDM_Odm,
u32 Addr,
u32 Bitmask,
u32 Data
);
void
odm_ConfigBB_TXPWR_LMT_8814A(
struct dm_struct *pDM_Odm,
u8* Regulation,
u8* Band,
u8* Bandwidth,
u8* RateSection,
u8* RfPath,
u8* Channel,
u8* PowerLimit
);
#endif
#endif // end of SUPPORT

503
hal/phydm/rtl8814a/phydm_rtl8814a.c 100644
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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//============================================================
// include files
//============================================================
#include "mp_precomp.h"
#include "../phydm_precomp.h"
#if (RTL8814A_SUPPORT == 1)
s8 phydm_cck_rssi_8814a(struct dm_struct *dm, u16 lna_idx, u8 vga_idx)
{
s8 rx_pwr_all = 0;
switch (lna_idx) {
case 7:
if (vga_idx <= 27)
rx_pwr_all = -94 + 2 * (27 - vga_idx);
else
rx_pwr_all = -94;
break;
case 6:
rx_pwr_all = -42 + 2 * (2 - vga_idx);
break;
case 5:
rx_pwr_all = -36 + 2 * (7 - vga_idx);
break;
case 4:
rx_pwr_all = -30 + 2 * (7 - vga_idx);
break;
case 3:
rx_pwr_all = -18 + 2 * (7 - vga_idx);
break;
case 2:
rx_pwr_all = 2 * (5 - vga_idx);
break;
case 1:
rx_pwr_all = 14 - 2 * vga_idx;
break;
case 0:
rx_pwr_all = 20 - 2 * vga_idx;
break;
default:
break;
}
return rx_pwr_all;
}
#ifdef PHYDM_PRIMARY_CCA
VOID
odm_Write_Dynamic_CCA_8814A(
struct dm_struct *pDM_Odm,
u8 CurrentMFstate
)
{
struct phydm_pri_cca_struct* PrimaryCCA = &(pDM_Odm->dm_pri_cca);
if (PrimaryCCA->MF_state != CurrentMFstate){
ODM_SetBBReg(pDM_Odm, ODM_REG_L1SBD_PD_CH_11N, BIT8|BIT7, CurrentMFstate);
}
PrimaryCCA->MF_state = CurrentMFstate;
}
VOID
odm_PrimaryCCA_Check_Init_8814A(
struct dm_struct *pDM_Odm)
{
#if ((DM_ODM_SUPPORT_TYPE == ODM_WIN) || (DM_ODM_SUPPORT_TYPE == ODM_AP))
PADAPTER pAdapter = pDM_Odm->Adapter;
struct phydm_pri_cca_struct* PrimaryCCA = &(pDM_Odm->dm_pri_cca);
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
pHalData->RTSEN = 0;
PrimaryCCA->DupRTS_flag = 0;
PrimaryCCA->intf_flag = 0;
PrimaryCCA->intf_type = 0;
PrimaryCCA->Monitor_flag = 0;
PrimaryCCA->PriCCA_flag = 0;
PrimaryCCA->CH_offset = 0;
PrimaryCCA->MF_state = 0;
#endif /*((DM_ODM_SUPPORT_TYPE==ODM_WIN) ||(DM_ODM_SUPPORT_TYPE==ODM_AP)) */
}
VOID
odm_DynamicPrimaryCCA_Check_8814A(
struct dm_struct *pDM_Odm
)
{
if(pDM_Odm->SupportICType != ODM_RTL8814A)
return;
switch (pDM_Odm->SupportPlatform)
{
case ODM_WIN:
#if(DM_ODM_SUPPORT_TYPE==ODM_WIN)
odm_DynamicPrimaryCCAMP_8814A(pDM_Odm);
#endif
break;
case ODM_CE:
#if(DM_ODM_SUPPORT_TYPE==ODM_CE)
#endif
break;
case ODM_AP:
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
odm_DynamicPrimaryCCAAP_8814A(pDM_Odm);
#endif
break;
}
}
#if(DM_ODM_SUPPORT_TYPE==ODM_WIN)
VOID
odm_DynamicPrimaryCCAMP_8814A(
struct dm_struct *pDM_Odm
)
{
PADAPTER pAdapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm, PHYDM_FALSEALMCNT);
struct phydm_pri_cca_struct* PrimaryCCA = &(pDM_Odm->dm_pri_cca);
BOOLEAN Is40MHz = FALSE;
u8Byte OFDM_CCA, OFDM_FA, BW_USC_Cnt, BW_LSC_Cnt;
u8 SecCHOffset;
u8 CurMFstate;
static u8 CountDown = Monitor_TIME;
OFDM_CCA = FalseAlmCnt->Cnt_OFDM_CCA;
OFDM_FA = FalseAlmCnt->Cnt_Ofdm_fail;
BW_USC_Cnt = FalseAlmCnt->Cnt_BW_USC;
BW_LSC_Cnt = FalseAlmCnt->Cnt_BW_LSC;
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("8814A: OFDM CCA=%d\n", OFDM_CCA));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("8814A: OFDM FA=%d\n", OFDM_FA));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("8814A: BW_USC=%d\n", BW_USC_Cnt));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("8814A: BW_LSC=%d\n", BW_LSC_Cnt));
Is40MHz = *(pDM_Odm->pBandWidth);
SecCHOffset = *(pDM_Odm->pSecChOffset); // NIC: 2: sec is below, 1: sec is above
//DbgPrint("8814A: SecCHOffset = %d\n", SecCHOffset);
if(!pDM_Odm->bLinked){
return;
}
else{
if(Is40MHz){
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("8814A: Cont Down= %d\n", CountDown));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("8814A: Primary_CCA_flag=%d\n", PrimaryCCA->PriCCA_flag));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("8814A: Intf_Type=%d\n", PrimaryCCA->intf_type));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("8814A: Intf_flag=%d\n", PrimaryCCA->intf_flag ));
ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_PRICCA, ODM_DBG_LOUD, ("8814A: Duplicate RTS Flag=%d\n", PrimaryCCA->DupRTS_flag));
//DbgPrint("8814A RTS_EN=%d\n", pHalData->RTSEN);
if(PrimaryCCA->PriCCA_flag == 0){
if(SecCHOffset == 2){ // Primary channel is above NOTE: duplicate CTS can remove this condition
if((OFDM_CCA > OFDMCCA_TH) && (BW_LSC_Cnt>(BW_USC_Cnt + BW_Ind_Bias))
&& (OFDM_FA>(OFDM_CCA>>1))){
PrimaryCCA->intf_type = 1;
PrimaryCCA->intf_flag = 1;
CurMFstate = MF_USC;
odm_Write_Dynamic_CCA_8814A(pDM_Odm, CurMFstate);
PrimaryCCA->PriCCA_flag = 1;
}
else if((OFDM_CCA > OFDMCCA_TH) && (BW_LSC_Cnt>(BW_USC_Cnt + BW_Ind_Bias))
&& (OFDM_FA < (OFDM_CCA>>1))){
PrimaryCCA->intf_type = 2;
PrimaryCCA->intf_flag = 1;
CurMFstate = MF_USC;
odm_Write_Dynamic_CCA_8814A(pDM_Odm, CurMFstate);
PrimaryCCA->PriCCA_flag = 1;
PrimaryCCA->DupRTS_flag = 1;
pHalData->RTSEN = 1;
}
else{
PrimaryCCA->intf_type = 0;
PrimaryCCA->intf_flag = 0;
CurMFstate = MF_USC_LSC;
odm_Write_Dynamic_CCA_8814A(pDM_Odm, CurMFstate);
pHalData->RTSEN = 0;
PrimaryCCA->DupRTS_flag = 0;
}
}
else if (SecCHOffset == 1){
if((OFDM_CCA > OFDMCCA_TH) && (BW_USC_Cnt > (BW_LSC_Cnt + BW_Ind_Bias))
&& (OFDM_FA > (OFDM_CCA>>1))){
PrimaryCCA->intf_type = 1;
PrimaryCCA->intf_flag = 1;
CurMFstate = MF_LSC;
odm_Write_Dynamic_CCA_8814A(pDM_Odm, CurMFstate);
PrimaryCCA->PriCCA_flag = 1;
}
else if((OFDM_CCA > OFDMCCA_TH) && (BW_USC_Cnt>(BW_LSC_Cnt + BW_Ind_Bias))
&& (OFDM_FA < (OFDM_CCA>>1))){
PrimaryCCA->intf_type = 2;
PrimaryCCA->intf_flag = 1;
CurMFstate = MF_LSC;
odm_Write_Dynamic_CCA_8814A(pDM_Odm, CurMFstate);
PrimaryCCA->PriCCA_flag = 1;
PrimaryCCA->DupRTS_flag = 1;
pHalData->RTSEN = 1;
}
else{
PrimaryCCA->intf_type = 0;
PrimaryCCA->intf_flag = 0;
CurMFstate = MF_USC_LSC;
odm_Write_Dynamic_CCA_8814A(pDM_Odm, CurMFstate);
pHalData->RTSEN = 0;
PrimaryCCA->DupRTS_flag = 0;
}
}
}
else{ // PrimaryCCA->PriCCA_flag==1
CountDown--;
if(CountDown == 0){
CountDown = Monitor_TIME;
PrimaryCCA->PriCCA_flag = 0;
CurMFstate = MF_USC_LSC;
odm_Write_Dynamic_CCA_8814A(pDM_Odm, CurMFstate); /* default*/
pHalData->RTSEN = 0;
PrimaryCCA->DupRTS_flag = 0;
PrimaryCCA->intf_type = 0;
PrimaryCCA->intf_flag = 0;
}
}
}
else{
return;
}
}
}
#elif(DM_ODM_SUPPORT_TYPE == ODM_AP)
VOID
odm_DynamicPrimaryCCAAP_8814A(
struct dm_struct *pDM_Odm
)
{
PADAPTER Adapter = pDM_Odm->Adapter;
prtl8192cd_priv priv = pDM_Odm->priv;
PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm, PHYDM_FALSEALMCNT);
struct phydm_pri_cca_struct* PrimaryCCA = &(pDM_Odm->dm_pri_cca);
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
u8 i;
static u4Byte Count_Down = Monitor_TIME;
BOOLEAN STA_BW = FALSE, STA_BW_pre = FALSE, STA_BW_TMP = FALSE;
BOOLEAN bConnected = FALSE;
BOOLEAN Is40MHz = FALSE;
u8 SecCHOffset;
u8 CurMFstate;
PSTA_INFO_T pstat;
Is40MHz = *(pDM_Odm->pBandWidth);
SecCHOffset = *(pDM_Odm->pSecChOffset); // AP: 1: sec is below, 2: sec is above
for(i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++){
pstat = pDM_Odm->pODM_StaInfo[i];
if(IS_STA_VALID(pstat)){
STA_BW_TMP = pstat->tx_bw;
if(STA_BW_TMP > STA_BW){
STA_BW = STA_BW_TMP;
}
bConnected = TRUE;
}
}
if(Is40MHz){
if(PrimaryCCA->PriCCA_flag == 0){
if(bConnected){
if(STA_BW == 0){ //2 STA BW=20M
PrimaryCCA->PriCCA_flag = 1;
if(SecCHOffset==1){
CurMFstate = MF_USC;
odm_Write_Dynamic_CCA_8814A(pDM_Odm, CurMFstate);
}
else if(SecCHOffset==2){
CurMFstate = MF_USC;
odm_Write_Dynamic_CCA_8814A(pDM_Odm, CurMFstate);
}
}
else{ //2 STA BW=40M
if(PrimaryCCA->intf_flag == 0){
odm_Intf_Detection(pDM_Odm);
}
else{ // intf_flag = 1
if(PrimaryCCA->intf_type == 1){
if(PrimaryCCA->CH_offset == 1){
CurMFstate = MF_USC;
if(SecCHOffset == 1){ // AP, 1: primary is above 2: primary is below
odm_Write_Dynamic_CCA_8814A(pDM_Odm, CurMFstate);
}
}
else if(PrimaryCCA->CH_offset == 2){
CurMFstate = MF_LSC;
if(SecCHOffset == 2){
odm_Write_Dynamic_CCA_8814A(pDM_Odm, CurMFstate);
}
}
}
else if(PrimaryCCA->intf_type==2){
if(PrimaryCCA->CH_offset==1){
//ODM_SetBBReg(pDM_Odm, ODM_REG_L1SBD_PD_CH_11N, BIT8|BIT7, MF_USC);
pHalData->RTSEN = 1;
}
else if(PrimaryCCA->CH_offset==2){
//ODM_SetBBReg(pDM_Odm, ODM_REG_L1SBD_PD_CH_11N, BIT8|BIT7, MF_LSC);
pHalData->RTSEN = 1;
}
}
}
}
}
else{ // disconnected interference detection
odm_Intf_Detection(pDM_Odm);
}// end of disconnected
}
else{ // PrimaryCCA->PriCCA_flag == 1
if(STA_BW==0){
STA_BW_pre = STA_BW;
return;
}
Count_Down--;
if((Count_Down == 0) || ((STA_BW & STA_BW_pre) != 1)){
Count_Down = Monitor_TIME;
PrimaryCCA->PriCCA_flag = 0;
PrimaryCCA->intf_type = 0;
PrimaryCCA->intf_flag = 0;
CurMFstate = MF_USC_LSC;
odm_Write_Dynamic_CCA_8814A(pDM_Odm, CurMFstate); /* default*/
pHalData->RTSEN = 0;
}
}
STA_BW_pre = STA_BW;
}
else{
//2 Reset
odm_PrimaryCCA_Check_Init(pDM_Odm);
CurMFstate = MF_USC_LSC;
odm_Write_Dynamic_CCA_8814A(pDM_Odm, CurMFstate);
Count_Down = Monitor_TIME;
}
}
VOID
odm_Intf_Detection_8814A(
struct dm_struct *pDM_Odm
)
{
PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm, PHYDM_FALSEALMCNT);
struct phydm_pri_cca_struct* PrimaryCCA = &(pDM_Odm->dm_pri_cca);
if((FalseAlmCnt->Cnt_OFDM_CCA>OFDMCCA_TH)
&&(FalseAlmCnt->Cnt_BW_LSC>(FalseAlmCnt->Cnt_BW_USC+BW_Ind_Bias))){
PrimaryCCA->intf_flag = 1;
PrimaryCCA->CH_offset = 1; // 1:LSC, 2:USC
if(FalseAlmCnt->Cnt_Ofdm_fail>(FalseAlmCnt->Cnt_OFDM_CCA>>1)){
PrimaryCCA->intf_type = 1;
}
else{
PrimaryCCA->intf_type = 2;
}
}
else if((FalseAlmCnt->Cnt_OFDM_CCA>OFDMCCA_TH)
&&(FalseAlmCnt->Cnt_BW_USC>(FalseAlmCnt->Cnt_BW_LSC+BW_Ind_Bias))){
PrimaryCCA->intf_flag = 1;
PrimaryCCA->CH_offset = 2; // 1:LSC, 2:USC
if(FalseAlmCnt->Cnt_Ofdm_fail>(FalseAlmCnt->Cnt_OFDM_CCA>>1)){
PrimaryCCA->intf_type = 1;
}
else{
PrimaryCCA->intf_type = 2;
}
}
else{
PrimaryCCA->intf_flag = 0;
PrimaryCCA->intf_type = 0;
PrimaryCCA->CH_offset = 0;
}
}
#endif
#endif /* #ifdef PHYDM_PRIMARY_CCA */
u8
phydm_spur_nbi_setting_8814a(
struct dm_struct *pDM_Odm
)
{
u8 set_result = 0;
/*pDM_Odm->pChannel means central frequency, so we can use 20M as input*/
if (pDM_Odm->rfe_type == 0 || pDM_Odm->rfe_type == 1 || pDM_Odm->rfe_type == 6) {
/*channel asked by RF Jeff*/
if (*pDM_Odm->channel == 14)
set_result = phydm_nbi_setting(pDM_Odm, FUNC_ENABLE, *pDM_Odm->channel, 40, 2480, PHYDM_DONT_CARE);
else if (*pDM_Odm->channel >= 4 || *pDM_Odm->channel <= 8)
set_result = phydm_nbi_setting(pDM_Odm, FUNC_ENABLE, *pDM_Odm->channel, 40, 2440, PHYDM_DONT_CARE);
else
set_result = phydm_nbi_setting(pDM_Odm, FUNC_ENABLE, *pDM_Odm->channel, 40, 2440, PHYDM_DONT_CARE);
}
ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("%s, set_result = 0x%d, pChannel = %d\n", __func__, set_result, *pDM_Odm->channel));
//printk("%s, set_result = 0x%d, pChannel = %d\n", __func__, set_result, *pDM_Odm->channel);
pDM_Odm->nbi_set_result = set_result;
return set_result;
}
void odm_hw_setting_8814a(
struct dm_struct *p_dm_odm
)
{
#ifdef PHYDM_PRIMARY_CCA
odm_PrimaryCCA_Check_Init_8814A(p_dm_odm);
odm_DynamicPrimaryCCA_Check_8814A(p_dm_odm);
odm_Intf_Detection_8814A(p_dm_odm);
#endif
}
#endif // RTL8814A_SUPPORT == 1

78
hal/phydm/rtl8814a/phydm_rtl8814a.h 100644
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@ -0,0 +1,78 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODM_RTL8814A_H__
#define __ODM_RTL8814A_H__
#define OFDMCCA_TH 500
#define BW_Ind_Bias 500
#define MF_USC 2
#define MF_LSC 1
#define MF_USC_LSC 0
#define Monitor_TIME 30
s8 phydm_cck_rssi_8814a(struct dm_struct *dm, u16 lna_idx, u8 vga_idx);
VOID
odm_Write_Dynamic_CCA_8814A(
struct dm_struct *pDM_Odm,
u8 CurrentMFstate
);
VOID
odm_PrimaryCCA_Check_Init_8814A(
struct dm_struct *pDM_Odm
);
VOID
odm_DynamicPrimaryCCA_Check_8814A(
struct dm_struct *pDM_Odm
);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
VOID
odm_DynamicPrimaryCCAMP_8814A(
struct dm_struct *pDM_Odm
);
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
VOID
odm_DynamicPrimaryCCAAP_8814A(
struct dm_struct *pDM_Odm
);
VOID
odm_Intf_Detection_8814A(
struct dm_struct *pDM_Odm
);
#endif
u1Byte
phydm_spur_nbi_setting_8814a(
struct dm_struct *pDM_Odm
);
void odm_hw_setting_8814a(
struct dm_struct *p_dm_odm
);
#endif

10
hal/phydm/rtl8814a/version_rtl8814a.h 100644
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@ -0,0 +1,10 @@
/*RTL8814A PHY Parameters*/
/*
[Caution]
Since 01/Aug/2015, the commit rules will be simplified.
You do not need to fill up the version.h anymore,
only the maintenance supervisor fills it before formal release.
*/
#define RELEASE_DATE_8814A 20150908
#define COMMIT_BY_8814A "BB_LUKE"
#define RELEASE_VERSION_8814A 81

923
hal/phydm/rtl8821a/halhwimg8821a_bb.c 100644
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@ -0,0 +1,923 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
/*Image2HeaderVersion: 2.18*/
#include "mp_precomp.h"
#include "../phydm_precomp.h"
#if (RTL8821A_SUPPORT == 1)
static boolean
check_positive(
struct dm_struct *dm,
const u32 condition1,
const u32 condition2,
const u32 condition3,
const u32 condition4
)
{
u8 _board_type = ((dm->board_type & BIT(4)) >> 4) << 0 | /* _GLNA*/
((dm->board_type & BIT(3)) >> 3) << 1 | /* _GPA*/
((dm->board_type & BIT(7)) >> 7) << 2 | /* _ALNA*/
((dm->board_type & BIT(6)) >> 6) << 3 | /* _APA */
((dm->board_type & BIT(2)) >> 2) << 4; /* _BT*/
u32 cond1 = condition1, cond2 = condition2, cond3 = condition3, cond4 = condition4;
u32 driver1 = dm->cut_version << 24 |
(dm->support_interface & 0xF0) << 16 |
dm->support_platform << 16 |
dm->package_type << 12 |
(dm->support_interface & 0x0F) << 8 |
_board_type;
u32 driver2 = (dm->type_glna & 0xFF) << 0 |
(dm->type_gpa & 0xFF) << 8 |
(dm->type_alna & 0xFF) << 16 |
(dm->type_apa & 0xFF) << 24;
u32 driver3 = 0;
u32 driver4 = (dm->type_glna & 0xFF00) >> 8 |
(dm->type_gpa & 0xFF00) |
(dm->type_alna & 0xFF00) << 8 |
(dm->type_apa & 0xFF00) << 16;
PHYDM_DBG(dm, ODM_COMP_INIT,
"===> check_positive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4);
PHYDM_DBG(dm, ODM_COMP_INIT,
"===> check_positive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4);
PHYDM_DBG(dm, ODM_COMP_INIT,
" (Platform, Interface) = (0x%X, 0x%X)\n", dm->support_platform, dm->support_interface);
PHYDM_DBG(dm, ODM_COMP_INIT,
" (Board, Package) = (0x%X, 0x%X)\n", dm->board_type, dm->package_type);
/*============== value Defined Check ===============*/
/*QFN type [15:12] and cut version [27:24] need to do value check*/
if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000)))
return false;
if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000)))
return false;
/*=============== Bit Defined Check ================*/
/* We don't care [31:28] */
cond1 &= 0x00FF0FFF;
driver1 &= 0x00FF0FFF;
if ((cond1 & driver1) == cond1) {
u32 bit_mask = 0;
if ((cond1 & 0x0F) == 0) /* board_type is DONTCARE*/
return true;
if ((cond1 & BIT(0)) != 0) /*GLNA*/
bit_mask |= 0x000000FF;
if ((cond1 & BIT(1)) != 0) /*GPA*/
bit_mask |= 0x0000FF00;
if ((cond1 & BIT(2)) != 0) /*ALNA*/
bit_mask |= 0x00FF0000;
if ((cond1 & BIT(3)) != 0) /*APA*/
bit_mask |= 0xFF000000;
if (((cond2 & bit_mask) == (driver2 & bit_mask)) && ((cond4 & bit_mask) == (driver4 & bit_mask))) /* board_type of each RF path is matched*/
return true;
else
return false;
} else
return false;
}
static boolean
check_negative(
struct dm_struct *dm,
const u32 condition1,
const u32 condition2
)
{
return true;
}
/******************************************************************************
* AGC_TAB.TXT
******************************************************************************/
u32 array_mp_8821a_agc_tab[] = {
0x81C, 0xBF000001,
0x81C, 0xBF020001,
0x81C, 0xBF040001,
0x81C, 0xBF060001,
0x81C, 0xBE080001,
0x81C, 0xBD0A0001,
0x81C, 0xBC0C0001,
0x81C, 0xBA0E0001,
0x81C, 0xB9100001,
0x81C, 0xB8120001,
0x81C, 0xB7140001,
0x81C, 0xB6160001,
0x81C, 0xB5180001,
0x81C, 0xB41A0001,
0x81C, 0xB31C0001,
0x81C, 0xB21E0001,
0x81C, 0xB1200001,
0x81C, 0xB0220001,
0x81C, 0xAF240001,
0x81C, 0xAE260001,
0x81C, 0xAD280001,
0x81C, 0xAC2A0001,
0x81C, 0xAB2C0001,
0x81C, 0xAA2E0001,
0x81C, 0xA9300001,
0x81C, 0xA8320001,
0x81C, 0xA7340001,
0x81C, 0xA6360001,
0x81C, 0xA5380001,
0x81C, 0xA43A0001,
0x81C, 0x683C0001,
0x81C, 0x673E0001,
0x81C, 0x66400001,
0x81C, 0x65420001,
0x81C, 0x64440001,
0x81C, 0x63460001,
0x81C, 0x62480001,
0x81C, 0x614A0001,
0x81C, 0x474C0001,
0x81C, 0x464E0001,
0x81C, 0x45500001,
0x81C, 0x44520001,
0x81C, 0x43540001,
0x81C, 0x42560001,
0x81C, 0x41580001,
0x81C, 0x285A0001,
0x81C, 0x275C0001,
0x81C, 0x265E0001,
0x81C, 0x25600001,
0x81C, 0x24620001,
0x81C, 0x0A640001,
0x81C, 0x09660001,
0x81C, 0x08680001,
0x81C, 0x076A0001,
0x81C, 0x066C0001,
0x81C, 0x056E0001,
0x81C, 0x04700001,
0x81C, 0x03720001,
0x81C, 0x02740001,
0x81C, 0x01760001,
0x81C, 0x01780001,
0x81C, 0x017A0001,
0x81C, 0x017C0001,
0x81C, 0x017E0001,
0x8000020c, 0x00000000, 0x40000000, 0x00000000,
0x81C, 0xFB000101,
0x81C, 0xFA020101,
0x81C, 0xF9040101,
0x81C, 0xF8060101,
0x81C, 0xF7080101,
0x81C, 0xF60A0101,
0x81C, 0xF50C0101,
0x81C, 0xF40E0101,
0x81C, 0xF3100101,
0x81C, 0xF2120101,
0x81C, 0xF1140101,
0x81C, 0xF0160101,
0x81C, 0xEF180101,
0x81C, 0xEE1A0101,
0x81C, 0xED1C0101,
0x81C, 0xEC1E0101,
0x81C, 0xEB200101,
0x81C, 0xEA220101,
0x81C, 0xE9240101,
0x81C, 0xE8260101,
0x81C, 0xE7280101,
0x81C, 0xE62A0101,
0x81C, 0xE52C0101,
0x81C, 0xE42E0101,
0x81C, 0xE3300101,
0x81C, 0xA5320101,
0x81C, 0xA4340101,
0x81C, 0xA3360101,
0x81C, 0x87380101,
0x81C, 0x863A0101,
0x81C, 0x853C0101,
0x81C, 0x843E0101,
0x81C, 0x69400101,
0x81C, 0x68420101,
0x81C, 0x67440101,
0x81C, 0x66460101,
0x81C, 0x49480101,
0x81C, 0x484A0101,
0x81C, 0x474C0101,
0x81C, 0x2A4E0101,
0x81C, 0x29500101,
0x81C, 0x28520101,
0x81C, 0x27540101,
0x81C, 0x26560101,
0x81C, 0x25580101,
0x81C, 0x245A0101,
0x81C, 0x235C0101,
0x81C, 0x055E0101,
0x81C, 0x04600101,
0x81C, 0x03620101,
0x81C, 0x02640101,
0x81C, 0x01660101,
0x81C, 0x01680101,
0x81C, 0x016A0101,
0x81C, 0x016C0101,
0x81C, 0x016E0101,
0x81C, 0x01700101,
0x81C, 0x01720101,
0x9000040c, 0x00000000, 0x40000000, 0x00000000,
0x81C, 0xFB000101,
0x81C, 0xFA020101,
0x81C, 0xF9040101,
0x81C, 0xF8060101,
0x81C, 0xF7080101,
0x81C, 0xF60A0101,
0x81C, 0xF50C0101,
0x81C, 0xF40E0101,
0x81C, 0xF3100101,
0x81C, 0xF2120101,
0x81C, 0xF1140101,
0x81C, 0xF0160101,
0x81C, 0xEF180101,
0x81C, 0xEE1A0101,
0x81C, 0xED1C0101,
0x81C, 0xEC1E0101,
0x81C, 0xEB200101,
0x81C, 0xEA220101,
0x81C, 0xE9240101,
0x81C, 0xE8260101,
0x81C, 0xE7280101,
0x81C, 0xE62A0101,
0x81C, 0xE52C0101,
0x81C, 0xE42E0101,
0x81C, 0xE3300101,
0x81C, 0xA5320101,
0x81C, 0xA4340101,
0x81C, 0xA3360101,
0x81C, 0x87380101,
0x81C, 0x863A0101,
0x81C, 0x853C0101,
0x81C, 0x843E0101,
0x81C, 0x69400101,
0x81C, 0x68420101,
0x81C, 0x67440101,
0x81C, 0x66460101,
0x81C, 0x49480101,
0x81C, 0x484A0101,
0x81C, 0x474C0101,
0x81C, 0x2A4E0101,
0x81C, 0x29500101,
0x81C, 0x28520101,
0x81C, 0x27540101,
0x81C, 0x26560101,
0x81C, 0x25580101,
0x81C, 0x245A0101,
0x81C, 0x235C0101,
0x81C, 0x055E0101,
0x81C, 0x04600101,
0x81C, 0x03620101,
0x81C, 0x02640101,
0x81C, 0x01660101,
0x81C, 0x01680101,
0x81C, 0x016A0101,
0x81C, 0x016C0101,
0x81C, 0x016E0101,
0x81C, 0x01700101,
0x81C, 0x01720101,
0xA0000000, 0x00000000,
0x81C, 0xFF000101,
0x81C, 0xFF020101,
0x81C, 0xFE040101,
0x81C, 0xFD060101,
0x81C, 0xFC080101,
0x81C, 0xFD0A0101,
0x81C, 0xFC0C0101,
0x81C, 0xFB0E0101,
0x81C, 0xFA100101,
0x81C, 0xF9120101,
0x81C, 0xF8140101,
0x81C, 0xF7160101,
0x81C, 0xF6180101,
0x81C, 0xF51A0101,
0x81C, 0xF41C0101,
0x81C, 0xF31E0101,
0x81C, 0xF2200101,
0x81C, 0xF1220101,
0x81C, 0xF0240101,
0x81C, 0xEF260101,
0x81C, 0xEE280101,
0x81C, 0xED2A0101,
0x81C, 0xEC2C0101,
0x81C, 0xEB2E0101,
0x81C, 0xEA300101,
0x81C, 0xE9320101,
0x81C, 0xE8340101,
0x81C, 0xE7360101,
0x81C, 0xE6380101,
0x81C, 0xE53A0101,
0x81C, 0xE43C0101,
0x81C, 0xE33E0101,
0x81C, 0xA5400101,
0x81C, 0xA4420101,
0x81C, 0xA3440101,
0x81C, 0x87460101,
0x81C, 0x86480101,
0x81C, 0x854A0101,
0x81C, 0x844C0101,
0x81C, 0x694E0101,
0x81C, 0x68500101,
0x81C, 0x67520101,
0x81C, 0x66540101,
0x81C, 0x49560101,
0x81C, 0x48580101,
0x81C, 0x475A0101,
0x81C, 0x2A5C0101,
0x81C, 0x295E0101,
0x81C, 0x28600101,
0x81C, 0x27620101,
0x81C, 0x26640101,
0x81C, 0x25660101,
0x81C, 0x24680101,
0x81C, 0x236A0101,
0x81C, 0x056C0101,
0x81C, 0x046E0101,
0x81C, 0x03700101,
0x81C, 0x02720101,
0xB0000000, 0x00000000,
0x81C, 0x01740101,
0x81C, 0x01760101,
0x81C, 0x01780101,
0x81C, 0x017A0101,
0x81C, 0x017C0101,
0x81C, 0x017E0101,
0xC50, 0x00000022,
0xC50, 0x00000020,
};
void
odm_read_and_config_mp_8821a_agc_tab(
struct dm_struct *dm
)
{
u32 i = 0;
u8 c_cond;
boolean is_matched = true, is_skipped = false;
u32 array_len = sizeof(array_mp_8821a_agc_tab) / sizeof(u32);
u32 *array = array_mp_8821a_agc_tab;
u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_read_and_config_mp_8821a_agc_tab\n");
while ((i + 1) < array_len) {
v1 = array[i];
v2 = array[i + 1];
if (v1 & (BIT(31) | BIT30)) {/*positive & negative condition*/
if (v1 & BIT(31)) {/* positive condition*/
c_cond = (u8)((v1 & (BIT(29) | BIT(28))) >> 28);
if (c_cond == COND_ENDIF) {/*end*/
is_matched = true;
is_skipped = false;
PHYDM_DBG(dm, ODM_COMP_INIT, "ENDIF\n");
} else if (c_cond == COND_ELSE) { /*else*/
is_matched = is_skipped ? false : true;
PHYDM_DBG(dm, ODM_COMP_INIT, "ELSE\n");
} else {/*if , else if*/
pre_v1 = v1;
pre_v2 = v2;
PHYDM_DBG(dm, ODM_COMP_INIT, "IF or ELSE IF\n");
}
} else if (v1 & BIT(30)) { /*negative condition*/
if (is_skipped == false) {
if (check_positive(dm, pre_v1, pre_v2, v1, v2)) {
is_matched = true;
is_skipped = true;
} else {
is_matched = false;
is_skipped = false;
}
} else
is_matched = false;
}
} else {
if (is_matched)
odm_config_bb_agc_8821a(dm, v1, MASKDWORD, v2);
}
i = i + 2;
}
}
u32
odm_get_version_mp_8821a_agc_tab(void)
{
return 59;
}
/******************************************************************************
* PHY_REG.TXT
******************************************************************************/
u32 array_mp_8821a_phy_reg[] = {
0x800, 0x0020D090,
0x804, 0x080112E0,
0x808, 0x0E028211,
0x80C, 0x92131111,
0x810, 0x20101261,
0x814, 0x020C3D10,
0x818, 0x03A00385,
0x820, 0x00000000,
0x824, 0x00030FE0,
0x828, 0x00000000,
0x82C, 0x002081DD,
0x830, 0x2AAAEEC8,
0x834, 0x0037A706,
0x838, 0x06489B44,
0x83C, 0x0000095B,
0x840, 0xC0000001,
0x844, 0x40003CDE,
0x848, 0x62103F8B,
0x84C, 0x6CFDFFB8,
0x850, 0x28874706,
0x854, 0x0001520C,
0x858, 0x8060E000,
0x85C, 0x74210168,
0x860, 0x6929C321,
0x864, 0x79727432,
0x868, 0x8CA7A314,
0x86C, 0x888C2878,
0x870, 0x08888888,
0x874, 0x31612C2E,
0x878, 0x00000152,
0x87C, 0x000FD000,
0x8A0, 0x00000013,
0x8A4, 0x7F7F7F7F,
0x8A8, 0xA2000338,
0x8AC, 0x0FF0FA0A,
0x8B4, 0x000FC080,
0x8B8, 0x6C10D7FF,
0x8BC, 0x0CA52090,
0x8C0, 0x1BF00020,
0x8C4, 0x00000000,
0x8C8, 0x00013169,
0x8CC, 0x08248492,
0x8D4, 0x940008A0,
0x8D8, 0x290B5612,
0x8F8, 0x400002C0,
0x8FC, 0x00000000,
0x900, 0x00000700,
0x90C, 0x00000000,
0x910, 0x0000FC00,
0x914, 0x00000404,
0x918, 0x1C1028C0,
0x91C, 0x64B11A1C,
0x920, 0xE0767233,
0x924, 0x055AA500,
0x928, 0x00000004,
0x92C, 0xFFFE0000,
0x930, 0xFFFFFFFE,
0x934, 0x001FFFFF,
0x960, 0x00000000,
0x964, 0x00000000,
0x968, 0x00000000,
0x96C, 0x00000000,
0x970, 0x801FFFFF,
0x974, 0x000003FF,
0x978, 0x00000000,
0x97C, 0x00000000,
0x980, 0x00000000,
0x984, 0x00000000,
0x988, 0x00000000,
0x990, 0x27100000,
0x994, 0xFFFF0100,
0x998, 0xFFFFFF5C,
0x99C, 0xFFFFFFFF,
0x9A0, 0x000000FF,
0x9A4, 0x00480080,
0x9A8, 0x00000000,
0x9AC, 0x00000000,
0x9B0, 0x81081008,
0x9B4, 0x01081008,
0x9B8, 0x01081008,
0x9BC, 0x01081008,
0x9D0, 0x00000000,
0x9D4, 0x00000000,
0x9D8, 0x00000000,
0x9DC, 0x00000000,
0x9E0, 0x00005D00,
0x9E4, 0x00000003,
0x9E8, 0x00000001,
0xA00, 0x00D047C8,
0xA04, 0x01FF800C,
0xA08, 0x8C8A8300,
0xA0C, 0x2E68000F,
0xA10, 0x9500BB78,
0xA14, 0x11144028,
0xA18, 0x00881117,
0xA1C, 0x89140F00,
0xA20, 0x1A1B0000,
0xA24, 0x090E1317,
0xA28, 0x00000204,
0xA2C, 0x00900000,
0xA70, 0x101FFF00,
0xA74, 0x00000008,
0xA78, 0x00000900,
0xA7C, 0x225B0606,
0xA80, 0x21805490,
0xA84, 0x001F0000,
0xB00, 0x03100040,
0xB04, 0x0000B000,
0xB08, 0xAE0201EB,
0xB0C, 0x01003207,
0xB10, 0x00009807,
0xB14, 0x01000000,
0xB18, 0x00000002,
0xB1C, 0x00000002,
0xB20, 0x0000001F,
0xB24, 0x03020100,
0xB28, 0x07060504,
0xB2C, 0x0B0A0908,
0xB30, 0x0F0E0D0C,
0xB34, 0x13121110,
0xB38, 0x17161514,
0xB3C, 0x0000003A,
0xB40, 0x00000000,
0xB44, 0x00000000,
0xB48, 0x13000032,
0xB4C, 0x48080000,
0xB50, 0x00000000,
0xB54, 0x00000000,
0xB58, 0x00000000,
0xB5C, 0x00000000,
0xC00, 0x00000007,
0xC04, 0x00042020,
0xC08, 0x80410231,
0xC0C, 0x00000000,
0xC10, 0x00000100,
0xC14, 0x01000000,
0xC1C, 0x40000003,
0xC20, 0x2C2C2C2C,
0xC24, 0x30303030,
0xC28, 0x30303030,
0xC2C, 0x2C2C2C2C,
0xC30, 0x2C2C2C2C,
0xC34, 0x2C2C2C2C,
0xC38, 0x2C2C2C2C,
0xC3C, 0x2A2A2A2A,
0xC40, 0x2A2A2A2A,
0xC44, 0x2A2A2A2A,
0xC48, 0x2A2A2A2A,
0xC4C, 0x2A2A2A2A,
0xC50, 0x00000020,
0xC54, 0x001C1208,
0xC58, 0x30000C1C,
0xC5C, 0x00000058,
0xC60, 0x34344443,
0xC64, 0x07003333,
0xC68, 0x19791979,
0xC6C, 0x19791979,
0xC70, 0x19791979,
0xC74, 0x19791979,
0xC78, 0x19791979,
0xC7C, 0x19791979,
0xC80, 0x19791979,
0xC84, 0x19791979,
0xC94, 0x0100005C,
0xC98, 0x00000000,
0xC9C, 0x00000000,
0xCA0, 0x00000029,
0xCA4, 0x08040201,
0xCA8, 0x80402010,
0xCB0, 0x77775747,
0xCB4, 0x10000077,
0xCB8, 0x00508240,
};
void
odm_read_and_config_mp_8821a_phy_reg(
struct dm_struct *dm
)
{
u32 i = 0;
u8 c_cond;
boolean is_matched = true, is_skipped = false;
u32 array_len = sizeof(array_mp_8821a_phy_reg) / sizeof(u32);
u32 *array = array_mp_8821a_phy_reg;
u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_read_and_config_mp_8821a_phy_reg\n");
while ((i + 1) < array_len) {
v1 = array[i];
v2 = array[i + 1];
if (v1 & (BIT(31) | BIT30)) {/*positive & negative condition*/
if (v1 & BIT(31)) {/* positive condition*/
c_cond = (u8)((v1 & (BIT(29) | BIT(28))) >> 28);
if (c_cond == COND_ENDIF) {/*end*/
is_matched = true;
is_skipped = false;
PHYDM_DBG(dm, ODM_COMP_INIT, "ENDIF\n");
} else if (c_cond == COND_ELSE) { /*else*/
is_matched = is_skipped ? false : true;
PHYDM_DBG(dm, ODM_COMP_INIT, "ELSE\n");
} else {/*if , else if*/
pre_v1 = v1;
pre_v2 = v2;
PHYDM_DBG(dm, ODM_COMP_INIT, "IF or ELSE IF\n");
}
} else if (v1 & BIT(30)) { /*negative condition*/
if (is_skipped == false) {
if (check_positive(dm, pre_v1, pre_v2, v1, v2)) {
is_matched = true;
is_skipped = true;
} else {
is_matched = false;
is_skipped = false;
}
} else
is_matched = false;
}
} else {
if (is_matched)
odm_config_bb_phy_8821a(dm, v1, MASKDWORD, v2);
}
i = i + 2;
}
}
u32
odm_get_version_mp_8821a_phy_reg(void)
{
return 59;
}
/******************************************************************************
* PHY_REG_PG.TXT
******************************************************************************/
u32 array_mp_8821a_phy_reg_pg[] = {
0, 0, 0, 0x00000c20, 0xffffffff, 0x32343638,
0, 0, 0, 0x00000c24, 0xffffffff, 0x36363838,
0, 0, 0, 0x00000c28, 0xffffffff, 0x28303234,
0, 0, 0, 0x00000c2c, 0xffffffff, 0x34363838,
0, 0, 0, 0x00000c30, 0xffffffff, 0x26283032,
0, 0, 0, 0x00000c3c, 0xffffffff, 0x32343636,
0, 0, 0, 0x00000c40, 0xffffffff, 0x24262830,
0, 0, 0, 0x00000c44, 0x0000ffff, 0x00002022,
1, 0, 0, 0x00000c24, 0xffffffff, 0x34343636,
1, 0, 0, 0x00000c28, 0xffffffff, 0x26283032,
1, 0, 0, 0x00000c2c, 0xffffffff, 0x32343636,
1, 0, 0, 0x00000c30, 0xffffffff, 0x24262830,
1, 0, 0, 0x00000c3c, 0xffffffff, 0x32343636,
1, 0, 0, 0x00000c40, 0xffffffff, 0x24262830,
1, 0, 0, 0x00000c44, 0x0000ffff, 0x00002022
};
void
odm_read_and_config_mp_8821a_phy_reg_pg(
struct dm_struct *dm
)
{
u32 i = 0;
u32 array_len = sizeof(array_mp_8821a_phy_reg_pg) / sizeof(u32);
u32 *array = array_mp_8821a_phy_reg_pg;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void *adapter = dm->adapter;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
PlatformZeroMemory(hal_data->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT * MAX_BYTES_LINE_HWCONFIG_TXT);
hal_data->nLinesReadPwrByRate = array_len / 6;
#endif
PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_read_and_config_mp_8821a_phy_reg_pg\n");
dm->phy_reg_pg_version = 1;
dm->phy_reg_pg_value_type = PHY_REG_PG_EXACT_VALUE;
for (i = 0; i < array_len; i += 6) {
u32 v1 = array[i];
u32 v2 = array[i + 1];
u32 v3 = array[i + 2];
u32 v4 = array[i + 3];
u32 v5 = array[i + 4];
u32 v6 = array[i + 5];
odm_config_bb_phy_reg_pg_8821a(dm, v1, v2, v3, v4, v5, v6);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
rsprintf((char *)hal_data->BufOfLinesPwrByRate[i / 6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,",
(v1 == 0 ? "2.4G" : " 5G"), (v2 == 0 ? "A" : "B"), (v3 == 0 ? "1Tx" : "2Tx"), v4, v5, v6);
#endif
}
}
/******************************************************************************
* PHY_REG_PG_DNI_JP.TXT
******************************************************************************/
u32 array_mp_8821a_phy_reg_pg_dni_jp[] = {
0, 0, 0, 0x00000c20, 0xffffffff, 0x28282828,
0, 0, 0, 0x00000c24, 0xffffffff, 0x28282828,
0, 0, 0, 0x00000c28, 0xffffffff, 0x28282828,
0, 0, 0, 0x00000c2c, 0xffffffff, 0x28282828,
0, 0, 0, 0x00000c30, 0xffffffff, 0x28282828,
0, 0, 0, 0x00000c3c, 0xffffffff, 0x28282828,
0, 0, 0, 0x00000c40, 0xffffffff, 0x28282828,
0, 0, 0, 0x00000c44, 0x0000ffff, 0x00002424,
1, 0, 0, 0x00000c24, 0xffffffff, 0x23232323,
1, 0, 0, 0x00000c28, 0xffffffff, 0x23232323,
1, 0, 0, 0x00000c2c, 0xffffffff, 0x23232323,
1, 0, 0, 0x00000c30, 0xffffffff, 0x23232323,
1, 0, 0, 0x00000c3c, 0xffffffff, 0x23232323,
1, 0, 0, 0x00000c40, 0xffffffff, 0x23232323,
1, 0, 0, 0x00000c44, 0x0000ffff, 0x00002020
};
void
odm_read_and_config_mp_8821a_phy_reg_pg_dni_jp(
struct dm_struct *dm
)
{
u32 i = 0;
u32 array_len = sizeof(array_mp_8821a_phy_reg_pg_dni_jp) / sizeof(u32);
u32 *array = array_mp_8821a_phy_reg_pg_dni_jp;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void *adapter = dm->adapter;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
PlatformZeroMemory(hal_data->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT * MAX_BYTES_LINE_HWCONFIG_TXT);
hal_data->nLinesReadPwrByRate = array_len / 6;
#endif
PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_read_and_config_mp_8821a_phy_reg_pg_dni_jp\n");
dm->phy_reg_pg_version = 1;
dm->phy_reg_pg_value_type = PHY_REG_PG_EXACT_VALUE;
for (i = 0; i < array_len; i += 6) {
u32 v1 = array[i];
u32 v2 = array[i + 1];
u32 v3 = array[i + 2];
u32 v4 = array[i + 3];
u32 v5 = array[i + 4];
u32 v6 = array[i + 5];
odm_config_bb_phy_reg_pg_8821a(dm, v1, v2, v3, v4, v5, v6);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
rsprintf((char *)hal_data->BufOfLinesPwrByRate[i / 6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,",
(v1 == 0 ? "2.4G" : " 5G"), (v2 == 0 ? "A" : "B"), (v3 == 0 ? "1Tx" : "2Tx"), v4, v5, v6);
#endif
}
}
/******************************************************************************
* PHY_REG_PG_DNI_US.TXT
******************************************************************************/
u32 array_mp_8821a_phy_reg_pg_dni_us[] = {
0, 0, 0, 0x00000c20, 0xffffffff, 0x28282828,
0, 0, 0, 0x00000c24, 0xffffffff, 0x28282828,
0, 0, 0, 0x00000c28, 0xffffffff, 0x28282828,
0, 0, 0, 0x00000c2c, 0xffffffff, 0x28282828,
0, 0, 0, 0x00000c30, 0xffffffff, 0x28282828,
0, 0, 0, 0x00000c3c, 0xffffffff, 0x28282828,
0, 0, 0, 0x00000c40, 0xffffffff, 0x28282828,
0, 0, 0, 0x00000c44, 0x0000ffff, 0x00002424,
1, 0, 0, 0x00000c24, 0xffffffff, 0x26262626,
1, 0, 0, 0x00000c28, 0xffffffff, 0x26262626,
1, 0, 0, 0x00000c2c, 0xffffffff, 0x26262626,
1, 0, 0, 0x00000c30, 0xffffffff, 0x26262626,
1, 0, 0, 0x00000c3c, 0xffffffff, 0x26262626,
1, 0, 0, 0x00000c40, 0xffffffff, 0x26262626,
1, 0, 0, 0x00000c44, 0x0000ffff, 0x00002020
};
void
odm_read_and_config_mp_8821a_phy_reg_pg_dni_us(
struct dm_struct *dm
)
{
u32 i = 0;
u32 array_len = sizeof(array_mp_8821a_phy_reg_pg_dni_us) / sizeof(u32);
u32 *array = array_mp_8821a_phy_reg_pg_dni_us;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void *adapter = dm->adapter;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
PlatformZeroMemory(hal_data->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT * MAX_BYTES_LINE_HWCONFIG_TXT);
hal_data->nLinesReadPwrByRate = array_len / 6;
#endif
PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_read_and_config_mp_8821a_phy_reg_pg_dni_us\n");
dm->phy_reg_pg_version = 1;
dm->phy_reg_pg_value_type = PHY_REG_PG_EXACT_VALUE;
for (i = 0; i < array_len; i += 6) {
u32 v1 = array[i];
u32 v2 = array[i + 1];
u32 v3 = array[i + 2];
u32 v4 = array[i + 3];
u32 v5 = array[i + 4];
u32 v6 = array[i + 5];
odm_config_bb_phy_reg_pg_8821a(dm, v1, v2, v3, v4, v5, v6);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
rsprintf((char *)hal_data->BufOfLinesPwrByRate[i / 6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,",
(v1 == 0 ? "2.4G" : " 5G"), (v2 == 0 ? "A" : "B"), (v3 == 0 ? "1Tx" : "2Tx"), v4, v5, v6);
#endif
}
}
/******************************************************************************
* PHY_REG_PG_E202SA.TXT
******************************************************************************/
u32 array_mp_8821a_phy_reg_pg_e202sa[] = {
0, 0, 0, 0x00000c20, 0xffffffff, 0x32323232,
0, 0, 0, 0x00000c24, 0xffffffff, 0x28282828,
0, 0, 0, 0x00000c28, 0xffffffff, 0x28282828,
0, 0, 0, 0x00000c2c, 0xffffffff, 0x22222222,
0, 0, 0, 0x00000c30, 0xffffffff, 0x22222222,
0, 0, 0, 0x00000c3c, 0xffffffff, 0x32343636,
0, 0, 0, 0x00000c40, 0xffffffff, 0x24262830,
0, 0, 0, 0x00000c44, 0x0000ffff, 0x00002022,
1, 0, 0, 0x00000c24, 0xffffffff, 0x26262626,
1, 0, 0, 0x00000c28, 0xffffffff, 0x26262626,
1, 0, 0, 0x00000c2c, 0xffffffff, 0x20202020,
1, 0, 0, 0x00000c30, 0xffffffff, 0x20202020,
1, 0, 0, 0x00000c3c, 0xffffffff, 0x16161616,
1, 0, 0, 0x00000c40, 0xffffffff, 0x16161616,
1, 0, 0, 0x00000c44, 0x0000ffff, 0x00001616
};
void
odm_read_and_config_mp_8821a_phy_reg_pg_e202_sa(
struct dm_struct *dm
)
{
u32 i = 0;
u32 array_len = sizeof(array_mp_8821a_phy_reg_pg_e202sa) / sizeof(u32);
u32 *array = array_mp_8821a_phy_reg_pg_e202sa;
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
void *adapter = dm->adapter;
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
PlatformZeroMemory(hal_data->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT * MAX_BYTES_LINE_HWCONFIG_TXT);
hal_data->nLinesReadPwrByRate = array_len / 6;
#endif
PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_read_and_config_mp_8821a_phy_reg_pg_e202_sa\n");
dm->phy_reg_pg_version = 1;
dm->phy_reg_pg_value_type = PHY_REG_PG_EXACT_VALUE;
for (i = 0; i < array_len; i += 6) {
u32 v1 = array[i];
u32 v2 = array[i + 1];
u32 v3 = array[i + 2];
u32 v4 = array[i + 3];
u32 v5 = array[i + 4];
u32 v6 = array[i + 5];
odm_config_bb_phy_reg_pg_8821a(dm, v1, v2, v3, v4, v5, v6);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
rsprintf((char *)hal_data->BufOfLinesPwrByRate[i / 6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,",
(v1 == 0 ? "2.4G" : " 5G"), (v2 == 0 ? "A" : "B"), (v3 == 0 ? "1Tx" : "2Tx"), v4, v5, v6);
#endif
}
}
#endif /* end of HWIMG_SUPPORT*/

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hal/phydm/rtl8821a/halhwimg8821a_bb.h 100644
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
/*Image2HeaderVersion: 2.18*/
#if (RTL8821A_SUPPORT == 1)
#ifndef __INC_MP_BB_HW_IMG_8821A_H
#define __INC_MP_BB_HW_IMG_8821A_H
/******************************************************************************
* AGC_TAB.TXT
******************************************************************************/
void
odm_read_and_config_mp_8821a_agc_tab(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8821a_agc_tab(void);
/******************************************************************************
* PHY_REG.TXT
******************************************************************************/
void
odm_read_and_config_mp_8821a_phy_reg(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8821a_phy_reg(void);
/******************************************************************************
* PHY_REG_PG.TXT
******************************************************************************/
void
odm_read_and_config_mp_8821a_phy_reg_pg(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8821a_phy_reg_pg(void);
/******************************************************************************
* PHY_REG_PG_DNI_JP.TXT
******************************************************************************/
void
odm_read_and_config_mp_8821a_phy_reg_pg_dni_jp(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8821a_phy_reg_pg_dni_jp(void);
/******************************************************************************
* PHY_REG_PG_DNI_US.TXT
******************************************************************************/
void
odm_read_and_config_mp_8821a_phy_reg_pg_dni_us(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8821a_phy_reg_pg_dni_us(void);
/******************************************************************************
* PHY_REG_PG_E202SA.TXT
******************************************************************************/
void
odm_read_and_config_mp_8821a_phy_reg_pg_e202_sa(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8821a_phy_reg_pg_e202sa(void);
#endif
#endif /* end of HWIMG_SUPPORT*/

279
hal/phydm/rtl8821a/halhwimg8821a_mac.c 100644
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
/*Image2HeaderVersion: 2.18*/
#include "mp_precomp.h"
#include "../phydm_precomp.h"
#if (RTL8821A_SUPPORT == 1)
static boolean
check_positive(
struct dm_struct *dm,
const u32 condition1,
const u32 condition2,
const u32 condition3,
const u32 condition4
)
{
u8 _board_type = ((dm->board_type & BIT(4)) >> 4) << 0 | /* _GLNA*/
((dm->board_type & BIT(3)) >> 3) << 1 | /* _GPA*/
((dm->board_type & BIT(7)) >> 7) << 2 | /* _ALNA*/
((dm->board_type & BIT(6)) >> 6) << 3 | /* _APA */
((dm->board_type & BIT(2)) >> 2) << 4; /* _BT*/
u32 cond1 = condition1, cond2 = condition2, cond3 = condition3, cond4 = condition4;
u32 driver1 = dm->cut_version << 24 |
(dm->support_interface & 0xF0) << 16 |
dm->support_platform << 16 |
dm->package_type << 12 |
(dm->support_interface & 0x0F) << 8 |
_board_type;
u32 driver2 = (dm->type_glna & 0xFF) << 0 |
(dm->type_gpa & 0xFF) << 8 |
(dm->type_alna & 0xFF) << 16 |
(dm->type_apa & 0xFF) << 24;
u32 driver3 = 0;
u32 driver4 = (dm->type_glna & 0xFF00) >> 8 |
(dm->type_gpa & 0xFF00) |
(dm->type_alna & 0xFF00) << 8 |
(dm->type_apa & 0xFF00) << 16;
PHYDM_DBG(dm, ODM_COMP_INIT,
"===> check_positive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4);
PHYDM_DBG(dm, ODM_COMP_INIT,
"===> check_positive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4);
PHYDM_DBG(dm, ODM_COMP_INIT,
" (Platform, Interface) = (0x%X, 0x%X)\n", dm->support_platform, dm->support_interface);
PHYDM_DBG(dm, ODM_COMP_INIT,
" (Board, Package) = (0x%X, 0x%X)\n", dm->board_type, dm->package_type);
/*============== value Defined Check ===============*/
/*QFN type [15:12] and cut version [27:24] need to do value check*/
if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000)))
return false;
if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000)))
return false;
/*=============== Bit Defined Check ================*/
/* We don't care [31:28] */
cond1 &= 0x00FF0FFF;
driver1 &= 0x00FF0FFF;
if ((cond1 & driver1) == cond1) {
u32 bit_mask = 0;
if ((cond1 & 0x0F) == 0) /* board_type is DONTCARE*/
return true;
if ((cond1 & BIT(0)) != 0) /*GLNA*/
bit_mask |= 0x000000FF;
if ((cond1 & BIT(1)) != 0) /*GPA*/
bit_mask |= 0x0000FF00;
if ((cond1 & BIT(2)) != 0) /*ALNA*/
bit_mask |= 0x00FF0000;
if ((cond1 & BIT(3)) != 0) /*APA*/
bit_mask |= 0xFF000000;
if (((cond2 & bit_mask) == (driver2 & bit_mask)) && ((cond4 & bit_mask) == (driver4 & bit_mask))) /* board_type of each RF path is matched*/
return true;
else
return false;
} else
return false;
}
static boolean
check_negative(
struct dm_struct *dm,
const u32 condition1,
const u32 condition2
)
{
return true;
}
/******************************************************************************
* MAC_REG.TXT
******************************************************************************/
u32 array_mp_8821a_mac_reg[] = {
0x421, 0x0000000F,
0x428, 0x0000000A,
0x429, 0x00000010,
0x430, 0x00000000,
0x431, 0x00000000,
0x432, 0x00000000,
0x433, 0x00000001,
0x434, 0x00000004,
0x435, 0x00000005,
0x436, 0x00000007,
0x437, 0x00000008,
0x43C, 0x00000004,
0x43D, 0x00000005,
0x43E, 0x00000007,
0x43F, 0x00000008,
0x440, 0x0000005D,
0x441, 0x00000001,
0x442, 0x00000000,
0x444, 0x00000010,
0x445, 0x00000000,
0x446, 0x00000000,
0x447, 0x00000000,
0x448, 0x00000000,
0x449, 0x000000F0,
0x44A, 0x0000000F,
0x44B, 0x0000003E,
0x44C, 0x00000010,
0x44D, 0x00000000,
0x44E, 0x00000000,
0x44F, 0x00000000,
0x450, 0x00000000,
0x451, 0x000000F0,
0x452, 0x0000000F,
0x453, 0x00000000,
0x456, 0x0000005E,
0x460, 0x00000066,
0x461, 0x00000066,
0x4C8, 0x0000003F,
0x4C9, 0x000000FF,
0x4CC, 0x000000FF,
0x4CD, 0x000000FF,
0x4CE, 0x00000001,
0x500, 0x00000026,
0x501, 0x000000A2,
0x502, 0x0000002F,
0x503, 0x00000000,
0x504, 0x00000028,
0x505, 0x000000A3,
0x506, 0x0000005E,
0x507, 0x00000000,
0x508, 0x0000002B,
0x509, 0x000000A4,
0x50A, 0x0000005E,
0x50B, 0x00000000,
0x50C, 0x0000004F,
0x50D, 0x000000A4,
0x50E, 0x00000000,
0x50F, 0x00000000,
0x512, 0x0000001C,
0x514, 0x0000000A,
0x516, 0x0000000A,
0x525, 0x0000004F,
0x550, 0x00000010,
0x551, 0x00000010,
0x559, 0x00000002,
0x55C, 0x00000050,
0x55D, 0x000000FF,
0x605, 0x00000030,
0x607, 0x00000007,
0x608, 0x0000000E,
0x609, 0x0000002A,
0x620, 0x000000FF,
0x621, 0x000000FF,
0x622, 0x000000FF,
0x623, 0x000000FF,
0x624, 0x000000FF,
0x625, 0x000000FF,
0x626, 0x000000FF,
0x627, 0x000000FF,
0x638, 0x00000050,
0x63C, 0x0000000A,
0x63D, 0x0000000A,
0x63E, 0x0000000E,
0x63F, 0x0000000E,
0x640, 0x00000040,
0x642, 0x00000040,
0x643, 0x00000000,
0x652, 0x000000C8,
0x66E, 0x00000005,
0x700, 0x00000021,
0x701, 0x00000043,
0x702, 0x00000065,
0x703, 0x00000087,
0x708, 0x00000021,
0x709, 0x00000043,
0x70A, 0x00000065,
0x70B, 0x00000087,
0x718, 0x00000040,
};
void
odm_read_and_config_mp_8821a_mac_reg(
struct dm_struct *dm
)
{
u32 i = 0;
u8 c_cond;
boolean is_matched = true, is_skipped = false;
u32 array_len = sizeof(array_mp_8821a_mac_reg) / sizeof(u32);
u32 *array = array_mp_8821a_mac_reg;
u32 v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0;
PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_read_and_config_mp_8821a_mac_reg\n");
while ((i + 1) < array_len) {
v1 = array[i];
v2 = array[i + 1];
if (v1 & (BIT(31) | BIT30)) {/*positive & negative condition*/
if (v1 & BIT(31)) {/* positive condition*/
c_cond = (u8)((v1 & (BIT(29) | BIT(28))) >> 28);
if (c_cond == COND_ENDIF) {/*end*/
is_matched = true;
is_skipped = false;
PHYDM_DBG(dm, ODM_COMP_INIT, "ENDIF\n");
} else if (c_cond == COND_ELSE) { /*else*/
is_matched = is_skipped ? false : true;
PHYDM_DBG(dm, ODM_COMP_INIT, "ELSE\n");
} else {/*if , else if*/
pre_v1 = v1;
pre_v2 = v2;
PHYDM_DBG(dm, ODM_COMP_INIT, "IF or ELSE IF\n");
}
} else if (v1 & BIT(30)) { /*negative condition*/
if (is_skipped == false) {
if (check_positive(dm, pre_v1, pre_v2, v1, v2)) {
is_matched = true;
is_skipped = true;
} else {
is_matched = false;
is_skipped = false;
}
} else
is_matched = false;
}
} else {
if (is_matched)
odm_config_mac_8821a(dm, v1, (u8)v2);
}
i = i + 2;
}
}
u32
odm_get_version_mp_8821a_mac_reg(void)
{
return 59;
}
#endif /* end of HWIMG_SUPPORT*/

33
hal/phydm/rtl8821a/halhwimg8821a_mac.h 100644
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
/*Image2HeaderVersion: 2.18*/
#if (RTL8821A_SUPPORT == 1)
#ifndef __INC_MP_MAC_HW_IMG_8821A_H
#define __INC_MP_MAC_HW_IMG_8821A_H
/******************************************************************************
* MAC_REG.TXT
******************************************************************************/
void
odm_read_and_config_mp_8821a_mac_reg(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8821a_mac_reg(void);
#endif
#endif /* end of HWIMG_SUPPORT*/

5457
hal/phydm/rtl8821a/halhwimg8821a_rf.c 100644
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File diff suppressed because it is too large Load Diff

143
hal/phydm/rtl8821a/halhwimg8821a_rf.h 100644
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
/*Image2HeaderVersion: 2.18*/
#if (RTL8821A_SUPPORT == 1)
#ifndef __INC_MP_RF_HW_IMG_8821A_H
#define __INC_MP_RF_HW_IMG_8821A_H
/******************************************************************************
* RadioA.TXT
******************************************************************************/
void
odm_read_and_config_mp_8821a_radioa(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8821a_radioa(void);
/******************************************************************************
* TxPowerTrack_AP.TXT
******************************************************************************/
void
odm_read_and_config_mp_8821a_txpowertrack_ap(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8821a_txpowertrack_ap(void);
/******************************************************************************
* TxPowerTrack_PCIE.TXT
******************************************************************************/
void
odm_read_and_config_mp_8821a_txpowertrack_pcie(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8821a_txpowertrack_pcie(void);
/******************************************************************************
* TxPowerTrack_SDIO.TXT
******************************************************************************/
void
odm_read_and_config_mp_8821a_txpowertrack_sdio(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8821a_txpowertrack_sdio(void);
/******************************************************************************
* TxPowerTrack_USB.TXT
******************************************************************************/
void
odm_read_and_config_mp_8821a_txpowertrack_usb(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8821a_txpowertrack_usb(void);
/******************************************************************************
* TXPWR_LMT_8811AU_FEM.TXT
******************************************************************************/
void
odm_read_and_config_mp_8821a_txpwr_lmt_8811a_u_fem(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8821a_txpwr_lmt_8811a_u_fem(void);
/******************************************************************************
* TXPWR_LMT_8811AU_IPA.TXT
******************************************************************************/
void
odm_read_and_config_mp_8821a_txpwr_lmt_8811a_u_ipa(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8821a_txpwr_lmt_8811a_u_ipa(void);
/******************************************************************************
* TXPWR_LMT_8821A.TXT
******************************************************************************/
void
odm_read_and_config_mp_8821a_txpwr_lmt_8821a(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8821a_txpwr_lmt_8821a(void);
/******************************************************************************
* TXPWR_LMT_8821A_E202SA.TXT
******************************************************************************/
void
odm_read_and_config_mp_8821a_txpwr_lmt_8821a_e202sa(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8821a_txpwr_lmt_8821a_e202sa(void);
/******************************************************************************
* TXPWR_LMT_8821A_SAR_13dBm.TXT
******************************************************************************/
void
odm_read_and_config_mp_8821a_txpwr_lmt_8821a_sar_13_dbm(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8821a_txpwr_lmt_8821a_sar_13_dbm(void);
/******************************************************************************
* TXPWR_LMT_8821A_SAR_5mm.TXT
******************************************************************************/
void
odm_read_and_config_mp_8821a_txpwr_lmt_8821a_sar_5mm(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8821a_txpwr_lmt_8821a_sar_5mm(void);
/******************************************************************************
* TXPWR_LMT_8821A_SAR_8mm.TXT
******************************************************************************/
void
odm_read_and_config_mp_8821a_txpwr_lmt_8821a_sar_8mm(/* TC: Test Chip, MP: MP Chip*/
struct dm_struct *dm
);
u32 odm_get_version_mp_8821a_txpwr_lmt_8821a_sar_8mm(void);
#endif
#endif /* end of HWIMG_SUPPORT*/

206
hal/phydm/rtl8821a/phydm_regconfig8821a.c 100644
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/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#include "mp_precomp.h"
#include "../phydm_precomp.h"
#if (RTL8821A_SUPPORT == 1)
void
odm_config_rf_reg_8821a(
struct dm_struct *dm,
u32 addr,
u32 data,
enum rf_path RF_PATH,
u32 reg_addr
)
{
if (addr == 0xfe || addr == 0xffe) {
#ifdef CONFIG_LONG_DELAY_ISSUE
ODM_sleep_ms(50);
#else
ODM_delay_ms(50);
#endif
} else if (addr == 0xfd)
ODM_delay_ms(5);
else if (addr == 0xfc)
ODM_delay_ms(1);
else if (addr == 0xfb)
ODM_delay_us(50);
else if (addr == 0xfa)
ODM_delay_us(5);
else if (addr == 0xf9)
ODM_delay_us(1);
else {
odm_set_rf_reg(dm, RF_PATH, reg_addr, RFREGOFFSETMASK, data);
/* Add 1us delay between BB/RF register setting. */
ODM_delay_us(1);
}
}
void
odm_config_rf_radio_a_8821a(
struct dm_struct *dm,
u32 addr,
u32 data
)
{
u32 content = 0x1000; /* RF_Content: radioa_txt */
u32 maskfor_phy_set = (u32)(content & 0xE000);
odm_config_rf_reg_8821a(dm, addr, data, RF_PATH_A, addr | maskfor_phy_set);
PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_config_rf_with_header_file: [RadioA] %08X %08X\n", addr, data);
}
/* 8821 no RF B */
#if 0
void
odm_config_rf_radio_b_8821a(
struct dm_struct *dm,
u32 addr,
u32 data
)
{
u32 content = 0x1001; /* RF_Content: radiob_txt */
u32 maskfor_phy_set = (u32)(content & 0xE000);
odm_config_rf_reg_8812a(dm, addr, data, RF_PATH_B, addr | maskfor_phy_set);
PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_config_rf_with_header_file: [RadioB] %08X %08X\n", addr, data);
}
#endif
void
odm_config_mac_8821a(
struct dm_struct *dm,
u32 addr,
u8 data
)
{
odm_write_1byte(dm, addr, data);
PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_config_mac_with_header_file: [MAC_REG] %08X %08X\n", addr, data);
}
void
odm_config_bb_agc_8821a(
struct dm_struct *dm,
u32 addr,
u32 bitmask,
u32 data
)
{
odm_set_bb_reg(dm, addr, bitmask, data);
/* Add 1us delay between BB/RF register setting. */
ODM_delay_us(1);
PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_config_bb_with_header_file: [AGC_TAB] %08X %08X\n", addr, data);
}
void
odm_config_bb_phy_reg_pg_8821a(
struct dm_struct *dm,
u32 band,
u32 rf_path,
u32 tx_num,
u32 addr,
u32 bitmask,
u32 data
)
{
if (addr == 0xfe)
#ifdef CONFIG_LONG_DELAY_ISSUE
ODM_sleep_ms(50);
#else
ODM_delay_ms(50);
#endif
else if (addr == 0xfd)
ODM_delay_ms(5);
else if (addr == 0xfc)
ODM_delay_ms(1);
else if (addr == 0xfb)
ODM_delay_us(50);
else if (addr == 0xfa)
ODM_delay_us(5);
else if (addr == 0xf9)
ODM_delay_us(1);
PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_config_bb_with_header_file: [PHY_REG] %08X %08X %08X\n", addr, bitmask, data);
#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
phy_store_tx_power_by_rate(dm->adapter, band, rf_path, tx_num, addr, bitmask, data);
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
PHY_StoreTxPowerByRate((PADAPTER)dm->adapter, band, rf_path, tx_num, addr, bitmask, data);
#endif
}
void
odm_config_bb_phy_8821a(
struct dm_struct *dm,
u32 addr,
u32 bitmask,
u32 data
)
{
if (addr == 0xfe)
#ifdef CONFIG_LONG_DELAY_ISSUE
ODM_sleep_ms(50);
#else
ODM_delay_ms(50);
#endif
else if (addr == 0xfd)
ODM_delay_ms(5);
else if (addr == 0xfc)
ODM_delay_ms(1);
else if (addr == 0xfb)
ODM_delay_us(50);
else if (addr == 0xfa)
ODM_delay_us(5);
else if (addr == 0xf9)
ODM_delay_us(1);
else if (addr == 0xa24)
dm->rf_calibrate_info.rega24 = data;
odm_set_bb_reg(dm, addr, bitmask, data);
/* Add 1us delay between BB/RF register setting. */
ODM_delay_us(1);
PHYDM_DBG(dm, ODM_COMP_INIT, "===> odm_config_bb_with_header_file: [PHY_REG] %08X %08X\n", addr, data);
}
void
odm_config_bb_txpwr_lmt_8821a(
struct dm_struct *dm,
u8 *regulation,
u8 *band,
u8 *bandwidth,
u8 *rate_section,
u8 *rf_path,
u8 *channel,
u8 *power_limit
)
{
#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
phy_set_tx_power_limit(dm, regulation, band,
bandwidth, rate_section, rf_path, channel, power_limit);
#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
PHY_SetTxPowerLimit(dm, regulation, band,
bandwidth, rate_section, rf_path, channel, power_limit);
#endif
}
#endif /* #if (RTL8821A_SUPPORT == 1)*/

90
hal/phydm/rtl8821a/phydm_regconfig8821a.h 100644
View File

@ -0,0 +1,90 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __INC_ODM_REGCONFIG_H_8821A
#define __INC_ODM_REGCONFIG_H_8821A
#if (RTL8821A_SUPPORT == 1)
void
odm_config_rf_reg_8821a(
struct dm_struct *dm,
u32 addr,
u32 data,
enum rf_path RF_PATH,
u32 reg_addr
);
void
odm_config_rf_radio_a_8821a(
struct dm_struct *dm,
u32 addr,
u32 data
);
void
odm_config_rf_radio_b_8821a(
struct dm_struct *dm,
u32 addr,
u32 data
);
void
odm_config_mac_8821a(
struct dm_struct *dm,
u32 addr,
u8 data
);
void
odm_config_bb_agc_8821a(
struct dm_struct *dm,
u32 addr,
u32 bitmask,
u32 data
);
void
odm_config_bb_phy_reg_pg_8821a(
struct dm_struct *dm,
u32 band,
u32 rf_path,
u32 tx_num,
u32 addr,
u32 bitmask,
u32 data
);
void
odm_config_bb_phy_8821a(
struct dm_struct *dm,
u32 addr,
u32 bitmask,
u32 data
);
void
odm_config_bb_txpwr_lmt_8821a(
struct dm_struct *dm,
u8 *regulation,
u8 *band,
u8 *bandwidth,
u8 *rate_section,
u8 *rf_path,
u8 *channel,
u8 *power_limit
);
#endif
#endif /* end of SUPPORT */

129
hal/phydm/rtl8821a/phydm_rtl8821a.c 100644
View File

@ -0,0 +1,129 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
/* ************************************************************
* include files
* ************************************************************ */
#include "mp_precomp.h"
#include "../phydm_precomp.h"
#if (RTL8821A_SUPPORT == 1)
s8 phydm_cck_rssi_8821a(struct dm_struct *dm, u16 lna_idx, u8 vga_idx)
{
s8 rx_pwr_all = 0;
switch (lna_idx) {
case 7:
if (vga_idx <= 27)
rx_pwr_all = -94 + 2 * (27 - vga_idx);
else
rx_pwr_all = -94;
break;
case 6:
rx_pwr_all = -42 + 2 * (2 - vga_idx);
break;
case 5:
rx_pwr_all = -36 + 2 * (7 - vga_idx);
break;
case 4:
rx_pwr_all = -30 + 2 * (7 - vga_idx);
break;
case 3:
rx_pwr_all = -18 + 2 * (7 - vga_idx);
break;
case 2:
rx_pwr_all = 2 * (5 - vga_idx);
break;
case 1:
rx_pwr_all = 14 - 2 * vga_idx;
break;
case 0:
rx_pwr_all = 20 - 2 * vga_idx;
break;
default:
break;
}
return rx_pwr_all;
}
void
phydm_set_ext_band_switch_8821A(
void *dm_void,
u32 band
)
{
struct dm_struct *dm = (struct dm_struct *)dm_void;
/*Output Pin Settings*/
odm_set_mac_reg(dm, 0x4C, BIT(23), 0); /*select DPDT_P and DPDT_N as output pin*/
odm_set_mac_reg(dm, 0x4C, BIT(24), 1); /*by WLAN control*/
odm_set_bb_reg(dm, 0xCB4, 0xF, 7); /*DPDT_P = 1b'0*/
odm_set_bb_reg(dm, 0xCB4, 0xF0, 7); /*DPDT_N = 1b'0*/
if (band == ODM_BAND_2_4G) {
odm_set_bb_reg(dm, 0xCB4, (BIT(29) | BIT(28)), 1);
PHYDM_DBG(dm, DBG_ANT_DIV, "***8821A set band switch = 2b'01\n");
} else {
odm_set_bb_reg(dm, 0xCB4, BIT(29) | BIT(28), 2);
PHYDM_DBG(dm, DBG_ANT_DIV, "***8821A set band switch = 2b'10\n");
}
}
void
odm_dynamic_try_state_agg_8821a(
struct dm_struct *dm
)
{
if ((dm->support_ic_type & ODM_RTL8821) && (dm->support_interface == ODM_ITRF_USB)) {
if (dm->rssi_min > 25)
odm_write_1byte(dm, 0x4CF, 0x02);
else if (dm->rssi_min < 20)
odm_write_1byte(dm, 0x4CF, 0x00);
}
}
void
odm_dynamic_packet_detection_th_8821a(
struct dm_struct *dm
)
{
if (dm->support_ic_type & ODM_RTL8821) {
if (dm->rssi_min <= 25) {
/*odm_set_bb_reg(dm, REG_PWED_TH_JAGUAR, MASKDWORD, 0x2aaaf1a8);*/
odm_set_bb_reg(dm, REG_PWED_TH_JAGUAR, 0x1ff0, 0x11a);
odm_set_bb_reg(dm, REG_BW_INDICATION_JAGUAR, BIT(26), 1);
} else if (dm->rssi_min >= 30) {
/*odm_set_bb_reg(dm, REG_PWED_TH_JAGUAR, MASKDWORD, 0x2aaaeec8);*/
odm_set_bb_reg(dm, REG_PWED_TH_JAGUAR, 0x1ff0, 0xec);
odm_set_bb_reg(dm, REG_BW_INDICATION_JAGUAR, BIT(26), 0);
}
}
}
void
odm_hw_setting_8821a(
struct dm_struct *dm
)
{
odm_dynamic_try_state_agg_8821a(dm);
odm_dynamic_packet_detection_th_8821a(dm);
}
#endif /* #if (RTL8821A_SUPPORT == 1) */

31
hal/phydm/rtl8821a/phydm_rtl8821a.h 100644
View File

@ -0,0 +1,31 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#ifndef __ODM_RTL8821A_H__
#define __ODM_RTL8821A_H__
s8 phydm_cck_rssi_8821a(struct dm_struct *dm, u16 lna_idx, u8 vga_idx);
void
phydm_set_ext_band_switch_8821A(
void *dm_void,
u32 band
);
void
odm_hw_setting_8821a(
struct dm_struct *dm
);
#endif

24
hal/phydm/rtl8821a/version_rtl8821a.h 100644
View File

@ -0,0 +1,24 @@
/******************************************************************************
*
* Copyright(c) 2016 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
/*RTL8821A PHY Parameters*/
/*
[Caution]
Since 01/Aug/2015, the commit rules will be simplified.
You do not need to fill up the version.h anymore,
only the maintenance supervisor fills it before formal release.
*/
#define RELEASE_DATE_8821A 20150920
#define COMMIT_BY_8821A "BB_LUKE"
#define RELEASE_VERSION_8821A 59

2
hal/rtl8812a/rtl8812a_phycfg.c
View File

@ -473,6 +473,8 @@ PHY_GetTxPowerLevel8812(
OUT s32 *powerlevel
)
{
/*HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
*powerlevel = pHalData->CurrentTxPwrIdx;*/
#if 0
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);

2
hal/rtl8812a/usb/usb_halinit.c
View File

@ -1055,7 +1055,7 @@ usb_AggSettingRxUpdate_8812A(
/* Adjust DMA page and thresh. */
temp = pHalData->rxagg_dma_size | (pHalData->rxagg_dma_timeout << 8);
rtw_write16(Adapter, REG_RXDMA_AGG_PG_TH, temp);
rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH + 3, BIT(7)); /* for dma agg , 0x280[31]¡GBIT_RXDMA_AGG_OLD_MOD, set 1 */
rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH + 3, BIT(7)); /* for dma agg , 0x280[31]GBIT_RXDMA_AGG_OLD_MOD, set 1 */
}
break;
case RX_AGG_USB:

98
hal/rtl8814a/Hal8814PwrSeq.c 100644
View File

@ -0,0 +1,98 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#include "Hal8814PwrSeq.h"
#include <rtl8814a_hal.h>
/*
drivers should parse below arrays and do the corresponding actions
*/
//3 Power on Array
WLAN_PWR_CFG rtl8814A_power_on_flow[RTL8814A_TRANS_CARDEMU_TO_ACT_STEPS+RTL8814A_TRANS_END_STEPS]=
{
RTL8814A_TRANS_CARDEMU_TO_ACT
RTL8814A_TRANS_END
};
//3Radio off GPIO Array
WLAN_PWR_CFG rtl8814A_radio_off_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8814A_TRANS_END_STEPS]=
{
RTL8814A_TRANS_ACT_TO_CARDEMU
RTL8814A_TRANS_END
};
//3Card Disable Array
WLAN_PWR_CFG rtl8814A_card_disable_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8814A_TRANS_END_STEPS]=
{
RTL8814A_TRANS_ACT_TO_CARDEMU
RTL8814A_TRANS_CARDEMU_TO_CARDDIS
RTL8814A_TRANS_END
};
//3 Card Enable Array
WLAN_PWR_CFG rtl8814A_card_enable_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8814A_TRANS_END_STEPS]=
{
RTL8814A_TRANS_CARDDIS_TO_CARDEMU
RTL8814A_TRANS_CARDEMU_TO_ACT
RTL8814A_TRANS_END
};
//3Suspend Array
WLAN_PWR_CFG rtl8814A_suspend_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8814A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8814A_TRANS_END_STEPS]=
{
RTL8814A_TRANS_ACT_TO_CARDEMU
RTL8814A_TRANS_CARDEMU_TO_SUS
RTL8814A_TRANS_END
};
//3 Resume Array
WLAN_PWR_CFG rtl8814A_resume_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8814A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8814A_TRANS_END_STEPS]=
{
RTL8814A_TRANS_SUS_TO_CARDEMU
RTL8814A_TRANS_CARDEMU_TO_ACT
RTL8814A_TRANS_END
};
//3HWPDN Array
WLAN_PWR_CFG rtl8814A_hwpdn_flow[RTL8814A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8814A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8814A_TRANS_END_STEPS]=
{
RTL8814A_TRANS_ACT_TO_CARDEMU
RTL8814A_TRANS_CARDEMU_TO_PDN
RTL8814A_TRANS_END
};
//3 Enter LPS
WLAN_PWR_CFG rtl8814A_enter_lps_flow[RTL8814A_TRANS_ACT_TO_LPS_STEPS+RTL8814A_TRANS_END_STEPS]=
{
//FW behavior
RTL8814A_TRANS_ACT_TO_LPS
RTL8814A_TRANS_END
};
//3 Leave LPS
WLAN_PWR_CFG rtl8814A_leave_lps_flow[RTL8814A_TRANS_LPS_TO_ACT_STEPS+RTL8814A_TRANS_END_STEPS]=
{
//FW behavior
RTL8814A_TRANS_LPS_TO_ACT
RTL8814A_TRANS_END
};

7741
hal/rtl8814a/hal8814a_fw.c 100644
View File

File diff suppressed because it is too large Load Diff

1515
hal/rtl8814a/rtl8814a_cmd.c 100644
View File

File diff suppressed because it is too large Load Diff

420
hal/rtl8814a/rtl8814a_dm.c 100644
View File

@ -0,0 +1,420 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//============================================================
// Description:
//
// This file is for 92CE/92CU dynamic mechanism only
//
//
//============================================================
#define _RTL8814A_DM_C_
//============================================================
// include files
//============================================================
//#include <drv_types.h>
#include <rtl8814a_hal.h>
//============================================================
// Global var
//============================================================
static VOID
dm_CheckProtection(
IN PADAPTER Adapter
)
{
#if 0
PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
u1Byte CurRate, RateThreshold;
if(pMgntInfo->pHTInfo->bCurBW40MHz)
RateThreshold = MGN_MCS1;
else
RateThreshold = MGN_MCS3;
if(Adapter->TxStats.CurrentInitTxRate <= RateThreshold)
{
pMgntInfo->bDmDisableProtect = TRUE;
DbgPrint("Forced disable protect: %x\n", Adapter->TxStats.CurrentInitTxRate);
}
else
{
pMgntInfo->bDmDisableProtect = FALSE;
DbgPrint("Enable protect: %x\n", Adapter->TxStats.CurrentInitTxRate);
}
#endif
}
#ifdef CONFIG_SUPPORT_HW_WPS_PBC
static void dm_CheckPbcGPIO(_adapter *padapter)
{
u8 tmp1byte;
u8 bPbcPressed = _FALSE;
if(!padapter->registrypriv.hw_wps_pbc)
return;
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
tmp1byte = rtw_read8(padapter, REG_GPIO_EXT_CTRL_8814A);
//DBG_871X("CheckPbcGPIO - %x\n", tmp1byte);
if (tmp1byte == 0xff)
return ;
else if (tmp1byte & BIT3)
{
// Here we only set bPbcPressed to TRUE. After trigger PBC, the variable will be set to FALSE
DBG_871X("CheckPbcGPIO - PBC is pressed\n");
bPbcPressed = _TRUE;
}
#endif
if (_TRUE == bPbcPressed) {
/* Here we only set bPbcPressed to true */
/* After trigger PBC, the variable will be set to false */
RTW_INFO("CheckPbcGPIO - PBC is pressed\n");
rtw_request_wps_pbc_event(padapter);
}
}
#endif /* #ifdef CONFIG_SUPPORT_HW_WPS_PBC */
#ifdef CONFIG_PCI_HCI
/*
* Description:
* Perform interrupt migration dynamically to reduce CPU utilization.
*
* Assumption:
* 1. Do not enable migration under WIFI test.
*
* Created by Roger, 2010.03.05.
* */
VOID
dm_InterruptMigration(
IN PADAPTER Adapter
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv);
BOOLEAN bCurrentIntMt, bCurrentACIntDisable;
BOOLEAN IntMtToSet = _FALSE;
BOOLEAN ACIntToSet = _FALSE;
/* Retrieve current interrupt migration and Tx four ACs IMR settings first. */
bCurrentIntMt = pHalData->bInterruptMigration;
bCurrentACIntDisable = pHalData->bDisableTxInt;
/* */
/* <Roger_Notes> Currently we use busy traffic for reference instead of RxIntOK counts to prevent non-linear Rx statistics */
/* when interrupt migration is set before. 2010.03.05. */
/* */
if (!Adapter->registrypriv.wifi_spec &&
(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) &&
pmlmepriv->LinkDetectInfo.bHigherBusyTraffic) {
IntMtToSet = _TRUE;
/* To check whether we should disable Tx interrupt or not. */
if (pmlmepriv->LinkDetectInfo.bHigherBusyRxTraffic)
ACIntToSet = _TRUE;
}
/* Update current settings. */
if (bCurrentIntMt != IntMtToSet) {
RTW_INFO("%s(): Update interrrupt migration(%d)\n", __FUNCTION__, IntMtToSet);
if (IntMtToSet) {
/* */
/* <Roger_Notes> Set interrrupt migration timer and corresponging Tx/Rx counter. */
/* timer 25ns*0xfa0=100us for 0xf packets. */
/* 2010.03.05. */
/* */
rtw_write32(Adapter, REG_INT_MIG, 0xff000fa0);/* 0x306:Rx, 0x307:Tx */
pHalData->bInterruptMigration = IntMtToSet;
} else {
/* Reset all interrupt migration settings. */
rtw_write32(Adapter, REG_INT_MIG, 0);
pHalData->bInterruptMigration = IntMtToSet;
}
}
#if 0
if (bCurrentACIntDisable != ACIntToSet) {
RTW_INFO("%s(): Update AC interrrupt(%d)\n", __FUNCTION__, ACIntToSet);
if (ACIntToSet) { /* Disable four ACs interrupts. */
/* */
/* <Roger_Notes> Disable VO, VI, BE and BK four AC interrupts to gain more efficient CPU utilization. */
/* When extremely highly Rx OK occurs, we will disable Tx interrupts. */
/* 2010.03.05. */
/* */
UpdateInterruptMask8192CE(Adapter, 0, RT_AC_INT_MASKS);
pHalData->bDisableTxInt = ACIntToSet;
} else { /* Enable four ACs interrupts. */
UpdateInterruptMask8192CE(Adapter, RT_AC_INT_MASKS, 0);
pHalData->bDisableTxInt = ACIntToSet;
}
}
#endif
}
#endif
/*
* Initialize GPIO setting registers
* */
static void
dm_InitGPIOSetting(
IN PADAPTER Adapter
)
{
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
u8 tmp1byte;
tmp1byte = rtw_read8(Adapter, REG_GPIO_MUXCFG);
tmp1byte &= (GPIOSEL_GPIO | ~GPIOSEL_ENBT);
rtw_write8(Adapter, REG_GPIO_MUXCFG, tmp1byte);
}
/* ************************************************************
* functions
* ************************************************************ */
static void Init_ODM_ComInfo_8814(PADAPTER Adapter)
{
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
struct dm_struct *pDM_Odm = &(pHalData->odmpriv);
u8 cut_ver, fab_ver;
Init_ODM_ComInfo(Adapter);
odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_IC_TYPE, ODM_RTL8814A);
fab_ver = ODM_TSMC;
if(IS_A_CUT(pHalData->version_id))
cut_ver = ODM_CUT_A;
else if(IS_B_CUT(pHalData->version_id))
cut_ver = ODM_CUT_B;
else if(IS_C_CUT(pHalData->version_id))
cut_ver = ODM_CUT_C;
else if(IS_D_CUT(pHalData->version_id))
cut_ver = ODM_CUT_D;
else if(IS_E_CUT(pHalData->version_id))
cut_ver = ODM_CUT_E;
else
cut_ver = ODM_CUT_A;
odm_cmn_info_init(pDM_Odm,ODM_CMNINFO_FAB_VER,fab_ver);
odm_cmn_info_init(pDM_Odm,ODM_CMNINFO_CUT_VER,cut_ver);
odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_RF_ANTENNA_TYPE, pHalData->TRxAntDivType);
//odm_cmn_info_init(pDM_Odm, ODM_CMNINFO_IQKFWOFFLOAD, pHalData->RegIQKFWOffload);
}
void
rtl8814_InitHalDm(
IN PADAPTER Adapter
)
{
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
struct dm_struct * pDM_Odm = &(pHalData->odmpriv);
u8 i;
#ifdef CONFIG_USB_HCI
dm_InitGPIOSetting(Adapter);
#endif //CONFIG_USB_HCI
odm_dm_init(pDM_Odm);
//Adapter->fix_rate = 0xFF;
}
VOID
rtl8814_HalDmWatchDog(
IN PADAPTER Adapter
)
{
BOOLEAN bFwCurrentInPSMode = _FALSE;
BOOLEAN bFwPSAwake = _TRUE;
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
struct dm_struct *pDM_Odm = &(pHalData->odmpriv);
struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(Adapter);
u8 in_lps = _FALSE;
if (!rtw_is_hw_init_completed(Adapter))
goto skip_dm;
#ifdef CONFIG_LPS
bFwCurrentInPSMode = adapter_to_pwrctl(Adapter)->bFwCurrentInPSMode;
rtw_hal_get_hwreg(Adapter, HW_VAR_FWLPS_RF_ON, &bFwPSAwake);
#endif
#ifdef CONFIG_P2P_PS
/* Fw is under p2p powersaving mode, driver should stop dynamic mechanism. */
/* modifed by thomas. 2011.06.11. */
if (Adapter->wdinfo.p2p_ps_mode)
bFwPSAwake = _FALSE;
#endif /* CONFIG_P2P_PS */
if ((rtw_is_hw_init_completed(Adapter))
&& ((!bFwCurrentInPSMode) && bFwPSAwake)) {
rtw_hal_check_rxfifo_full(Adapter);
/* */
/* Dynamically switch RTS/CTS protection. */
/* */
/* dm_CheckProtection(Adapter); */
#ifdef CONFIG_PCI_HCI
/* 20100630 Joseph: Disable Interrupt Migration mechanism temporarily because it degrades Rx throughput. */
/* Tx Migration settings. */
/* dm_InterruptMigration(Adapter); */
/* if(Adapter->HalFunc.TxCheckStuckHandler(Adapter)) */
/* PlatformScheduleWorkItem(&(GET_HAL_DATA(Adapter)->HalResetWorkItem)); */
#endif
}
#ifdef CONFIG_DISABLE_ODM
goto skip_dm;
#endif
#ifdef CONFIG_LPS
if (pwrpriv->bLeisurePs && bFwCurrentInPSMode && pwrpriv->pwr_mode != PS_MODE_ACTIVE)
in_lps = _TRUE;
#endif
rtw_phydm_watchdog(Adapter, in_lps);
skip_dm:
#ifdef CONFIG_SUPPORT_HW_WPS_PBC
/* Check GPIO to determine current Pbc status. */
dm_CheckPbcGPIO(Adapter);
#endif
return;
}
void rtl8814_init_dm_priv(IN PADAPTER Adapter)
{
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
struct dm_struct *podmpriv = &pHalData->odmpriv;
/* _rtw_spinlock_init(&(pHalData->odm_stainfo_lock)); */
#ifndef CONFIG_IQK_PA_OFF /* FW has no IQK PA OFF option yet, don't offload */
#ifdef CONFIG_BT_COEXIST
/* firmware size issue, btcoex fw doesn't support IQK offload */
if (pHalData->EEPROMBluetoothCoexist == _FALSE)
#endif
{
pHalData->RegIQKFWOffload = 1;
rtw_sctx_init(&pHalData->iqk_sctx, 0);
}
#endif
Init_ODM_ComInfo_8814(Adapter);
odm_init_all_timers(podmpriv );
//PHYDM_InitDebugSetting(podmpriv);
pHalData->CurrentTxPwrIdx = 18;
}
void rtl8814_deinit_dm_priv(IN PADAPTER Adapter)
{
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
struct dm_struct *podmpriv = &pHalData->odmpriv;
/* _rtw_spinlock_free(&pHalData->odm_stainfo_lock); */
odm_cancel_all_timers(podmpriv);
}
#ifdef CONFIG_ANTENNA_DIVERSITY
// Add new function to reset the state of antenna diversity before link.
//
// Compare RSSI for deciding antenna
void AntDivCompare8814(PADAPTER Adapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src)
{
//PADAPTER Adapter = pDM_Odm->Adapter ;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
if(0 != pHalData->AntDivCfg )
{
//DBG_8192C("update_network=> orgRSSI(%d)(%d),newRSSI(%d)(%d)\n",dst->Rssi,query_rx_pwr_percentage(dst->Rssi),
// src->Rssi,query_rx_pwr_percentage(src->Rssi));
//select optimum_antenna for before linked =>For antenna diversity
if(dst->Rssi >= src->Rssi )//keep org parameter
{
src->Rssi = dst->Rssi;
src->PhyInfo.Optimum_antenna = dst->PhyInfo.Optimum_antenna;
}
}
}
// Add new function to reset the state of antenna diversity before link.
u8 AntDivBeforeLink8814(PADAPTER Adapter )
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
struct dm_struct * pDM_Odm =&pHalData->odmpriv;
SWAT_T *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv);
// Condition that does not need to use antenna diversity.
if(pHalData->AntDivCfg==0)
{
//DBG_8192C("odm_AntDivBeforeLink8192C(): No AntDiv Mechanism.\n");
return _FALSE;
}
if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)
{
return _FALSE;
}
if(pDM_SWAT_Table->SWAS_NoLink_State == 0){
//switch channel
pDM_SWAT_Table->SWAS_NoLink_State = 1;
pDM_SWAT_Table->CurAntenna = (pDM_SWAT_Table->CurAntenna==MAIN_ANT)?AUX_ANT:MAIN_ANT;
//PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, pDM_SWAT_Table->CurAntenna);
rtw_antenna_select_cmd(Adapter, pDM_SWAT_Table->CurAntenna, _FALSE);
//DBG_8192C("%s change antenna to ANT_( %s ).....\n",__FUNCTION__, (pDM_SWAT_Table->CurAntenna==MAIN_ANT)?"MAIN":"AUX");
return _TRUE;
}
else
{
pDM_SWAT_Table->SWAS_NoLink_State = 0;
return _FALSE;
}
}
#endif //CONFIG_ANTENNA_DIVERSITY

6769
hal/rtl8814a/rtl8814a_hal_init.c 100644
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File diff suppressed because it is too large Load Diff

3027
hal/rtl8814a/rtl8814a_phycfg.c 100644
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File diff suppressed because it is too large Load Diff

210
hal/rtl8814a/rtl8814a_rf6052.c 100644
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@ -0,0 +1,210 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#define _RTL8814A_RF6052_C_
//#include <drv_types.h>
#include <rtl8814a_hal.h>
/*-----------------------------------------------------------------------------
* Function: PHY_RF6052SetBandwidth()
*
* Overview: This function is called by SetBWModeCallback8190Pci() only
*
* Input: PADAPTER Adapter
* WIRELESS_BANDWIDTH_E Bandwidth //20M or 40M
*
* Output: NONE
*
* Return: NONE
*
* Note: For RF type 0222D
*---------------------------------------------------------------------------*/
VOID
PHY_RF6052SetBandwidth8814A(
IN PADAPTER Adapter,
IN enum channel_width Bandwidth) //20M or 40M
{
switch(Bandwidth)
{
case CHANNEL_WIDTH_20:
/*RTW_INFO("PHY_RF6052SetBandwidth8814A(), set 20MHz\n");*/
phy_set_rf_reg(Adapter, RF_PATH_A, RF_CHNLBW_Jaguar, BIT11|BIT10, 3);
phy_set_rf_reg(Adapter, RF_PATH_B, RF_CHNLBW_Jaguar, BIT11|BIT10, 3);
phy_set_rf_reg(Adapter, RF_PATH_C, RF_CHNLBW_Jaguar, BIT11|BIT10, 3);
phy_set_rf_reg(Adapter, RF_PATH_D, RF_CHNLBW_Jaguar, BIT11|BIT10, 3);
break;
case CHANNEL_WIDTH_40:
/*RTW_INFO("PHY_RF6052SetBandwidth8814A(), set 40MHz\n");*/
phy_set_rf_reg(Adapter, RF_PATH_A, RF_CHNLBW_Jaguar, BIT11|BIT10, 1);
phy_set_rf_reg(Adapter, RF_PATH_B, RF_CHNLBW_Jaguar, BIT11|BIT10, 1);
phy_set_rf_reg(Adapter, RF_PATH_C, RF_CHNLBW_Jaguar, BIT11|BIT10, 1);
phy_set_rf_reg(Adapter, RF_PATH_D, RF_CHNLBW_Jaguar, BIT11|BIT10, 1);
break;
case CHANNEL_WIDTH_80:
/*RTW_INFO("PHY_RF6052SetBandwidth8814A(), set 80MHz\n");*/
phy_set_rf_reg(Adapter, RF_PATH_A, RF_CHNLBW_Jaguar, BIT11|BIT10, 0);
phy_set_rf_reg(Adapter, RF_PATH_B, RF_CHNLBW_Jaguar, BIT11|BIT10, 0);
phy_set_rf_reg(Adapter, RF_PATH_C, RF_CHNLBW_Jaguar, BIT11|BIT10, 0);
phy_set_rf_reg(Adapter, RF_PATH_D, RF_CHNLBW_Jaguar, BIT11|BIT10, 0);
break;
default:
RTW_INFO("PHY_RF6052SetBandwidth8814A(): unknown Bandwidth: %#X\n",Bandwidth );
break;
}
}
static int
phy_RF6052_Config_ParaFile_8814A(
IN PADAPTER Adapter
)
{
u32 u4RegValue=0;
u8 eRFPath;
int rtStatus = _SUCCESS;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
static char sz8814RadioAFile[] = PHY_FILE_RADIO_A;
static char sz8814RadioBFile[] = PHY_FILE_RADIO_B;
static char sz8814RadioCFile[] = PHY_FILE_RADIO_C;
static char sz8814RadioDFile[] = PHY_FILE_RADIO_D;
static char sz8814TxPwrTrack[] = PHY_FILE_TXPWR_TRACK;
char *pszRadioAFile = NULL, *pszRadioBFile = NULL, *pszRadioCFile = NULL, *pszRadioDFile = NULL, *pszTxPwrTrack = NULL;
pszRadioAFile = sz8814RadioAFile;
pszRadioBFile = sz8814RadioBFile;
pszRadioCFile = sz8814RadioCFile;
pszRadioDFile = sz8814RadioDFile;
pszTxPwrTrack = sz8814TxPwrTrack;
//3//-----------------------------------------------------------------
//3// <2> Initialize RF
//3//-----------------------------------------------------------------
//for(eRFPath = RF_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
{
/*----Initialize RF fom connfiguration file----*/
switch(eRFPath)
{
case RF_PATH_A:
#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
if (PHY_ConfigRFWithParaFile(Adapter, pszRadioAFile, eRFPath) == _FAIL)
#endif //CONFIG_LOAD_PHY_PARA_FROM_FILE
{
#ifdef CONFIG_EMBEDDED_FWIMG
if(HAL_STATUS_FAILURE ==odm_config_rf_with_header_file(&pHalData->odmpriv,CONFIG_RF_RADIO, (enum rf_path)eRFPath))
rtStatus = _FAIL;
#endif //CONFIG_EMBEDDED_FWIMG
}
break;
case RF_PATH_B:
#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
if (PHY_ConfigRFWithParaFile(Adapter, pszRadioBFile, eRFPath) == _FAIL)
#endif //CONFIG_LOAD_PHY_PARA_FROM_FILE
{
#ifdef CONFIG_EMBEDDED_FWIMG
if(HAL_STATUS_FAILURE ==odm_config_rf_with_header_file(&pHalData->odmpriv,CONFIG_RF_RADIO, (enum rf_path)eRFPath))
rtStatus = _FAIL;
#endif //CONFIG_EMBEDDED_FWIMG
}
break;
case RF_PATH_C:
#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
if (PHY_ConfigRFWithParaFile(Adapter, pszRadioCFile, eRFPath) == _FAIL)
#endif //CONFIG_LOAD_PHY_PARA_FROM_FILE
{
#ifdef CONFIG_EMBEDDED_FWIMG
if(HAL_STATUS_FAILURE ==odm_config_rf_with_header_file(&pHalData->odmpriv,CONFIG_RF_RADIO, (enum rf_path)eRFPath))
rtStatus = _FAIL;
#endif //CONFIG_EMBEDDED_FWIMG
}
break;
case RF_PATH_D:
#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
if (PHY_ConfigRFWithParaFile(Adapter, pszRadioDFile, eRFPath) == _FAIL)
#endif //CONFIG_LOAD_PHY_PARA_FROM_FILE
{
#ifdef CONFIG_EMBEDDED_FWIMG
if(HAL_STATUS_FAILURE ==odm_config_rf_with_header_file(&pHalData->odmpriv,CONFIG_RF_RADIO, (enum rf_path)eRFPath))
rtStatus = _FAIL;
#endif //CONFIG_EMBEDDED_FWIMG
}
break;
default:
break;
}
if(rtStatus != _SUCCESS){
RTW_INFO("%s():Radio[%d] Fail!!", __FUNCTION__, eRFPath);
goto phy_RF6052_Config_ParaFile_Fail;
}
}
u4RegValue = phy_query_rf_reg(Adapter, RF_PATH_A, RF_RCK1_Jaguar, bRFRegOffsetMask);
phy_set_rf_reg(Adapter, RF_PATH_B, RF_RCK1_Jaguar, bRFRegOffsetMask, u4RegValue);
phy_set_rf_reg(Adapter, RF_PATH_C, RF_RCK1_Jaguar, bRFRegOffsetMask, u4RegValue);
phy_set_rf_reg(Adapter, RF_PATH_D, RF_RCK1_Jaguar, bRFRegOffsetMask, u4RegValue);
//3 -----------------------------------------------------------------
//3 Configuration of Tx Power Tracking
//3 -----------------------------------------------------------------
#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE
if (PHY_ConfigRFWithTxPwrTrackParaFile(Adapter, pszTxPwrTrack) == _FAIL)
#endif //CONFIG_LOAD_PHY_PARA_FROM_FILE
{
#ifdef CONFIG_EMBEDDED_FWIMG
odm_config_rf_with_tx_pwr_track_header_file(&pHalData->odmpriv);
#endif
}
//RT_TRACE(COMP_INIT, DBG_LOUD, ("<---phy_RF6052_Config_ParaFile_8812()\n"));
phy_RF6052_Config_ParaFile_Fail:
return rtStatus;
}
int
PHY_RF6052_Config_8814A(
IN PADAPTER Adapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
int rtStatus = _SUCCESS;
// Initialize general global value
pHalData->NumTotalRFPath = 4;
//
// Config BB and RF
//
rtStatus = phy_RF6052_Config_ParaFile_8814A(Adapter);
return rtStatus;
}
/* End of HalRf6052.c */

68
hal/rtl8814a/rtl8814a_rxdesc.c 100644
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@ -0,0 +1,68 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#define _RTL8814A_RXDESC_C_
//#include <drv_types.h>
#include <rtl8814a_hal.h>
void rtl8814_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc)
{
struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib;
_rtw_memset(pattrib, 0, sizeof(struct rx_pkt_attrib));
#ifdef CONFIG_RADIOTAP_WITH_RXDESC
_rtw_memcpy(pattrib->rxdesc, pdesc, RXDESC_SIZE);
#endif
//Offset 0
pattrib->pkt_len = (u16)GET_RX_STATUS_DESC_PKT_LEN_8814A(pdesc);//(le32_to_cpu(pdesc->rxdw0)&0x00003fff)
pattrib->crc_err = (u8)GET_RX_STATUS_DESC_CRC32_8814A(pdesc);//((le32_to_cpu(pdesc->rxdw0) >> 14) & 0x1);
pattrib->icv_err = (u8)GET_RX_STATUS_DESC_ICV_8814A(pdesc);//((le32_to_cpu(pdesc->rxdw0) >> 15) & 0x1);
pattrib->drvinfo_sz = (u8)GET_RX_STATUS_DESC_DRVINFO_SIZE_8814A(pdesc) * 8;//((le32_to_cpu(pdesc->rxdw0) >> 16) & 0xf) * 8;//uint 2^3 = 8 bytes
pattrib->encrypt = (u8)GET_RX_STATUS_DESC_SECURITY_8814A(pdesc);//((le32_to_cpu(pdesc->rxdw0) >> 20) & 0x7);
pattrib->qos = (u8)GET_RX_STATUS_DESC_QOS_8814A(pdesc);//(( le32_to_cpu( pdesc->rxdw0 ) >> 23) & 0x1);// Qos data, wireless lan header length is 26
pattrib->shift_sz = (u8)GET_RX_STATUS_DESC_SHIFT_8814A(pdesc);//((le32_to_cpu(pdesc->rxdw0) >> 24) & 0x3);
pattrib->physt = (u8)GET_RX_STATUS_DESC_PHY_STATUS_8814A(pdesc);//((le32_to_cpu(pdesc->rxdw0) >> 26) & 0x1);
pattrib->bdecrypted = !GET_RX_STATUS_DESC_SWDEC_8814A(pdesc);//(le32_to_cpu(pdesc->rxdw0) & BIT(27))? 0:1;
//Offset 4
pattrib->priority = (u8)GET_RX_STATUS_DESC_TID_8814A(pdesc);//((le32_to_cpu(pdesc->rxdw1) >> 8) & 0xf);
pattrib->mdata = (u8)GET_RX_STATUS_DESC_MORE_DATA_8814A(pdesc);//((le32_to_cpu(pdesc->rxdw1) >> 26) & 0x1);
pattrib->mfrag = (u8)GET_RX_STATUS_DESC_MORE_FRAG_8814A(pdesc);//((le32_to_cpu(pdesc->rxdw1) >> 27) & 0x1);//more fragment bit
//Offset 8
pattrib->seq_num = (u16)GET_RX_STATUS_DESC_SEQ_8814A(pdesc);//(le32_to_cpu(pdesc->rxdw2) & 0x00000fff);
pattrib->frag_num = (u8)GET_RX_STATUS_DESC_FRAG_8814A(pdesc);//((le32_to_cpu(pdesc->rxdw2) >> 12) & 0xf);//fragmentation number
if (GET_RX_STATUS_DESC_RPT_SEL_8814A(pdesc))
pattrib->pkt_rpt_type = C2H_PACKET;
else
pattrib->pkt_rpt_type = NORMAL_RX;
//Offset 12
pattrib->data_rate=(u8)GET_RX_STATUS_DESC_RX_RATE_8814A(pdesc);//((le32_to_cpu(pdesc->rxdw3))&0x7f);
//Offset 16
//Offset 20
}

114
hal/rtl8814a/rtl8814a_sreset.c 100644
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@ -0,0 +1,114 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#define _RTL8814A_SRESET_C_
//#include <drv_types.h>
#include <rtl8814a_hal.h>
#ifdef DBG_CONFIG_ERROR_DETECT
void rtl8814_sreset_xmit_status_check(_adapter *padapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
struct sreset_priv *psrtpriv = &pHalData->srestpriv;
unsigned long current_time;
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
unsigned int diff_time;
u32 txdma_status;
if( (txdma_status=rtw_read32(padapter, REG_TXDMA_STATUS)) !=0x00){
RTW_INFO("%s REG_TXDMA_STATUS:0x%08x\n", __FUNCTION__, txdma_status);
rtw_hal_sreset_reset(padapter);
}
#ifdef CONFIG_USB_HCI
//total xmit irp = 4
//DBG_8192C("==>%s free_xmitbuf_cnt(%d),txirp_cnt(%d)\n",__FUNCTION__,pxmitpriv->free_xmitbuf_cnt,pxmitpriv->txirp_cnt);
//if(pxmitpriv->txirp_cnt == NR_XMITBUFF+1)
current_time = rtw_get_current_time();
if (0 == pxmitpriv->free_xmitbuf_cnt || 0 == pxmitpriv->free_xmit_extbuf_cnt) {
diff_time = rtw_get_passing_time_ms(psrtpriv->last_tx_time);
if (diff_time > 2000) {
if (psrtpriv->last_tx_complete_time == 0) {
psrtpriv->last_tx_complete_time = current_time;
}
else{
diff_time = rtw_get_passing_time_ms(psrtpriv->last_tx_complete_time);
if (diff_time > 4000) {
u32 ability = 0;
//padapter->Wifi_Error_Status = WIFI_TX_HANG;
ability = rtw_phydm_ability_get(padapter);
RTW_INFO("%s tx hang %s\n", __FUNCTION__,
(ability & ODM_BB_ADAPTIVITY)? "ODM_BB_ADAPTIVITY" : "");
if (!(ability & ODM_BB_ADAPTIVITY))
rtw_hal_sreset_reset(padapter);
}
}
}
}
#endif //CONFIG_USB_HCI
if (psrtpriv->dbg_trigger_point == SRESET_TGP_XMIT_STATUS) {
psrtpriv->dbg_trigger_point = SRESET_TGP_NULL;
rtw_hal_sreset_reset(padapter);
return;
}
}
void rtl8814_sreset_linked_status_check(_adapter *padapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
struct sreset_priv *psrtpriv = &pHalData->srestpriv;
u32 rx_dma_status = 0;
rx_dma_status = rtw_read32(padapter,REG_RXDMA_STATUS);
if(rx_dma_status!= 0x00){
RTW_INFO("%s REG_RXDMA_STATUS:0x%08x\n",__FUNCTION__,rx_dma_status);
}
#if 0
u32 regc50,regc58,reg824,reg800;
regc50 = rtw_read32(padapter,0xc50);
regc58 = rtw_read32(padapter,0xc58);
reg824 = rtw_read32(padapter,0x824);
reg800 = rtw_read32(padapter,0x800);
if( ((regc50&0xFFFFFF00)!= 0x69543400)||
((regc58&0xFFFFFF00)!= 0x69543400)||
(((reg824&0xFFFFFF00)!= 0x00390000)&&(((reg824&0xFFFFFF00)!= 0x80390000)))||
( ((reg800&0xFFFFFF00)!= 0x03040000)&&((reg800&0xFFFFFF00)!= 0x83040000)))
{
DBG_8192C("%s regc50:0x%08x, regc58:0x%08x, reg824:0x%08x, reg800:0x%08x,\n", __FUNCTION__,
regc50, regc58, reg824, reg800);
rtw_hal_sreset_reset(padapter);
}
#endif
if (psrtpriv->dbg_trigger_point == SRESET_TGP_LINK_STATUS) {
psrtpriv->dbg_trigger_point = SRESET_TGP_NULL;
rtw_hal_sreset_reset(padapter);
return;
}
}
#endif

515
hal/rtl8814a/rtl8814a_xmit.c 100644
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@ -0,0 +1,515 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#define _RTL8814A_XMIT_C_
//#include <drv_types.h>
#include <rtl8814a_hal.h>
/*
* Description:
* Aggregation packets and send to hardware
*
* Return:
* 0 Success
* -1 Hardware resource(TX FIFO) not ready
* -2 Software resource(xmitbuf) not ready
*/
#ifdef CONFIG_TX_EARLY_MODE
//#define DBG_EMINFO
#if RTL8188E_EARLY_MODE_PKT_NUM_10 == 1
#define EARLY_MODE_MAX_PKT_NUM 10
#else
#define EARLY_MODE_MAX_PKT_NUM 5
#endif
struct EMInfo{
u8 EMPktNum;
u16 EMPktLen[EARLY_MODE_MAX_PKT_NUM];
};
void
InsertEMContent_8814(
struct EMInfo *pEMInfo,
IN pu1Byte VirtualAddress)
{
#if RTL8188E_EARLY_MODE_PKT_NUM_10 == 1
u1Byte index=0;
u4Byte dwtmp=0;
#endif
_rtw_memset(VirtualAddress, 0, EARLY_MODE_INFO_SIZE);
if(pEMInfo->EMPktNum==0)
return;
#ifdef DBG_EMINFO
{
int i;
RTW_INFO("\n%s ==> pEMInfo->EMPktNum =%d\n",__FUNCTION__,pEMInfo->EMPktNum);
for(i=0;i< EARLY_MODE_MAX_PKT_NUM;i++){
RTW_INFO("%s ==> pEMInfo->EMPktLen[%d] =%d\n",__FUNCTION__,i,pEMInfo->EMPktLen[i]);
}
}
#endif
#if RTL8188E_EARLY_MODE_PKT_NUM_10 == 1
SET_EARLYMODE_PKTNUM(VirtualAddress, pEMInfo->EMPktNum);
if(pEMInfo->EMPktNum == 1){
dwtmp = pEMInfo->EMPktLen[0];
}else{
dwtmp = pEMInfo->EMPktLen[0];
dwtmp += ((dwtmp%4)?(4-dwtmp%4):0)+4;
dwtmp += pEMInfo->EMPktLen[1];
}
SET_EARLYMODE_LEN0(VirtualAddress, dwtmp);
if(pEMInfo->EMPktNum <= 3){
dwtmp = pEMInfo->EMPktLen[2];
}else{
dwtmp = pEMInfo->EMPktLen[2];
dwtmp += ((dwtmp%4)?(4-dwtmp%4):0)+4;
dwtmp += pEMInfo->EMPktLen[3];
}
SET_EARLYMODE_LEN1(VirtualAddress, dwtmp);
if(pEMInfo->EMPktNum <= 5){
dwtmp = pEMInfo->EMPktLen[4];
}else{
dwtmp = pEMInfo->EMPktLen[4];
dwtmp += ((dwtmp%4)?(4-dwtmp%4):0)+4;
dwtmp += pEMInfo->EMPktLen[5];
}
SET_EARLYMODE_LEN2_1(VirtualAddress, dwtmp&0xF);
SET_EARLYMODE_LEN2_2(VirtualAddress, dwtmp>>4);
if(pEMInfo->EMPktNum <= 7){
dwtmp = pEMInfo->EMPktLen[6];
}else{
dwtmp = pEMInfo->EMPktLen[6];
dwtmp += ((dwtmp%4)?(4-dwtmp%4):0)+4;
dwtmp += pEMInfo->EMPktLen[7];
}
SET_EARLYMODE_LEN3(VirtualAddress, dwtmp);
if(pEMInfo->EMPktNum <= 9){
dwtmp = pEMInfo->EMPktLen[8];
}else{
dwtmp = pEMInfo->EMPktLen[8];
dwtmp += ((dwtmp%4)?(4-dwtmp%4):0)+4;
dwtmp += pEMInfo->EMPktLen[9];
}
SET_EARLYMODE_LEN4(VirtualAddress, dwtmp);
#else
SET_EARLYMODE_PKTNUM(VirtualAddress, pEMInfo->EMPktNum);
SET_EARLYMODE_LEN0(VirtualAddress, pEMInfo->EMPktLen[0]);
SET_EARLYMODE_LEN1(VirtualAddress, pEMInfo->EMPktLen[1]);
SET_EARLYMODE_LEN2_1(VirtualAddress, pEMInfo->EMPktLen[2]&0xF);
SET_EARLYMODE_LEN2_2(VirtualAddress, pEMInfo->EMPktLen[2]>>4);
SET_EARLYMODE_LEN3(VirtualAddress, pEMInfo->EMPktLen[3]);
SET_EARLYMODE_LEN4(VirtualAddress, pEMInfo->EMPktLen[4]);
#endif
//RT_PRINT_DATA(COMP_SEND, DBG_LOUD, "EMHdr:", VirtualAddress, 8);
}
void UpdateEarlyModeInfo8814(struct xmit_priv *pxmitpriv,struct xmit_buf *pxmitbuf )
{
//_adapter *padapter, struct xmit_frame *pxmitframe,struct tx_servq *ptxservq
int index,j;
u16 offset,pktlen;
PTXDESC_8814 ptxdesc;
u8 *pmem,*pEMInfo_mem;
s8 node_num_0=0,node_num_1=0;
struct EMInfo eminfo;
struct agg_pkt_info *paggpkt;
struct xmit_frame *pframe = (struct xmit_frame*)pxmitbuf->priv_data;
pmem= pframe->buf_addr;
#ifdef DBG_EMINFO
RTW_INFO("\n%s ==> agg_num:%d\n",__FUNCTION__, pframe->agg_num);
for(index=0;index<pframe->agg_num;index++){
offset = pxmitpriv->agg_pkt[index].offset;
pktlen = pxmitpriv->agg_pkt[index].pkt_len;
RTW_INFO("%s ==> agg_pkt[%d].offset=%d\n",__FUNCTION__,index,offset);
RTW_INFO("%s ==> agg_pkt[%d].pkt_len=%d\n",__FUNCTION__,index,pktlen);
}
#endif
if( pframe->agg_num > EARLY_MODE_MAX_PKT_NUM)
{
node_num_0 = pframe->agg_num;
node_num_1= EARLY_MODE_MAX_PKT_NUM-1;
}
for(index=0;index<pframe->agg_num;index++){
offset = pxmitpriv->agg_pkt[index].offset;
pktlen = pxmitpriv->agg_pkt[index].pkt_len;
_rtw_memset(&eminfo,0,sizeof(struct EMInfo));
if( pframe->agg_num > EARLY_MODE_MAX_PKT_NUM){
if(node_num_0 > EARLY_MODE_MAX_PKT_NUM){
eminfo.EMPktNum = EARLY_MODE_MAX_PKT_NUM;
node_num_0--;
}
else{
eminfo.EMPktNum = node_num_1;
node_num_1--;
}
}
else{
eminfo.EMPktNum = pframe->agg_num-(index+1);
}
for(j=0;j< eminfo.EMPktNum ;j++){
eminfo.EMPktLen[j] = pxmitpriv->agg_pkt[index+1+j].pkt_len+4;// 4 bytes CRC
}
if(pmem){
if(index==0){
ptxdesc = (PTXDESC_8814)(pmem);
pEMInfo_mem = ((u8 *)ptxdesc)+TXDESC_SIZE;
}
else{
pmem = pmem + pxmitpriv->agg_pkt[index-1].offset;
ptxdesc = (PTXDESC_8814)(pmem);
pEMInfo_mem = ((u8 *)ptxdesc)+TXDESC_SIZE;
}
#ifdef DBG_EMINFO
RTW_INFO("%s ==> desc.pkt_len=%d\n",__FUNCTION__,ptxdesc->pktlen);
#endif
InsertEMContent_8814(&eminfo,pEMInfo_mem);
}
}
_rtw_memset(pxmitpriv->agg_pkt,0,sizeof(struct agg_pkt_info)*MAX_AGG_PKT_NUM);
}
#endif
#if ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
void rtl8814a_cal_txdesc_chksum(u8 *ptxdesc)
{
u16 *usPtr;
u32 count;
u32 index;
u16 checksum = 0;
usPtr = (u16*)ptxdesc;
// checksume is always calculated by first 32 bytes,
// and it doesn't depend on TX DESC length.
// Thomas,Lucas@SD4,20130515
count = 16;
// Clear first
SET_TX_DESC_TX_DESC_CHECKSUM_8814A(ptxdesc, 0);
for(index = 0 ; index < count ; index++){
checksum = checksum ^ le16_to_cpu(*(usPtr + index));
}
SET_TX_DESC_TX_DESC_CHECKSUM_8814A(ptxdesc, checksum);
}
#endif
//
// Description: In normal chip, we should send some packet to Hw which will be used by Fw
// in FW LPS mode. The function is to fill the Tx descriptor of this packets, then
// Fw can tell Hw to send these packet derectly.
//
void rtl8814a_fill_fake_txdesc(
PADAPTER padapter,
u8* pDesc,
u32 BufferLen,
u8 IsPsPoll,
u8 IsBTQosNull,
u8 bDataFrame)
{
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
// Clear all status
_rtw_memset(pDesc, 0, TXDESC_SIZE);
SET_TX_DESC_LAST_SEG_8814A(pDesc, 1);
SET_TX_DESC_OFFSET_8814A(pDesc, TXDESC_SIZE);
SET_TX_DESC_PKT_SIZE_8814A(pDesc, BufferLen);
SET_TX_DESC_QUEUE_SEL_8814A(pDesc, QSLT_MGNT);
if (pmlmeext->cur_wireless_mode & WIRELESS_11B) {
SET_TX_DESC_RATE_ID_8814A(pDesc, RATEID_IDX_B);
} else {
SET_TX_DESC_RATE_ID_8814A(pDesc, RATEID_IDX_G);
}
//Set NAVUSEHDR to prevent Ps-poll AId filed to be changed to error vlaue by Hw.
if (IsPsPoll)
{
SET_TX_DESC_NAV_USE_HDR_8814A(pDesc, 1);
}
else
{
SET_TX_DESC_HWSEQ_EN_8814A(pDesc, 1); // Hw set sequence number
}
#if 0 //todo
if(IsBTQosNull)
{
SET_TX_DESC_BT_INT_8812(pDesc, 1);
}
#endif //0
SET_TX_DESC_USE_RATE_8814A(pDesc, 1);
//8814 no OWN bit?
//SET_TX_DESC_OWN_8812(pDesc, 1);
//
// Encrypt the data frame if under security mode excepct null data. Suggested by CCW.
//
if (_TRUE ==bDataFrame)
{
u32 EncAlg;
EncAlg = padapter->securitypriv.dot11PrivacyAlgrthm;
switch (EncAlg)
{
case _NO_PRIVACY_:
SET_TX_DESC_SEC_TYPE_8814A(pDesc, 0x0);
break;
case _WEP40_:
case _WEP104_:
case _TKIP_:
SET_TX_DESC_SEC_TYPE_8814A(pDesc, 0x1);
break;
case _SMS4_:
SET_TX_DESC_SEC_TYPE_8814A(pDesc, 0x2);
break;
case _AES_:
SET_TX_DESC_SEC_TYPE_8814A(pDesc, 0x3);
break;
default:
SET_TX_DESC_SEC_TYPE_8814A(pDesc, 0x0);
break;
}
}
SET_TX_DESC_TX_RATE_8814A(pDesc, MRateToHwRate(pmlmeext->tx_rate));
#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI)
// USB interface drop packet if the checksum of descriptor isn't correct.
// Using this checksum can let hardware recovery from packet bulk out error (e.g. Cancel URC, Bulk out error.).
rtl8814a_cal_txdesc_chksum(pDesc);
#endif
}
void rtl8814a_fill_txdesc_sectype(struct pkt_attrib *pattrib, u8 *ptxdesc)
{
if ((pattrib->encrypt > 0) && !pattrib->bswenc)
{
switch (pattrib->encrypt)
{
//SEC_TYPE : 0:NO_ENC,1:WEP40/TKIP,2:WAPI,3:AES
case _WEP40_:
case _WEP104_:
case _TKIP_:
case _TKIP_WTMIC_:
SET_TX_DESC_SEC_TYPE_8814A(ptxdesc, 0x1);
break;
#ifdef CONFIG_WAPI_SUPPORT
case _SMS4_:
SET_TX_DESC_SEC_TYPE_8814A(ptxdesc, 0x2);
break;
#endif
case _AES_:
SET_TX_DESC_SEC_TYPE_8814A(ptxdesc, 0x3);
break;
case _NO_PRIVACY_:
default:
SET_TX_DESC_SEC_TYPE_8814A(ptxdesc, 0x0);
break;
}
}
}
void rtl8814a_fill_txdesc_vcs(PADAPTER padapter, struct pkt_attrib *pattrib, u8 *ptxdesc)
{
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
//RTW_INFO("vcs_mode=%d\n", pattrib->vcs_mode);
if (pattrib->vcs_mode) {
switch(pattrib->vcs_mode)
{
case RTS_CTS:
SET_TX_DESC_RTS_ENABLE_8814A(ptxdesc, 1);
break;
case CTS_TO_SELF:
SET_TX_DESC_CTS2SELF_8814A(ptxdesc, 1);
break;
case NONE_VCS:
default:
break;
}
if (pmlmeinfo->preamble_mode == PREAMBLE_SHORT)
SET_TX_DESC_RTS_SHORT_8814A(ptxdesc, 1);
SET_TX_DESC_RTS_RATE_8814A(ptxdesc, 0x8);//RTS Rate=24M
SET_TX_DESC_RTS_RATE_FB_LIMIT_8814A(ptxdesc, 0xf);
}
}
u8
BWMapping_8814(
IN PADAPTER Adapter,
IN struct pkt_attrib *pattrib
)
{
u8 BWSettingOfDesc = 0;
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
//RTW_INFO("BWMapping pHalData->current_channel_bw %d, pattrib->bwmode %d \n",pHalData->current_channel_bw,pattrib->bwmode);
if(pHalData->current_channel_bw== CHANNEL_WIDTH_80)
{
if(pattrib->bwmode == CHANNEL_WIDTH_80)
BWSettingOfDesc= 2;
else if(pattrib->bwmode == CHANNEL_WIDTH_40)
BWSettingOfDesc = 1;
else
BWSettingOfDesc = 0;
}
else if(pHalData->current_channel_bw== CHANNEL_WIDTH_40)
{
if((pattrib->bwmode == CHANNEL_WIDTH_40) || (pattrib->bwmode == CHANNEL_WIDTH_80))
BWSettingOfDesc = 1;
else
BWSettingOfDesc = 0;
}
else
BWSettingOfDesc = 0;
return BWSettingOfDesc;
}
u8
SCMapping_8814(
IN PADAPTER Adapter,
IN struct pkt_attrib *pattrib
)
{
u8 SCSettingOfDesc = 0;
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
//RTW_INFO("SCMapping: pHalData->current_channel_bw %d, pHalData->nCur80MhzPrimeSC %d, pHalData->nCur40MhzPrimeSC %d \n",pHalData->current_channel_bw,pHalData->nCur80MhzPrimeSC,pHalData->nCur40MhzPrimeSC);
if(pHalData->current_channel_bw == CHANNEL_WIDTH_80)
{
if(pattrib->bwmode == CHANNEL_WIDTH_80)
{
SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
}
else if(pattrib->bwmode == CHANNEL_WIDTH_40)
{
if(pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
SCSettingOfDesc = VHT_DATA_SC_40_LOWER_OF_80MHZ;
else if(pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
SCSettingOfDesc = VHT_DATA_SC_40_UPPER_OF_80MHZ;
else
RTW_INFO("SCMapping: DONOT CARE Mode Setting\n");
}
else
{
if((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
SCSettingOfDesc = VHT_DATA_SC_20_LOWEST_OF_80MHZ;
else if((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
SCSettingOfDesc = VHT_DATA_SC_20_LOWER_OF_80MHZ;
else if((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
SCSettingOfDesc = VHT_DATA_SC_20_UPPER_OF_80MHZ;
else if((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
SCSettingOfDesc = VHT_DATA_SC_20_UPPERST_OF_80MHZ;
else
RTW_INFO("SCMapping: DONOT CARE Mode Setting\n");
}
}
else if(pHalData->current_channel_bw== CHANNEL_WIDTH_40)
{
//RTW_INFO("SCMapping: HT Case: pHalData->current_channel_bw %d, pHalData->nCur40MhzPrimeSC %d \n",pHalData->current_channel_bw,pHalData->nCur40MhzPrimeSC);
if(pattrib->bwmode == CHANNEL_WIDTH_40)
{
SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
}
else if(pattrib->bwmode == CHANNEL_WIDTH_20)
{
if(pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
{
SCSettingOfDesc = VHT_DATA_SC_20_UPPER_OF_80MHZ;
}
else if(pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
{
SCSettingOfDesc = VHT_DATA_SC_20_LOWER_OF_80MHZ;
}
else
{
SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
}
}
}
else
{
SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
}
return SCSettingOfDesc;
}
void rtl8814a_fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, u8 *ptxdesc)
{
//RTW_INFO("bwmode=%d, ch_off=%d\n", pattrib->bwmode, pattrib->ch_offset);
if(pattrib->ht_en)
{
// Set Bandwidth and sub-channel settings.
SET_TX_DESC_DATA_BW_8814A(ptxdesc, BWMapping_8814(padapter,pattrib));
SET_TX_DESC_DATA_SC_8814A(ptxdesc, SCMapping_8814(padapter,pattrib));
}
}

147
hal/rtl8814a/usb/rtl8814au_led.c 100644
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@ -0,0 +1,147 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#define _RTL8814AU_LED_C_
//#include <drv_types.h>
#include <rtl8814a_hal.h>
#ifdef CONFIG_RTW_SW_LED
//================================================================================
// LED object.
//================================================================================
//================================================================================
// Prototype of protected function.
//================================================================================
//================================================================================
// LED_819xUsb routines.
//================================================================================
//
// Description:
// Turn on LED according to LedPin specified.
//
static void
SwLedOn_8814AU(
PADAPTER padapter,
PLED_USB pLed
)
{
u32 LedGpioCfg;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
if (RTW_CANNOT_RUN(padapter))
return;
LedGpioCfg = rtw_read32(padapter , REG_GPIO_PIN_CTRL_2); /* 0x60. In 8814AU, the name should be REG_GPIO_EXT_CTRL */
switch (pLed->LedPin) {
case LED_PIN_LED0:
LedGpioCfg |= (BIT16 | BIT17 | BIT21 | BIT22); /* config as gpo */
LedGpioCfg &= ~(BIT8 | BIT9 | BIT13 | BIT14); /* set gpo value */
LedGpioCfg &= ~(BIT0 | BIT1 | BIT5 | BIT6); /* set gpi value. TBD: may not need this */
rtw_write32(padapter , REG_GPIO_PIN_CTRL_2 , LedGpioCfg);
break;
default:
break;
}
pLed->bLedOn = _TRUE;
}
//
// Description:
// Turn off LED according to LedPin specified.
//
static void
SwLedOff_8814AU(
PADAPTER padapter,
PLED_USB pLed
)
{
u32 LedGpioCfg;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
if (RTW_CANNOT_RUN(padapter))
return;
LedGpioCfg = rtw_read32(padapter , REG_GPIO_PIN_CTRL_2); /* 0x60. In 8814AU, the name should be REG_GPIO_EXT_CTRL */
switch (pLed->LedPin) {
case LED_PIN_LED0:
LedGpioCfg |= (BIT16 | BIT17 | BIT21 | BIT22); /* config as gpo */
LedGpioCfg |= (BIT8 | BIT9 | BIT13 | BIT14); /* set gpo output value */
rtw_write32(padapter , REG_GPIO_PIN_CTRL_2 , LedGpioCfg);
break;
default:
break;
}
pLed->bLedOn = _FALSE;
}
//================================================================================
// Interface to manipulate LED objects.
//================================================================================
//================================================================================
// Default LED behavior.
//================================================================================
//
// Description:
// Initialize all LED_871x objects.
//
void
rtl8814au_InitSwLeds(
_adapter *padapter
)
{
struct led_priv *pledpriv = adapter_to_led(padapter);
pledpriv->LedControlHandler = LedControlUSB;
pledpriv->SwLedOn = SwLedOn_8814AU;
pledpriv->SwLedOff = SwLedOff_8814AU;
InitLed(padapter, &(pledpriv->SwLed0), LED_PIN_LED0);
InitLed(padapter, &(pledpriv->SwLed1), LED_PIN_LED1);
InitLed(padapter, &(pledpriv->SwLed2), LED_PIN_LED2);
}
//
// Description:
// DeInitialize all LED_819xUsb objects.
//
void
rtl8814au_DeInitSwLeds(
_adapter *padapter
)
{
struct led_priv *ledpriv = adapter_to_led(padapter);
DeInitLed( &(ledpriv->SwLed0) );
DeInitLed( &(ledpriv->SwLed1) );
DeInitLed( &(ledpriv->SwLed2) );
}
#endif

34
hal/rtl8814a/usb/rtl8814au_recv.c 100644
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@ -0,0 +1,34 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#define _RTL8814AU_RECV_C_
//#include <drv_types.h>
#include <rtl8814a_hal.h>
int rtl8814au_init_recv_priv(_adapter *padapter)
{
return usb_init_recv_priv(padapter, INTERRUPT_MSG_FORMAT_LEN);
}
void rtl8814au_free_recv_priv(_adapter *padapter)
{
usb_free_recv_priv(padapter, INTERRUPT_MSG_FORMAT_LEN);
}

1121
hal/rtl8814a/usb/rtl8814au_xmit.c 100644
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File diff suppressed because it is too large Load Diff

2416
hal/rtl8814a/usb/usb_halinit.c 100644
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File diff suppressed because it is too large Load Diff

314
hal/rtl8814a/usb/usb_ops_linux.c 100644
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@ -0,0 +1,314 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2017 Realtek Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*****************************************************************************/
#define _HCI_OPS_OS_C_
/* #include <drv_types.h> */
#include <rtl8814a_hal.h>
#ifdef CONFIG_SUPPORT_USB_INT
void interrupt_handler_8814au(_adapter *padapter, u16 pkt_len, u8 *pbuf)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
struct reportpwrstate_parm pwr_rpt;
if (pkt_len != INTERRUPT_MSG_FORMAT_LEN) {
RTW_INFO("%s Invalid interrupt content length (%d)!\n", __FUNCTION__, pkt_len);
return ;
}
/* HISR */
_rtw_memcpy(&(pHalData->IntArray[0]), &(pbuf[USB_INTR_CONTENT_HISR_OFFSET]), 4);
_rtw_memcpy(&(pHalData->IntArray[1]), &(pbuf[USB_INTR_CONTENT_HISRE_OFFSET]), 4);
#if 0 /*DBG*/
{
u32 hisr = 0 , hisr_ex = 0;
_rtw_memcpy(&hisr, &(pHalData->IntArray[0]), 4);
hisr = le32_to_cpu(hisr);
_rtw_memcpy(&hisr_ex, &(pHalData->IntArray[1]), 4);
hisr_ex = le32_to_cpu(hisr_ex);
if ((hisr != 0) || (hisr_ex != 0))
RTW_INFO("===> %s hisr:0x%08x ,hisr_ex:0x%08x\n", __FUNCTION__, hisr, hisr_ex);
}
#endif
#ifdef CONFIG_LPS_LCLK
if (pHalData->IntArray[0] & IMR_CPWM_88E) {
_rtw_memcpy(&pwr_rpt.state, &(pbuf[USB_INTR_CONTENT_CPWM1_OFFSET]), 1);
/* _rtw_memcpy(&pwr_rpt.state2, &(pbuf[USB_INTR_CONTENT_CPWM2_OFFSET]), 1); */
/* 88e's cpwm value only change BIT0, so driver need to add PS_STATE_S2 for LPS flow. */
pwr_rpt.state |= PS_STATE_S2;
_set_workitem(&(adapter_to_pwrctl(padapter)->cpwm_event));
}
#endif/* CONFIG_LPS_LCLK */
#ifdef CONFIG_INTERRUPT_BASED_TXBCN
#ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
if (pHalData->IntArray[0] & IMR_BCNDMAINT0_88E)
#endif
#ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
if (pHalData->IntArray[0] & (IMR_TBDER_88E | IMR_TBDOK_88E))
#endif
{
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
#if 0
if (pHalData->IntArray[0] & IMR_BCNDMAINT0_88E)
RTW_INFO("%s: HISR_BCNERLY_INT\n", __func__);
if (pHalData->IntArray[0] & IMR_TBDOK_88E)
RTW_INFO("%s: HISR_TXBCNOK\n", __func__);
if (pHalData->IntArray[0] & IMR_TBDER_88E)
RTW_INFO("%s: HISR_TXBCNERR\n", __func__);
#endif /* 0 */
if(check_fwstate(pmlmepriv, WIFI_AP_STATE))
{
//send_beacon(padapter);
if(pmlmepriv->update_bcn == _TRUE)
{
//tx_beacon_hdl(padapter, NULL);
set_tx_beacon_cmd(padapter);
}
}
#ifdef CONFIG_CONCURRENT_MODE
if(check_buddy_fwstate(padapter, WIFI_AP_STATE))
{
//send_beacon(padapter);
if(padapter->pbuddy_adapter->mlmepriv.update_bcn == _TRUE)
{
//tx_beacon_hdl(padapter, NULL);
set_tx_beacon_cmd(padapter->pbuddy_adapter);
}
}
#endif
}
#endif /* CONFIG_INTERRUPT_BASED_TXBCN */
#ifdef DBG_CONFIG_ERROR_DETECT_INT
if (pHalData->IntArray[1] & IMR_TXERR_88E)
RTW_INFO("===> %s Tx Error Flag Interrupt Status\n", __FUNCTION__);
if (pHalData->IntArray[1] & IMR_RXERR_88E)
RTW_INFO("===> %s Rx Error Flag INT Status\n", __FUNCTION__);
if (pHalData->IntArray[1] & IMR_TXFOVW_88E)
RTW_INFO("===> %s Transmit FIFO Overflow\n", __FUNCTION__);
if (pHalData->IntArray[1] & IMR_RXFOVW_88E)
RTW_INFO("===> %s Receive FIFO Overflow\n", __FUNCTION__);
#endif/* DBG_CONFIG_ERROR_DETECT_INT */
#ifdef CONFIG_FW_C2H_REG
/* C2H Event */
if (pbuf[0] != 0)
usb_c2h_hisr_hdl(padapter, pbuf);
#endif
}
#endif /* CONFIG_SUPPORT_USB_INT */
#if 0
int recvbuf2recvframe(PADAPTER padapter, void *ptr)
{
u8 *pbuf;
u8 pkt_cnt = 0;
u32 pkt_offset;
s32 transfer_len;
u8 *pphy_status = NULL;
union recv_frame *precvframe = NULL;
struct rx_pkt_attrib *pattrib = NULL;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
struct recv_priv *precvpriv = &padapter->recvpriv;
_queue *pfree_recv_queue = &precvpriv->free_recv_queue;
_pkt *pskb;
#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX
pskb = NULL;
transfer_len = (s32)((struct recv_buf *)ptr)->transfer_len;
pbuf = ((struct recv_buf *)ptr)->pbuf;
#else
pskb = (_pkt *)ptr;
transfer_len = (s32)pskb->len;
pbuf = pskb->data;
#endif/* CONFIG_USE_USB_BUFFER_ALLOC_RX */
#ifdef CONFIG_USB_RX_AGGREGATION
pkt_cnt = GET_RX_STATUS_DESC_DMA_AGG_NUM_8814A(pbuf);
#endif
do {
precvframe = rtw_alloc_recvframe(pfree_recv_queue);
if (precvframe == NULL) {
RTW_INFO("%s()-%d: rtw_alloc_recvframe() failed! RX Drop!\n", __FUNCTION__, __LINE__);
goto _exit_recvbuf2recvframe;
}
_rtw_init_listhead(&precvframe->u.hdr.list);
precvframe->u.hdr.precvbuf = NULL; /* can't access the precvbuf for new arch. */
precvframe->u.hdr.len = 0;
rtl8814_query_rx_desc_status(precvframe, pbuf);
pattrib = &precvframe->u.hdr.attrib;
if ((padapter->registrypriv.mp_mode == 0) && ((pattrib->crc_err) || (pattrib->icv_err))) {
RTW_INFO("%s: RX Warning! crc_err=%d icv_err=%d, skip!\n", __FUNCTION__, pattrib->crc_err, pattrib->icv_err);
rtw_free_recvframe(precvframe, pfree_recv_queue);
goto _exit_recvbuf2recvframe;
}
pkt_offset = RXDESC_SIZE + pattrib->drvinfo_sz + pattrib->shift_sz + pattrib->pkt_len;
if ((pattrib->pkt_len <= 0) || (pkt_offset > transfer_len)) {
RTW_INFO("%s()-%d: RX Warning!,pkt_len<=0 or pkt_offset> transfer_len\n", __FUNCTION__, __LINE__);
rtw_free_recvframe(precvframe, pfree_recv_queue);
goto _exit_recvbuf2recvframe;
}
#ifdef CONFIG_RX_PACKET_APPEND_FCS
if(pattrib->pkt_rpt_type == NORMAL_RX)
pattrib->pkt_len -= IEEE80211_FCS_LEN;
#endif
if (rtw_os_alloc_recvframe(padapter, precvframe,
(pbuf + pattrib->shift_sz + pattrib->drvinfo_sz + RXDESC_SIZE), pskb) == _FAIL) {
rtw_free_recvframe(precvframe, pfree_recv_queue);
goto _exit_recvbuf2recvframe;
}
recvframe_put(precvframe, pattrib->pkt_len);
/* recvframe_pull(precvframe, drvinfo_sz + RXDESC_SIZE); */
if(pattrib->pkt_rpt_type == NORMAL_RX)//Normal rx packet
{
if(pattrib->physt)
pphy_status = (pbuf + RXDESC_OFFSET);
#ifdef CONFIG_CONCURRENT_MODE
if(rtw_buddy_adapter_up(padapter))
{
if(pre_recv_entry(precvframe, pphy_status) != _SUCCESS)
{
RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,
("recvbuf2recvframe: recv_entry(precvframe) != _SUCCESS\n"));
}
}
#endif //CONFIG_CONCURRENT_MODE
if(pattrib->physt && pphy_status)
rx_query_phy_status(precvframe, pphy_status);
if(rtw_recv_entry(precvframe) != _SUCCESS)
{
RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,
("recvbuf2recvframe: rtw_recv_entry(precvframe) != _SUCCESS\n"));
}
}
else{ // pkt_rpt_type == TX_REPORT1-CCX, TX_REPORT2-TX RTP,HIS_REPORT-USB HISR RTP
if (pattrib->pkt_rpt_type == C2H_PACKET) {
//RTW_INFO("rx C2H_PACKET \n");
rtw_hal_c2h_pkt_pre_hdl(padapter,precvframe->u.hdr.rx_data,pattrib->pkt_len);
}
rtw_free_recvframe(precvframe, pfree_recv_queue);
}
#ifdef CONFIG_USB_RX_AGGREGATION
/* jaguar 8-byte alignment */
pkt_offset = (u16)_RND8(pkt_offset);
pkt_cnt--;
pbuf += pkt_offset;
#endif
transfer_len -= pkt_offset;
precvframe = NULL;
} while (transfer_len > 0);
_exit_recvbuf2recvframe:
return _SUCCESS;
}
#endif
void rtl8814au_xmit_tasklet(void *priv)
{
int ret = _FALSE;
_adapter *padapter = (_adapter*)priv;
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
while(1)
{
if (RTW_CANNOT_TX(padapter))
{
RTW_INFO("xmit_tasklet => bDriverStopped or bSurpriseRemoved or bWritePortCancel\n");
break;
}
if (rtw_xmit_ac_blocked(padapter) == _TRUE)
break;
ret = rtl8814au_xmitframe_complete(padapter, pxmitpriv, NULL);
if(ret==_FALSE)
break;
}
}
void rtl8814au_set_intf_ops(struct _io_ops *pops)
{
_rtw_memset((u8 *)pops, 0, sizeof(struct _io_ops));
pops->_read8 = &usb_read8;
pops->_read16 = &usb_read16;
pops->_read32 = &usb_read32;
pops->_read_mem = &usb_read_mem;
pops->_read_port = &usb_read_port;
pops->_write8 = &usb_write8;
pops->_write16 = &usb_write16;
pops->_write32 = &usb_write32;
pops->_writeN = &usb_writeN;
#ifdef CONFIG_USB_SUPPORT_ASYNC_VDN_REQ
pops->_write8_async= &usb_async_write8;
pops->_write16_async = &usb_async_write16;
pops->_write32_async = &usb_async_write32;
#endif
pops->_write_mem = &usb_write_mem;
pops->_write_port = &usb_write_port;
pops->_read_port_cancel = &usb_read_port_cancel;
pops->_write_port_cancel = &usb_write_port_cancel;
#ifdef CONFIG_USB_INTERRUPT_IN_PIPE
pops->_read_interrupt = &usb_read_interrupt;
#endif
}
void rtl8814au_set_hw_type(struct dvobj_priv *pdvobj)
{
pdvobj->HardwareType = HARDWARE_TYPE_RTL8814AU;
RTW_INFO("CHIP TYPE: RTL8814\n");
}

2
include/hal_data.h
View File

@ -494,6 +494,8 @@ typedef struct hal_com_data {
u8 txpwr_limit_from_file:1;
u8 rf_power_tracking_type;
u8 CurrentTxPwrIdx;
/* Read/write are allow for following hardware information variables */
u8 crystal_cap;

4
include/rtl8814a_hal.h
View File

@ -32,11 +32,11 @@
#ifdef DBG_CONFIG_ERROR_DETECT
#include "rtl8814a_sreset.h"
#endif /* DBG_CONFIG_ERROR_DETECT */
/*
enum {
VOLTAGE_V25 = 0x03,
LDOE25_SHIFT = 28 ,
};
};*/
/* max. iram is 64k , max dmen is 32k. Total = 96k = 0x18000*/
#define FW_SIZE 0x18000
#define FW_START_ADDRESS 0x1000

8
include/rtl8814a_spec.h
View File

@ -645,4 +645,12 @@ So the following defines for 92C is not entire!!!!!!
#define LAST_ENTRY_OF_TX_PKT_BUFFER_8814A (2048-1) /* 20130415 KaiYuan add for 8814 */
#define MACID_NUM_8814A 128
#define SEC_CAM_ENT_NUM_8814A 64
#define HW_PORT_NUM_8814A 5
#define NSS_NUM_8814A 3
#define BAND_CAP_8814A (BAND_CAP_2G | BAND_CAP_5G)
#define BW_CAP_8814A (BW_CAP_20M | BW_CAP_40M | BW_CAP_80M)
#define PROTO_CAP_8814A (PROTO_CAP_11B | PROTO_CAP_11G | PROTO_CAP_11N | PROTO_CAP_11AC)
#endif /* __RTL8814A_SPEC_H__ */

31
os_dep/linux/ioctl_cfg80211.c
View File

@ -9220,12 +9220,12 @@ static void rtw_cfg80211_init_ht_capab_ex(_adapter *padapter
case RF_2T2R:
case RF_1T2R:
ht_cap->cap |= IEEE80211_HT_CAP_RX_STBC_1R;/* Only one spatial-stream STBC RX is supported */
ht_cap->cap |= IEEE80211_HT_CAP_RX_STBC_2R;/* Only one spatial-stream STBC RX is supported */
break;
case RF_3T3R:
case RF_3T4R:
case RF_4T4R:
ht_cap->cap |= IEEE80211_HT_CAP_RX_STBC_1R;/* Only one spatial-stream STBC RX is supported */
ht_cap->cap |= IEEE80211_HT_CAP_RX_STBC_3R;/* Only one spatial-stream STBC RX is supported */
break;
default:
RTW_INFO("[warning] rf_type %d is not expected\n", rf_type);
@ -9413,6 +9413,8 @@ static void rtw_cfg80211_preinit_wiphy(_adapter *adapter, struct wiphy *wiphy)
{
struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
struct registry_priv *regsty = dvobj_to_regsty(dvobj);
struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
struct ieee80211_supported_band *band;
wiphy->signal_type = CFG80211_SIGNAL_TYPE_MBM;
@ -9552,6 +9554,31 @@ static void rtw_cfg80211_preinit_wiphy(_adapter *adapter, struct wiphy *wiphy)
#if (KERNEL_VERSION(3, 8, 0) <= LINUX_VERSION_CODE)
wiphy->features |= NL80211_FEATURE_SAE;
#endif
wiphy->available_antennas_tx = hal_spec->tx_nss_num;
wiphy->available_antennas_rx = hal_spec->rx_nss_num;
if (IsSupported24G(adapter->registrypriv.wireless_mode)) {
band = wiphy->bands[NL80211_BAND_2GHZ];
if (band) {
#if defined(CONFIG_80211N_HT)
rtw_cfg80211_init_ht_capab(adapter, &band->ht_cap, BAND_ON_2_4G, RF_1T1R);
#endif
}
}
#ifdef CONFIG_IEEE80211_BAND_5GHZ
if (is_supported_5g(adapter->registrypriv.wireless_mode)) {
band = wiphy->bands[NL80211_BAND_5GHZ];
if (band) {
#if defined(CONFIG_80211N_HT)
rtw_cfg80211_init_ht_capab(adapter, &band->ht_cap, BAND_ON_5G, RF_1T1R);
#endif
#if defined(CONFIG_80211AC_VHT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0))
rtw_cfg80211_init_vht_capab(adapter, &band->vht_cap, BAND_ON_5G, RF_1T1R);
#endif
}
}
#endif
}
#ifdef CONFIG_RFKILL_POLL

10260
os_dep/linux/ioctl_cfg80211.c.orig 100644
View File

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