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This repository has been archived on
2025-09-02
. You can view files and clone it, but cannot push or open issues or pull requests.
Files
9575a7638a8cab5772d5b536aead42a990a05222
ryujinx
/
ARMeilleure
/
IntermediateRepresentation
History
FICTURE7
8b3eba7e13
Reduce allocation during SSA construction (
#2162
)
...
* Reduce allocation during SSA construction * Re-trigger CI
2021-04-02 19:26:16 +02:00
..
BasicBlock.cs
…
BasicBlockFrequency.cs
…
Comparison.cs
…
IIntrusiveListNode.cs
…
Instruction.cs
Relax block ordering constraints (
#1535
)
2020-09-12 12:32:53 -03:00
Intrinsic.cs
CPU (A64): Add Fmaxnmp & Fminnmp Scalar Inst.s, Fast & Slow Paths; with Tests. (
#1894
)
2021-01-20 09:12:33 +11:00
IntrinsicOperation.cs
Add a new JIT compiler for CPU code (
#693
)
2019-08-08 21:56:22 +03:00
IntrusiveList.cs
Replace LinkedList by IntrusiveList to avoid allocations on JIT (
#931
)
2020-02-17 22:30:54 +01:00
MemoryOperand.cs
…
Multiplier.cs
…
Node.cs
…
Operand.cs
Reduce allocation during SSA construction (
#2162
)
2021-04-02 19:26:16 +02:00
OperandHelper.cs
…
OperandKind.cs
Add a new JIT compiler for CPU code (
#693
)
2019-08-08 21:56:22 +03:00
OperandType.cs
…
Operation.cs
…
OperationHelper.cs
…
PhiNode.cs
Add a new JIT compiler for CPU code (
#693
)
2019-08-08 21:56:22 +03:00
Register.cs
…
RegisterType.cs
Add most of the A32 instruction set to ARMeilleure (
#897
)
2020-02-24 08:20:40 +11:00