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merryandGitHub 6dfb6ccf8c PreAllocator: Check if instruction supports a Vex prefix in IsVexSameOperandDestSrc1 (#3587)

2022-08-14 17:35:08 -03:00

..

CodeGen

PreAllocator: Check if instruction supports a Vex prefix in IsVexSameOperandDestSrc1 (#3587)

2022-08-14 17:35:08 -03:00

Common

Optimize LSRA (#2563)

2021-10-08 18:15:44 -03:00

Decoders

Implement Arm32 Sha256 and MRS Rd, CPSR instructions (#3544)

2022-08-05 19:03:50 +02:00

Diagnostics

Add an early TailMerge pass (#2721)

2021-10-18 19:51:22 -03:00

Instructions

Implement Arm32 Sha256 and MRS Rd, CPSR instructions (#3544)

2022-08-05 19:03:50 +02:00

IntermediateRepresentation

Extend uses count from ushort to uint on Operand Data structure (#3374)

2022-06-05 14:15:27 -03:00

Memory

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Signal

Move partial unmap handler to the native signal handler (#3437)

2022-07-29 19:16:29 -03:00

State

Refactor CPU interface to allow the implementation of other CPU emulators (#3362)

2022-05-31 16:29:35 -03:00

Translation

Implement CPU FCVT Half <-> Double conversion variants (#3439)

2022-07-06 13:40:31 +02:00

Allocators.cs

Optimize LSRA (#2563)

2021-10-08 18:15:44 -03:00

ARMeilleure.csproj

Remove usage of Mono.Posix.NETStandard accross all projects (#2906)

2021-12-08 18:24:26 -03:00

Optimizations.cs

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Statistics.cs

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