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merry df70442c46 InstEmitMemoryEx: Barrier after write on ordered store (#3193) ...

* InstEmitMemoryEx: Barrier after write on ordered store

* increment ptc version

* 32

2022-03-19 10:32:35 -03:00

..

Cache

misc: Migrate usage of RuntimeInformation to OperatingSystem (#2901)

2021-12-04 20:02:30 -03:00

PTC

InstEmitMemoryEx: Barrier after write on ordered store (#3193)

2022-03-19 10:32:35 -03:00

ArmEmitterContext.cs

ARMeilleure: Thumb support (All T16 instructions) (#3105)

2022-02-17 19:39:45 -03:00

Compiler.cs

Add an early TailMerge pass (#2721)

2021-10-18 19:51:22 -03:00

CompilerContext.cs

…

CompilerOptions.cs

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ControlFlowGraph.cs

Add an early TailMerge pass (#2721)

2021-10-18 19:51:22 -03:00

DelegateHelper.cs

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DelegateInfo.cs

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Delegates.cs

Enable CPU JIT cache invalidation (#2965)

2022-02-18 02:53:18 +01:00

DispatcherFunction.cs

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Dominance.cs

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EmitterContext.cs

Add host CPU memory barriers for DMB/DSB and ordered load/store (#3015)

2022-01-21 12:47:34 -03:00

GuestFunction.cs

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IntervalTree.cs

Enable CPU JIT cache invalidation (#2965)

2022-02-18 02:53:18 +01:00

RegisterToLocal.cs

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RegisterUsage.cs

Add an early TailMerge pass (#2721)

2021-10-18 19:51:22 -03:00

RejitRequest.cs

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SsaConstruction.cs

Collapse AsSpan().Slice(..) calls into AsSpan(..) (#3145)

2022-02-22 10:32:10 -03:00

SsaDeconstruction.cs

Reduce JIT GC allocations (#2515)

2021-08-17 15:08:34 -03:00

TranslatedFunction.cs

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Translator.cs

ARMeilleure: Implement single stepping (#3133)

2022-02-22 11:11:42 -03:00

TranslatorCache.cs

Enable CPU JIT cache invalidation (#2965)

2022-02-18 02:53:18 +01:00

TranslatorStubs.cs

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