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317
src/Ryujinx.Tests/Cpu/CpuTestSimdTbl.cs
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317
src/Ryujinx.Tests/Cpu/CpuTestSimdTbl.cs
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#define SimdTbl
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using ARMeilleure.State;
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using NUnit.Framework;
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using System.Collections.Generic;
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namespace Ryujinx.Tests.Cpu
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{
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[Category("SimdTbl")]
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public sealed class CpuTestSimdTbl : CpuTest
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{
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#if SimdTbl
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#region "Helper methods"
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private static ulong GenIdxsForTbls(int regs)
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{
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const byte idxInRngMin = 0;
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byte idxInRngMax = (byte)((16 * regs) - 1);
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byte idxOutRngMin = (byte) (16 * regs);
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const byte idxOutRngMax = 255;
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ulong idxs = 0ul;
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for (int cnt = 1; cnt <= 8; cnt++)
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{
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ulong idxInRng = TestContext.CurrentContext.Random.NextByte(idxInRngMin, idxInRngMax);
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ulong idxOutRng = TestContext.CurrentContext.Random.NextByte(idxOutRngMin, idxOutRngMax);
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ulong idx = TestContext.CurrentContext.Random.NextBool() ? idxInRng : idxOutRng;
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idxs = (idxs << 8) | idx;
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}
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return idxs;
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}
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#endregion
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#region "ValueSource (Types)"
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private static ulong[] _8B_()
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{
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return new[] { 0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
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0x8080808080808080ul, 0xFFFFFFFFFFFFFFFFul };
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}
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private static IEnumerable<ulong> _GenIdxsForTbl1_()
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{
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yield return 0x0000000000000000ul;
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yield return 0x7F7F7F7F7F7F7F7Ful;
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yield return 0x8080808080808080ul;
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yield return 0xFFFFFFFFFFFFFFFFul;
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for (int cnt = 1; cnt <= RndCntIdxs; cnt++)
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{
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yield return GenIdxsForTbls(regs: 1);
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}
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}
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private static IEnumerable<ulong> _GenIdxsForTbl2_()
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{
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yield return 0x0000000000000000ul;
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yield return 0x7F7F7F7F7F7F7F7Ful;
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yield return 0x8080808080808080ul;
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yield return 0xFFFFFFFFFFFFFFFFul;
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for (int cnt = 1; cnt <= RndCntIdxs; cnt++)
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{
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yield return GenIdxsForTbls(regs: 2);
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}
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}
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private static IEnumerable<ulong> _GenIdxsForTbl3_()
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{
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yield return 0x0000000000000000ul;
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yield return 0x7F7F7F7F7F7F7F7Ful;
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yield return 0x8080808080808080ul;
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yield return 0xFFFFFFFFFFFFFFFFul;
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for (int cnt = 1; cnt <= RndCntIdxs; cnt++)
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{
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yield return GenIdxsForTbls(regs: 3);
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}
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}
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private static IEnumerable<ulong> _GenIdxsForTbl4_()
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{
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yield return 0x0000000000000000ul;
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yield return 0x7F7F7F7F7F7F7F7Ful;
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yield return 0x8080808080808080ul;
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yield return 0xFFFFFFFFFFFFFFFFul;
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for (int cnt = 1; cnt <= RndCntIdxs; cnt++)
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{
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yield return GenIdxsForTbls(regs: 4);
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}
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}
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#endregion
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#region "ValueSource (Opcodes)"
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private static uint[] _SingleRegisterTable_V_8B_16B_()
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{
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return new[]
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{
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0x0E000000u, // TBL V0.8B, { V0.16B }, V0.8B
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0x0E001000u // TBX V0.8B, { V0.16B }, V0.8B
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};
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}
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private static uint[] _TwoRegisterTable_V_8B_16B_()
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{
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return new[]
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{
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0x0E002000u, // TBL V0.8B, { V0.16B, V1.16B }, V0.8B
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0x0E003000u // TBX V0.8B, { V0.16B, V1.16B }, V0.8B
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};
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}
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private static uint[] _ThreeRegisterTable_V_8B_16B_()
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{
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return new[]
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{
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0x0E004000u, // TBL V0.8B, { V0.16B, V1.16B, V2.16B }, V0.8B
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0x0E005000u // TBX V0.8B, { V0.16B, V1.16B, V2.16B }, V0.8B
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};
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}
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private static uint[] _FourRegisterTable_V_8B_16B_()
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{
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return new[]
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{
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0x0E006000u, // TBL V0.8B, { V0.16B, V1.16B, V2.16B, V3.16B }, V0.8B
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0x0E006000u // TBX V0.8B, { V0.16B, V1.16B, V2.16B, V3.16B }, V0.8B
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};
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}
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#endregion
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private const int RndCntIdxs = 2;
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[Test, Pairwise]
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public void SingleRegisterTable_V_8B_16B([ValueSource(nameof(_SingleRegisterTable_V_8B_16B_))] uint opcodes,
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[Values(0u)] uint rd,
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[Values(1u)] uint rn,
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[Values(2u)] uint rm,
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[ValueSource(nameof(_8B_))] ulong z,
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[ValueSource(nameof(_8B_))] ulong table0,
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[ValueSource(nameof(_GenIdxsForTbl1_))] ulong indexes,
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[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
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{
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opcodes |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
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opcodes |= ((q & 1) << 30);
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V128 v0 = MakeVectorE0E1(z, z);
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V128 v1 = MakeVectorE0E1(table0, table0);
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V128 v2 = MakeVectorE0E1(indexes, q == 1u ? indexes : 0ul);
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SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise]
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public void TwoRegisterTable_V_8B_16B([ValueSource(nameof(_TwoRegisterTable_V_8B_16B_))] uint opcodes,
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[Values(0u)] uint rd,
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[Values(1u)] uint rn,
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[Values(3u)] uint rm,
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[ValueSource(nameof(_8B_))] ulong z,
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[ValueSource(nameof(_8B_))] ulong table0,
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[ValueSource(nameof(_8B_))] ulong table1,
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[ValueSource(nameof(_GenIdxsForTbl2_))] ulong indexes,
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[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
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{
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opcodes |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
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opcodes |= ((q & 1) << 30);
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V128 v0 = MakeVectorE0E1(z, z);
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V128 v1 = MakeVectorE0E1(table0, table0);
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V128 v2 = MakeVectorE0E1(table1, table1);
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V128 v3 = MakeVectorE0E1(indexes, q == 1u ? indexes : 0ul);
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SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2, v3: v3);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise]
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public void Mod_TwoRegisterTable_V_8B_16B([ValueSource(nameof(_TwoRegisterTable_V_8B_16B_))] uint opcodes,
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[Values(30u, 1u)] uint rd,
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[Values(31u)] uint rn,
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[Values(1u, 30u)] uint rm,
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[ValueSource(nameof(_8B_))] ulong z,
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[ValueSource(nameof(_8B_))] ulong table0,
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[ValueSource(nameof(_8B_))] ulong table1,
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[ValueSource(nameof(_GenIdxsForTbl2_))] ulong indexes,
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[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
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{
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opcodes |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
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opcodes |= ((q & 1) << 30);
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V128 v30 = MakeVectorE0E1(z, z);
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V128 v31 = MakeVectorE0E1(table0, table0);
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V128 v0 = MakeVectorE0E1(table1, table1);
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V128 v1 = MakeVectorE0E1(indexes, indexes);
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SingleOpcode(opcodes, v0: v0, v1: v1, v30: v30, v31: v31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise]
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public void ThreeRegisterTable_V_8B_16B([ValueSource(nameof(_ThreeRegisterTable_V_8B_16B_))] uint opcodes,
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[Values(0u)] uint rd,
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[Values(1u)] uint rn,
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[Values(4u)] uint rm,
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[ValueSource(nameof(_8B_))] ulong z,
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[ValueSource(nameof(_8B_))] ulong table0,
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[ValueSource(nameof(_8B_))] ulong table1,
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[ValueSource(nameof(_8B_))] ulong table2,
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[ValueSource(nameof(_GenIdxsForTbl3_))] ulong indexes,
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[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
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{
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opcodes |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
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opcodes |= ((q & 1) << 30);
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V128 v0 = MakeVectorE0E1(z, z);
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V128 v1 = MakeVectorE0E1(table0, table0);
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V128 v2 = MakeVectorE0E1(table1, table1);
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V128 v3 = MakeVectorE0E1(table2, table2);
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V128 v4 = MakeVectorE0E1(indexes, q == 1u ? indexes : 0ul);
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SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2, v3: v3, v4: v4);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise]
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public void Mod_ThreeRegisterTable_V_8B_16B([ValueSource(nameof(_ThreeRegisterTable_V_8B_16B_))] uint opcodes,
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[Values(30u, 2u)] uint rd,
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[Values(31u)] uint rn,
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[Values(2u, 30u)] uint rm,
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[ValueSource(nameof(_8B_))] ulong z,
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[ValueSource(nameof(_8B_))] ulong table0,
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[ValueSource(nameof(_8B_))] ulong table1,
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[ValueSource(nameof(_8B_))] ulong table2,
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[ValueSource(nameof(_GenIdxsForTbl3_))] ulong indexes,
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[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
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{
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opcodes |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
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opcodes |= ((q & 1) << 30);
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V128 v30 = MakeVectorE0E1(z, z);
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V128 v31 = MakeVectorE0E1(table0, table0);
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V128 v0 = MakeVectorE0E1(table1, table1);
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V128 v1 = MakeVectorE0E1(table2, table2);
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V128 v2 = MakeVectorE0E1(indexes, indexes);
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SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2, v30: v30, v31: v31);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise]
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public void FourRegisterTable_V_8B_16B([ValueSource(nameof(_FourRegisterTable_V_8B_16B_))] uint opcodes,
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[Values(0u)] uint rd,
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[Values(1u)] uint rn,
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[Values(5u)] uint rm,
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[ValueSource(nameof(_8B_))] ulong z,
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[ValueSource(nameof(_8B_))] ulong table0,
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[ValueSource(nameof(_8B_))] ulong table1,
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[ValueSource(nameof(_8B_))] ulong table2,
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[ValueSource(nameof(_8B_))] ulong table3,
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[ValueSource(nameof(_GenIdxsForTbl4_))] ulong indexes,
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[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
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{
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opcodes |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
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opcodes |= ((q & 1) << 30);
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V128 v0 = MakeVectorE0E1(z, z);
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V128 v1 = MakeVectorE0E1(table0, table0);
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V128 v2 = MakeVectorE0E1(table1, table1);
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V128 v3 = MakeVectorE0E1(table2, table2);
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V128 v4 = MakeVectorE0E1(table3, table3);
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V128 v5 = MakeVectorE0E1(indexes, q == 1u ? indexes : 0ul);
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SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2, v3: v3, v4: v4, v5: v5);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise]
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public void Mod_FourRegisterTable_V_8B_16B([ValueSource(nameof(_FourRegisterTable_V_8B_16B_))] uint opcodes,
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[Values(30u, 3u)] uint rd,
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[Values(31u)] uint rn,
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[Values(3u, 30u)] uint rm,
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[ValueSource(nameof(_8B_))] ulong z,
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[ValueSource(nameof(_8B_))] ulong table0,
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[ValueSource(nameof(_8B_))] ulong table1,
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[ValueSource(nameof(_8B_))] ulong table2,
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[ValueSource(nameof(_8B_))] ulong table3,
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[ValueSource(nameof(_GenIdxsForTbl4_))] ulong indexes,
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[Values(0b0u, 0b1u)] uint q) // <8B, 16B>
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{
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opcodes |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
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opcodes |= ((q & 1) << 30);
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V128 v30 = MakeVectorE0E1(z, z);
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V128 v31 = MakeVectorE0E1(table0, table0);
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V128 v0 = MakeVectorE0E1(table1, table1);
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V128 v1 = MakeVectorE0E1(table2, table2);
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V128 v2 = MakeVectorE0E1(table3, table3);
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V128 v3 = MakeVectorE0E1(indexes, indexes);
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SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2, v3: v3, v30: v30, v31: v31);
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CompareAgainstUnicorn();
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}
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#endif
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}
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}
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