mirror of
https://github.com/aircrack-ng/rtl8812au.git
synced 2024-11-29 08:27:41 +00:00
453 lines
13 KiB
C
453 lines
13 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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/* ************************************************************
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* include files
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* ************************************************************ */
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#include "mp_precomp.h"
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#include "phydm_precomp.h"
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#define READ_AND_CONFIG_MP(ic, txt) (odm_read_and_config_mp_##ic##txt(p_dm))
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#define READ_AND_CONFIG READ_AND_CONFIG_MP
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#define GET_VERSION_MP(ic, txt) (odm_get_version_mp_##ic##txt())
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#define GET_VERSION_TC(ic, txt) (odm_get_version_tc_##ic##txt())
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#define GET_VERSION(ic, txt) GET_VERSION_MP(ic, txt)
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enum hal_status
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odm_config_rf_with_header_file(
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struct PHY_DM_STRUCT *p_dm,
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enum odm_rf_config_type config_type,
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u8 e_rf_path
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)
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{
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#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
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struct _ADAPTER *adapter = p_dm->adapter;
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PMGNT_INFO p_mgnt_info = &(adapter->MgntInfo);
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#endif
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enum hal_status result = HAL_STATUS_SUCCESS;
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PHYDM_DBG(p_dm, ODM_COMP_INIT,
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("===>odm_config_rf_with_header_file (%s)\n", (p_dm->is_mp_chip) ? "MPChip" : "TestChip"));
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PHYDM_DBG(p_dm, ODM_COMP_INIT,
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("support_platform: 0x%X, support_interface: 0x%X, board_type: 0x%X\n",
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p_dm->support_platform, p_dm->support_interface, p_dm->board_type));
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/* 1 AP doesn't use PHYDM power tracking table in these ICs */
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#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
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#if (RTL8812A_SUPPORT == 1)
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if (p_dm->support_ic_type == ODM_RTL8812) {
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if (config_type == CONFIG_RF_RADIO) {
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if (e_rf_path == RF_PATH_A)
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READ_AND_CONFIG_MP(8812a, _radioa);
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else if (e_rf_path == RF_PATH_B)
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READ_AND_CONFIG_MP(8812a, _radiob);
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} else if (config_type == CONFIG_RF_TXPWR_LMT) {
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#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) && (DEV_BUS_TYPE == RT_PCI_INTERFACE)
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HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
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if ((p_hal_data->EEPROMSVID == 0x17AA && p_hal_data->EEPROMSMID == 0xA811) ||
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(p_hal_data->EEPROMSVID == 0x10EC && p_hal_data->EEPROMSMID == 0xA812) ||
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(p_hal_data->EEPROMSVID == 0x10EC && p_hal_data->EEPROMSMID == 0x8812))
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READ_AND_CONFIG_MP(8812a, _txpwr_lmt_hm812a03);
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else
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#endif
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READ_AND_CONFIG_MP(8812a, _txpwr_lmt);
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}
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}
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#endif
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#if (RTL8821A_SUPPORT == 1)
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if (p_dm->support_ic_type == ODM_RTL8821) {
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if (config_type == CONFIG_RF_RADIO) {
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if (e_rf_path == RF_PATH_A)
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READ_AND_CONFIG_MP(8821a, _radioa);
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} else if (config_type == CONFIG_RF_TXPWR_LMT) {
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if (p_dm->support_interface == ODM_ITRF_USB) {
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if (p_dm->ext_pa_5g || p_dm->ext_lna_5g)
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READ_AND_CONFIG_MP(8821a, _txpwr_lmt_8811a_u_fem);
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else
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READ_AND_CONFIG_MP(8821a, _txpwr_lmt_8811a_u_ipa);
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} else {
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#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
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if (p_mgnt_info->CustomerID == RT_CID_8821AE_ASUS_MB)
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READ_AND_CONFIG_MP(8821a, _txpwr_lmt_8821a_sar_8mm);
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else if (p_mgnt_info->CustomerID == RT_CID_ASUS_NB)
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READ_AND_CONFIG_MP(8821a, _txpwr_lmt_8821a_sar_5mm);
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else
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#endif
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READ_AND_CONFIG_MP(8821a, _txpwr_lmt_8821a);
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}
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}
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}
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#endif
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#endif/* (DM_ODM_SUPPORT_TYPE != ODM_AP) */
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/* 1 All platforms support */
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#if (RTL8814A_SUPPORT == 1)
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if (p_dm->support_ic_type == ODM_RTL8814A) {
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if (config_type == CONFIG_RF_RADIO) {
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if (e_rf_path == RF_PATH_A)
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READ_AND_CONFIG_MP(8814a, _radioa);
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else if (e_rf_path == RF_PATH_B)
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READ_AND_CONFIG_MP(8814a, _radiob);
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else if (e_rf_path == RF_PATH_C)
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READ_AND_CONFIG_MP(8814a, _radioc);
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else if (e_rf_path == RF_PATH_D)
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READ_AND_CONFIG_MP(8814a, _radiod);
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} else if (config_type == CONFIG_RF_TXPWR_LMT) {
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READ_AND_CONFIG_MP(8814a,_txpwr_lmt);
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}
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}
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#endif
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if (config_type == CONFIG_RF_RADIO) {
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if (p_dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) {
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result = phydm_set_reg_by_fw(p_dm,
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PHYDM_HALMAC_CMD_END,
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0,
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0,
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0,
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(enum rf_path)0,
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0);
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PHYDM_DBG(p_dm, ODM_COMP_INIT,
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("rf param offload end!result = %d", result));
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}
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}
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return result;
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}
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enum hal_status
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odm_config_rf_with_tx_pwr_track_header_file(
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struct PHY_DM_STRUCT *p_dm
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)
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{
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PHYDM_DBG(p_dm, ODM_COMP_INIT,
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("===>odm_config_rf_with_tx_pwr_track_header_file (%s)\n", (p_dm->is_mp_chip) ? "MPChip" : "TestChip"));
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PHYDM_DBG(p_dm, ODM_COMP_INIT,
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("support_platform: 0x%X, support_interface: 0x%X, board_type: 0x%X\n",
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p_dm->support_platform, p_dm->support_interface, p_dm->board_type));
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/* 1 AP doesn't use PHYDM power tracking table in these ICs */
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#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
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#if RTL8821A_SUPPORT
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if (p_dm->support_ic_type == ODM_RTL8821) {
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if (p_dm->support_interface == ODM_ITRF_PCIE)
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READ_AND_CONFIG_MP(8821a, _txpowertrack_pcie);
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else if (p_dm->support_interface == ODM_ITRF_USB)
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READ_AND_CONFIG_MP(8821a, _txpowertrack_usb);
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else if (p_dm->support_interface == ODM_ITRF_SDIO)
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READ_AND_CONFIG_MP(8821a, _txpowertrack_sdio);
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}
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#endif
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#if RTL8812A_SUPPORT
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if (p_dm->support_ic_type == ODM_RTL8812) {
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if (p_dm->support_interface == ODM_ITRF_PCIE)
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READ_AND_CONFIG_MP(8812a, _txpowertrack_pcie);
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else if (p_dm->support_interface == ODM_ITRF_USB) {
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if (p_dm->rfe_type == 3 && p_dm->is_mp_chip)
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READ_AND_CONFIG_MP(8812a, _txpowertrack_rfe3);
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else
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READ_AND_CONFIG_MP(8812a, _txpowertrack_usb);
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}
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}
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#endif
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#endif/* (DM_ODM_SUPPORT_TYPE != ODM_AP) */
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/* 1 All platforms support */
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#if RTL8814A_SUPPORT
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if (p_dm->support_ic_type == ODM_RTL8814A) {
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if (p_dm->rfe_type == 0)
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READ_AND_CONFIG_MP(8814a, _txpowertrack_type0);
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else if (p_dm->rfe_type == 2)
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READ_AND_CONFIG_MP(8814a, _txpowertrack_type2);
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else if (p_dm->rfe_type == 5)
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READ_AND_CONFIG_MP(8814a, _txpowertrack_type5);
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/*else if (p_dm->rfe_type == 7)
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READ_AND_CONFIG_MP(8814a, _txpowertrack_type7);
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else if (p_dm->rfe_type == 8)
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READ_AND_CONFIG_MP(8814a, _txpowertrack_type8);*/
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else
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READ_AND_CONFIG_MP(8814a, _txpowertrack);
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// READ_AND_CONFIG_MP(8814a, _txpowertssi);
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}
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#endif
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return HAL_STATUS_SUCCESS;
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}
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enum hal_status
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odm_config_bb_with_header_file(
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struct PHY_DM_STRUCT *p_dm,
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enum odm_bb_config_type config_type
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)
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{
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#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
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struct _ADAPTER *adapter = p_dm->adapter;
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PMGNT_INFO p_mgnt_info = &(adapter->MgntInfo);
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#endif
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enum hal_status result = HAL_STATUS_SUCCESS;
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/* 1 AP doesn't use PHYDM initialization in these ICs */
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#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
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#if (RTL8812A_SUPPORT == 1)
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if (p_dm->support_ic_type == ODM_RTL8812) {
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if (config_type == CONFIG_BB_PHY_REG)
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READ_AND_CONFIG_MP(8812a, _phy_reg);
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else if (config_type == CONFIG_BB_AGC_TAB)
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READ_AND_CONFIG_MP(8812a, _agc_tab);
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else if (config_type == CONFIG_BB_PHY_REG_PG) {
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if (p_dm->rfe_type == 3 && p_dm->is_mp_chip)
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READ_AND_CONFIG_MP(8812a, _phy_reg_pg_asus);
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#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
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else if (p_mgnt_info->CustomerID == RT_CID_WNC_NEC && p_dm->is_mp_chip)
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READ_AND_CONFIG_MP(8812a, _phy_reg_pg_nec);
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#if RT_PLATFORM == PLATFORM_MACOSX
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/*{1827}{1024} for BUFFALO power by rate table. Isaiah 2013-11-29*/
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else if (p_mgnt_info->CustomerID == RT_CID_DNI_BUFFALO)
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READ_AND_CONFIG_MP(8812a, _phy_reg_pg_dni);
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/* TP-Link T4UH, Isaiah 2015-03-16*/
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else if (p_mgnt_info->CustomerID == RT_CID_TPLINK_HPWR) {
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dbg_print("RT_CID_TPLINK_HPWR:: _PHY_REG_PG_TPLINK\n");
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READ_AND_CONFIG_MP(8812a, _phy_reg_pg_tplink);
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}
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#endif
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#endif
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else
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READ_AND_CONFIG_MP(8812a, _phy_reg_pg);
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} else if (config_type == CONFIG_BB_PHY_REG_MP)
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READ_AND_CONFIG_MP(8812a, _phy_reg_mp);
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else if (config_type == CONFIG_BB_AGC_TAB_DIFF) {
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p_dm->fw_offload_ability &= ~PHYDM_PHY_PARAM_OFFLOAD;
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/*AGC_TAB DIFF dont support FW offload*/
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if ((*p_dm->p_channel >= 36) && (*p_dm->p_channel <= 64))
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AGC_DIFF_CONFIG_MP(8812a, lb);
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else if (*p_dm->p_channel >= 100)
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AGC_DIFF_CONFIG_MP(8812a, hb);
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}
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}
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#endif
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#if (RTL8821A_SUPPORT == 1)
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if (p_dm->support_ic_type == ODM_RTL8821) {
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if (config_type == CONFIG_BB_PHY_REG)
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READ_AND_CONFIG_MP(8821a, _phy_reg);
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else if (config_type == CONFIG_BB_AGC_TAB)
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READ_AND_CONFIG_MP(8821a, _agc_tab);
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else if (config_type == CONFIG_BB_PHY_REG_PG) {
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#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
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#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
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HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
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if ((p_hal_data->EEPROMSVID == 0x1043 && p_hal_data->EEPROMSMID == 0x207F))
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READ_AND_CONFIG_MP(8821a, _phy_reg_pg_e202_sa);
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else
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#endif
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#if (RT_PLATFORM == PLATFORM_MACOSX)
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/*{1827}{1022} for BUFFALO power by rate table. Isaiah 2013-10-18*/
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if (p_mgnt_info->CustomerID == RT_CID_DNI_BUFFALO) {
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/*{1024} for BUFFALO power by rate table. (JP/US)*/
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if (p_mgnt_info->ChannelPlan == RT_CHANNEL_DOMAIN_US_2G_CANADA_5G)
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READ_AND_CONFIG_MP(8821a, _phy_reg_pg_dni_us);
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else
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READ_AND_CONFIG_MP(8821a, _phy_reg_pg_dni_jp);
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} else
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#endif
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#endif
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READ_AND_CONFIG_MP(8821a, _phy_reg_pg);
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}
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}
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#endif
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#endif/* (DM_ODM_SUPPORT_TYPE != ODM_AP) */
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/* 1 All platforms support */
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#if (RTL8814A_SUPPORT == 1)
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if (p_dm->support_ic_type == ODM_RTL8814A) {
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if (config_type == CONFIG_BB_PHY_REG)
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READ_AND_CONFIG_MP(8814a, _phy_reg);
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else if (config_type == CONFIG_BB_AGC_TAB)
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READ_AND_CONFIG_MP(8814a, _agc_tab);
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else if (config_type == CONFIG_BB_PHY_REG_PG) {
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/*if (p_dm->rfe_type == 0)
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READ_AND_CONFIG_MP(8814a,_phy_reg_pg_type0);
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else if (p_dm->rfe_type == 2)
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READ_AND_CONFIG_MP(8814a,_phy_reg_pg_type2);
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else if (p_dm->rfe_type == 3)
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READ_AND_CONFIG_MP(8814a,_phy_reg_pg_type3);
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else if (p_dm->rfe_type == 4)
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READ_AND_CONFIG_MP(8814a,_phy_reg_pg_type4);
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else if (p_dm->rfe_type == 5)
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READ_AND_CONFIG_MP(8814a,_phy_reg_pg_type5);
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else if (p_dm->rfe_type == 7)
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READ_AND_CONFIG_MP(8814a,_phy_reg_pg_type7);
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else if (p_dm->rfe_type == 8)
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READ_AND_CONFIG_MP(8814a,_phy_reg_pg_type8);
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else*/
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READ_AND_CONFIG_MP(8814a,_phy_reg_pg);
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}
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else if (config_type == CONFIG_BB_PHY_REG_MP)
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READ_AND_CONFIG_MP(8814a, _phy_reg_mp);
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}
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#endif
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if (config_type == CONFIG_BB_PHY_REG || config_type == CONFIG_BB_AGC_TAB)
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if (p_dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) {
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result = phydm_set_reg_by_fw(p_dm,
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PHYDM_HALMAC_CMD_END,
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0,
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0,
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0,
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(enum rf_path)0,
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0);
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PHYDM_DBG(p_dm, ODM_COMP_INIT,
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("phy param offload end!result = %d", result));
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}
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return result;
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}
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enum hal_status
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odm_config_mac_with_header_file(
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struct PHY_DM_STRUCT *p_dm
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)
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{
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enum hal_status result = HAL_STATUS_SUCCESS;
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PHYDM_DBG(p_dm, ODM_COMP_INIT,
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("===>odm_config_mac_with_header_file (%s)\n", (p_dm->is_mp_chip) ? "MPChip" : "TestChip"));
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PHYDM_DBG(p_dm, ODM_COMP_INIT,
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("support_platform: 0x%X, support_interface: 0x%X, board_type: 0x%X\n",
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p_dm->support_platform, p_dm->support_interface, p_dm->board_type));
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/* 1 AP doesn't use PHYDM initialization in these ICs */
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#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
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#if (RTL8812A_SUPPORT == 1)
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if (p_dm->support_ic_type == ODM_RTL8812)
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READ_AND_CONFIG_MP(8812a, _mac_reg);
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#endif
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#if (RTL8821A_SUPPORT == 1)
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if (p_dm->support_ic_type == ODM_RTL8821)
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READ_AND_CONFIG_MP(8821a, _mac_reg);
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#endif
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#endif/* (DM_ODM_SUPPORT_TYPE != ODM_AP) */
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/* 1 All platforms support */
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#if (RTL8814A_SUPPORT == 1)
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if (p_dm->support_ic_type == ODM_RTL8814A)
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READ_AND_CONFIG_MP(8814a, _mac_reg);
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#endif
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if (p_dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) {
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result = phydm_set_reg_by_fw(p_dm,
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PHYDM_HALMAC_CMD_END,
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0,
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0,
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0,
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(enum rf_path)0,
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0);
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PHYDM_DBG(p_dm, ODM_COMP_INIT,
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("mac param offload end!result = %d", result));
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}
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return result;
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}
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u32
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odm_get_hw_img_version(
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struct PHY_DM_STRUCT *p_dm
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)
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{
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u32 version = 0;
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/* 1 AP doesn't use PHYDM initialization in these ICs */
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#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
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#if (RTL8821A_SUPPORT == 1)
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if (p_dm->support_ic_type == ODM_RTL8821)
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version = GET_VERSION_MP(8821a, _mac_reg);
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#endif
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#if (RTL8812A_SUPPORT == 1)
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if (p_dm->support_ic_type == ODM_RTL8812)
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version = GET_VERSION_MP(8812a, _mac_reg);
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#endif
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#endif /* (DM_ODM_SUPPORT_TYPE != ODM_AP) */
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/*1 All platforms support*/
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#if (RTL8814A_SUPPORT == 1)
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if (p_dm->support_ic_type == ODM_RTL8814A)
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version = GET_VERSION_MP(8814a, _mac_reg);
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#endif
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return version;
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}
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u32
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query_phydm_trx_capability(
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struct PHY_DM_STRUCT *p_dm
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)
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{
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u32 value32 = 0xFFFFFFFF;
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|
|
|
return value32;
|
|
}
|
|
|
|
u32
|
|
query_phydm_stbc_capability(
|
|
struct PHY_DM_STRUCT *p_dm
|
|
)
|
|
{
|
|
u32 value32 = 0xFFFFFFFF;
|
|
|
|
return value32;
|
|
}
|
|
|
|
u32
|
|
query_phydm_ldpc_capability(
|
|
struct PHY_DM_STRUCT *p_dm
|
|
)
|
|
{
|
|
u32 value32 = 0xFFFFFFFF;
|
|
|
|
return value32;
|
|
}
|
|
|
|
u32
|
|
query_phydm_txbf_parameters(
|
|
struct PHY_DM_STRUCT *p_dm
|
|
)
|
|
{
|
|
u32 value32 = 0xFFFFFFFF;
|
|
|
|
return value32;
|
|
}
|
|
|
|
u32
|
|
query_phydm_txbf_capability(
|
|
struct PHY_DM_STRUCT *p_dm
|
|
)
|
|
{
|
|
u32 value32 = 0xFFFFFFFF;
|
|
|
|
return value32;
|
|
}
|