mirror of
https://github.com/morrownr/8821cu-20210916.git
synced 2024-11-29 08:38:05 +00:00
704 lines
26 KiB
C
704 lines
26 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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******************************************************************************/
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#ifndef __INC_HALMAC_REG_8197F_H
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#define __INC_HALMAC_REG_8197F_H
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#define REG_SYS_ISO_CTRL_8197F 0x0000
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#define REG_SYS_FUNC_EN_8197F 0x0002
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#define REG_SYS_PW_CTRL_8197F 0x0004
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#define REG_SYS_CLK_CTRL_8197F 0x0008
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#define REG_SYS_EEPROM_CTRL_8197F 0x000A
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#define REG_EE_VPD_8197F 0x000C
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#define REG_SYS_SWR_CTRL1_8197F 0x0010
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#define REG_SYS_SWR_CTRL2_8197F 0x0014
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#define REG_SYS_SWR_CTRL3_8197F 0x0018
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#define REG_RSV_CTRL_8197F 0x001C
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#define REG_RF0_CTRL_8197F 0x001F
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#define REG_AFE_LDO_CTRL_8197F 0x0020
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#define REG_AFE_CTRL1_8197F 0x0024
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#define REG_AFE_CTRL2_8197F 0x0028
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#define REG_AFE_CTRL3_8197F 0x002C
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#define REG_EFUSE_CTRL_8197F 0x0030
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#define REG_LDO_EFUSE_CTRL_8197F 0x0034
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#define REG_PWR_OPTION_CTRL_8197F 0x0038
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#define REG_CAL_TIMER_8197F 0x003C
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#define REG_ACLK_MON_8197F 0x003E
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#define REG_GPIO_MUXCFG_8197F 0x0040
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#define REG_GPIO_PIN_CTRL_8197F 0x0044
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#define REG_GPIO_INTM_8197F 0x0048
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#define REG_LED_CFG_8197F 0x004C
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#define REG_FSIMR_8197F 0x0050
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#define REG_FSISR_8197F 0x0054
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#define REG_HSIMR_8197F 0x0058
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#define REG_HSISR_8197F 0x005C
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#define REG_GPIO_EXT_CTRL_8197F 0x0060
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#define REG_PAD_CTRL1_8197F 0x0064
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#define REG_WL_BT_PWR_CTRL_8197F 0x0068
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#define REG_SDM_DEBUG_8197F 0x006C
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#define REG_SYS_SDIO_CTRL_8197F 0x0070
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#define REG_HCI_OPT_CTRL_8197F 0x0074
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#define REG_AFE_CTRL4_8197F 0x0078
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#define REG_LDO_SWR_CTRL_8197F 0x007C
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#define REG_MCUFW_CTRL_8197F 0x0080
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#define REG_MCU_TST_CFG_8197F 0x0084
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#define REG_HMEBOX_E0_E1_8197F 0x0088
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#define REG_HMEBOX_E2_E3_8197F 0x008C
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#define REG_WLLPS_CTRL_8197F 0x0090
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#define REG_AFE_CTRL5_8197F 0x0094
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#define REG_GPIO_DEBOUNCE_CTRL_8197F 0x0098
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#define REG_RPWM2_8197F 0x009C
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#define REG_SYSON_FSM_MON_8197F 0x00A0
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#define REG_AFE_CTRL6_8197F 0x00A4
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#define REG_PMC_DBG_CTRL1_8197F 0x00A8
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#define REG_AFE_CTRL7_8197F 0x00AC
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#define REG_HIMR0_8197F 0x00B0
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#define REG_HISR0_8197F 0x00B4
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#define REG_HIMR1_8197F 0x00B8
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#define REG_HISR1_8197F 0x00BC
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#define REG_DBG_PORT_SEL_8197F 0x00C0
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#define REG_PAD_CTRL2_8197F 0x00C4
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#define REG_PMC_DBG_CTRL2_8197F 0x00CC
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#define REG_BIST_CTRL_8197F 0x00D0
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#define REG_BIST_RPT_8197F 0x00D4
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#define REG_MEM_CTRL_8197F 0x00D8
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#define REG_AFE_CTRL8_8197F 0x00DC
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#define REG_USB_SIE_INTF_8197F 0x00E0
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#define REG_PCIE_MIO_INTF_8197F 0x00E4
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#define REG_PCIE_MIO_INTD_8197F 0x00E8
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#define REG_WLRF1_8197F 0x00EC
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#define REG_SYS_CFG1_8197F 0x00F0
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#define REG_SYS_STATUS1_8197F 0x00F4
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#define REG_SYS_STATUS2_8197F 0x00F8
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#define REG_SYS_CFG2_8197F 0x00FC
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#define REG_SYS_CFG3_8197F 0x1000
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#define REG_SYS_CFG4_8197F 0x1034
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#define REG_CPU_DMEM_CON_8197F 0x1080
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#define REG_HIMR2_8197F 0x10B0
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#define REG_HISR2_8197F 0x10B4
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#define REG_HIMR3_8197F 0x10B8
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#define REG_HISR3_8197F 0x10BC
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#define REG_SW_MDIO_8197F 0x10C0
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#define REG_SW_FLUSH_8197F 0x10C4
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#define REG_DBG_GPIO_BMUX_8197F 0x10C8
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#define REG_FPGA_TAG_8197F 0x10CC
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#define REG_WL_DSS_CTRL0_8197F 0x10D0
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#define REG_WL_DSS_CTRL1_8197F 0x10D8
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#define REG_WL_DSS_STATUS1_8197F 0x10DC
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#define REG_FW_DBG0_8197F 0x10E0
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#define REG_FW_DBG1_8197F 0x10E4
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#define REG_FW_DBG2_8197F 0x10E8
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#define REG_FW_DBG3_8197F 0x10EC
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#define REG_FW_DBG4_8197F 0x10F0
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#define REG_FW_DBG5_8197F 0x10F4
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#define REG_FW_DBG6_8197F 0x10F8
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#define REG_FW_DBG7_8197F 0x10FC
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#define REG_CR_8197F 0x0100
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#define REG_TSF_CLK_STATE_8197F 0x0108
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#define REG_TXDMA_PQ_MAP_8197F 0x010C
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#define REG_TRXFF_BNDY_8197F 0x0114
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#define REG_PTA_I2C_MBOX_8197F 0x0118
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#define REG_RXFF_BNDY_8197F 0x011C
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#define REG_FE1IMR_8197F 0x0120
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#define REG_FE1ISR_8197F 0x0124
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#define REG_CPWM_8197F 0x012C
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#define REG_FWIMR_8197F 0x0130
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#define REG_FWISR_8197F 0x0134
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#define REG_FTIMR_8197F 0x0138
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#define REG_FTISR_8197F 0x013C
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#define REG_PKTBUF_DBG_CTRL_8197F 0x0140
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#define REG_PKTBUF_DBG_DATA_L_8197F 0x0144
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#define REG_PKTBUF_DBG_DATA_H_8197F 0x0148
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#define REG_CPWM2_8197F 0x014C
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#define REG_TC0_CTRL_8197F 0x0150
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#define REG_TC1_CTRL_8197F 0x0154
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#define REG_TC2_CTRL_8197F 0x0158
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#define REG_TC3_CTRL_8197F 0x015C
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#define REG_TC4_CTRL_8197F 0x0160
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#define REG_TCUNIT_BASE_8197F 0x0164
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#define REG_TC5_CTRL_8197F 0x0168
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#define REG_TC6_CTRL_8197F 0x016C
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#define REG_MBIST_FAIL_8197F 0x0170
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#define REG_MBIST_START_PAUSE_8197F 0x0174
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#define REG_MBIST_DONE_8197F 0x0178
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#define REG_MBIST_FAIL_NRML_8197F 0x017C
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#define REG_AES_DECRPT_DATA_8197F 0x0180
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#define REG_AES_DECRPT_CFG_8197F 0x0184
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#define REG_MACCLKFRQ_8197F 0x018C
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#define REG_TMETER_8197F 0x0190
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#define REG_OSC_32K_CTRL_8197F 0x0194
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#define REG_32K_CAL_REG1_8197F 0x0198
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#define REG_C2HEVT_8197F 0x01A0
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#define REG_SW_DEFINED_PAGE1_8197F 0x01B8
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#define REG_MCUTST_I_8197F 0x01C0
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#define REG_MCUTST_II_8197F 0x01C4
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#define REG_FMETHR_8197F 0x01C8
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#define REG_HMETFR_8197F 0x01CC
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#define REG_HMEBOX0_8197F 0x01D0
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#define REG_HMEBOX1_8197F 0x01D4
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#define REG_HMEBOX2_8197F 0x01D8
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#define REG_HMEBOX3_8197F 0x01DC
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#define REG_LLT_INIT_8197F 0x01E0
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#define REG_LLT_INIT_ADDR_8197F 0x01E4
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#define REG_BB_ACCESS_CTRL_8197F 0x01E8
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#define REG_BB_ACCESS_DATA_8197F 0x01EC
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#define REG_HMEBOX_E0_8197F 0x01F0
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#define REG_HMEBOX_E1_8197F 0x01F4
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#define REG_HMEBOX_E2_8197F 0x01F8
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#define REG_HMEBOX_E3_8197F 0x01FC
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#define REG_CR_EXT_8197F 0x1100
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#define REG_FWFF_8197F 0x1114
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#define REG_RXFF_PTR_V1_8197F 0x1118
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#define REG_RXFF_WTR_V1_8197F 0x111C
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#define REG_FE2IMR_8197F 0x1120
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#define REG_FE2ISR_8197F 0x1124
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#define REG_FE3IMR_8197F 0x1128
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#define REG_FE3ISR_8197F 0x112C
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#define REG_FE4IMR_8197F 0x1130
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#define REG_FE4ISR_8197F 0x1134
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#define REG_FT1IMR_8197F 0x1138
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#define REG_FT1ISR_8197F 0x113C
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#define REG_SPWR0_8197F 0x1140
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#define REG_SPWR1_8197F 0x1144
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#define REG_SPWR2_8197F 0x1148
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#define REG_SPWR3_8197F 0x114C
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#define REG_POWSEQ_8197F 0x1150
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#define REG_TC7_CTRL_V1_8197F 0x1158
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#define REG_TC8_CTRL_V1_8197F 0x115C
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#define REG_RXBCN_TBTT_INTERVAL_PORT0TO3_8197F 0x1160
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#define REG_RXBCN_TBTT_INTERVAL_PORT4_8197F 0x1164
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#define REG_EXT_QUEUE_REG_8197F 0x11C0
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#define REG_COUNTER_CONTROL_8197F 0x11C4
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#define REG_COUNTER_TH_8197F 0x11C8
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#define REG_COUNTER_SET_8197F 0x11CC
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#define REG_COUNTER_OVERFLOW_8197F 0x11D0
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#define REG_TDE_LEN_TH_8197F 0x11D4
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#define REG_RDE_LEN_TH_8197F 0x11D8
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#define REG_PCIE_EXEC_TIME_8197F 0x11DC
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#define REG_FT2IMR_8197F 0x11E0
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#define REG_FT2ISR_8197F 0x11E4
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#define REG_MSG2_8197F 0x11F0
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#define REG_MSG3_8197F 0x11F4
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#define REG_MSG4_8197F 0x11F8
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#define REG_MSG5_8197F 0x11FC
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#define REG_FIFOPAGE_CTRL_1_8197F 0x0200
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#define REG_FIFOPAGE_CTRL_2_8197F 0x0204
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#define REG_AUTO_LLT_V1_8197F 0x0208
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#define REG_TXDMA_OFFSET_CHK_8197F 0x020C
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#define REG_TXDMA_STATUS_8197F 0x0210
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#define REG_TX_DMA_DBG_8197F 0x0214
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#define REG_TQPNT1_8197F 0x0218
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#define REG_TQPNT2_8197F 0x021C
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#define REG_TQPNT3_8197F 0x0220
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#define REG_TQPNT4_8197F 0x0224
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#define REG_RQPN_CTRL_1_8197F 0x0228
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#define REG_RQPN_CTRL_2_8197F 0x022C
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#define REG_FIFOPAGE_INFO_1_8197F 0x0230
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#define REG_FIFOPAGE_INFO_2_8197F 0x0234
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#define REG_FIFOPAGE_INFO_3_8197F 0x0238
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#define REG_FIFOPAGE_INFO_4_8197F 0x023C
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#define REG_FIFOPAGE_INFO_5_8197F 0x0240
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#define REG_H2C_HEAD_8197F 0x0244
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#define REG_H2C_TAIL_8197F 0x0248
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#define REG_H2C_READ_ADDR_8197F 0x024C
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#define REG_H2C_WR_ADDR_8197F 0x0250
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#define REG_H2C_INFO_8197F 0x0254
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#define REG_RXDMA_AGG_PG_TH_8197F 0x0280
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#define REG_RXPKT_NUM_8197F 0x0284
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#define REG_RXDMA_STATUS_8197F 0x0288
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#define REG_RXDMA_DPR_8197F 0x028C
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#define REG_RXDMA_MODE_8197F 0x0290
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#define REG_C2H_PKT_8197F 0x0294
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#define REG_FWFF_C2H_8197F 0x0298
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#define REG_FWFF_CTRL_8197F 0x029C
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#define REG_FWFF_PKT_INFO_8197F 0x02A0
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#define REG_FC2H_INFO_8197F 0x02A4
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#define REG_DDMA_CH0SA_8197F 0x1200
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#define REG_DDMA_CH0DA_8197F 0x1204
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#define REG_DDMA_CH0CTRL_8197F 0x1208
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#define REG_DDMA_CH1SA_8197F 0x1210
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#define REG_DDMA_CH1DA_8197F 0x1214
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#define REG_DDMA_CH1CTRL_8197F 0x1218
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#define REG_DDMA_CH2SA_8197F 0x1220
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#define REG_DDMA_CH2DA_8197F 0x1224
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#define REG_DDMA_CH2CTRL_8197F 0x1228
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#define REG_DDMA_CH3SA_8197F 0x1230
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#define REG_DDMA_CH3DA_8197F 0x1234
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#define REG_DDMA_CH3CTRL_8197F 0x1238
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#define REG_DDMA_CH4SA_8197F 0x1240
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#define REG_DDMA_CH4DA_8197F 0x1244
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#define REG_DDMA_CH4CTRL_8197F 0x1248
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#define REG_DDMA_CH5SA_8197F 0x1250
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#define REG_DDMA_CH5DA_8197F 0x1254
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#define REG_REG_DDMA_CH5CTRL_8197F 0x1258
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#define REG_DDMA_INT_MSK_8197F 0x12E0
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#define REG_DDMA_CHSTATUS_8197F 0x12E8
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#define REG_DDMA_CHKSUM_8197F 0x12F0
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#define REG_DDMA_MONITOR_8197F 0x12FC
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#define REG_HCI_CTRL_8197F 0x0300
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#define REG_INT_MIG_8197F 0x0304
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#define REG_BCNQ_TXBD_DESA_8197F 0x0308
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#define REG_MGQ_TXBD_DESA_8197F 0x0310
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#define REG_VOQ_TXBD_DESA_8197F 0x0318
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#define REG_VIQ_TXBD_DESA_8197F 0x0320
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#define REG_BEQ_TXBD_DESA_8197F 0x0328
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#define REG_BKQ_TXBD_DESA_8197F 0x0330
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#define REG_RXQ_RXBD_DESA_8197F 0x0338
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#define REG_HI0Q_TXBD_DESA_8197F 0x0340
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#define REG_HI1Q_TXBD_DESA_8197F 0x0348
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#define REG_HI2Q_TXBD_DESA_8197F 0x0350
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#define REG_HI3Q_TXBD_DESA_8197F 0x0358
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#define REG_HI4Q_TXBD_DESA_8197F 0x0360
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#define REG_HI5Q_TXBD_DESA_8197F 0x0368
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#define REG_HI6Q_TXBD_DESA_8197F 0x0370
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#define REG_HI7Q_TXBD_DESA_8197F 0x0378
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#define REG_MGQ_TXBD_NUM_8197F 0x0380
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#define REG_RX_RXBD_NUM_8197F 0x0382
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#define REG_VOQ_TXBD_NUM_8197F 0x0384
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#define REG_VIQ_TXBD_NUM_8197F 0x0386
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#define REG_BEQ_TXBD_NUM_8197F 0x0388
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#define REG_BKQ_TXBD_NUM_8197F 0x038A
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#define REG_HI0Q_TXBD_NUM_8197F 0x038C
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#define REG_HI1Q_TXBD_NUM_8197F 0x038E
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#define REG_HI2Q_TXBD_NUM_8197F 0x0390
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#define REG_HI3Q_TXBD_NUM_8197F 0x0392
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#define REG_HI4Q_TXBD_NUM_8197F 0x0394
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#define REG_HI5Q_TXBD_NUM_8197F 0x0396
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#define REG_HI6Q_TXBD_NUM_8197F 0x0398
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#define REG_HI7Q_TXBD_NUM_8197F 0x039A
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#define REG_TSFTIMER_HCI_8197F 0x039C
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#define REG_BD_RWPTR_CLR_8197F 0x039C
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#define REG_VOQ_TXBD_IDX_8197F 0x03A0
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#define REG_VIQ_TXBD_IDX_8197F 0x03A4
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#define REG_BEQ_TXBD_IDX_8197F 0x03A8
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#define REG_BKQ_TXBD_IDX_8197F 0x03AC
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#define REG_MGQ_TXBD_IDX_8197F 0x03B0
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#define REG_RXQ_RXBD_IDX_8197F 0x03B4
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#define REG_HI0Q_TXBD_IDX_8197F 0x03B8
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#define REG_HI1Q_TXBD_IDX_8197F 0x03BC
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#define REG_HI2Q_TXBD_IDX_8197F 0x03C0
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#define REG_HI3Q_TXBD_IDX_8197F 0x03C4
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#define REG_HI4Q_TXBD_IDX_8197F 0x03C8
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#define REG_HI5Q_TXBD_IDX_8197F 0x03CC
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#define REG_HI6Q_TXBD_IDX_8197F 0x03D0
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#define REG_HI7Q_TXBD_IDX_8197F 0x03D4
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#define REG_DBG_SEL_V1_8197F 0x03D8
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#define REG_HCI_HRPWM1_V1_8197F 0x03D9
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#define REG_HCI_HCPWM1_V1_8197F 0x03DA
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#define REG_HCI_CTRL2_8197F 0x03DB
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#define REG_HCI_HRPWM2_V1_8197F 0x03DC
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#define REG_HCI_HCPWM2_V1_8197F 0x03DE
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#define REG_HCI_H2C_MSG_V1_8197F 0x03E0
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#define REG_HCI_C2H_MSG_V1_8197F 0x03E4
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#define REG_DBI_WDATA_V1_8197F 0x03E8
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#define REG_DBI_RDATA_V1_8197F 0x03EC
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#define REG_STUCK_FLAG_V1_8197F 0x03F0
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#define REG_MDIO_V1_8197F 0x03F4
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#define REG_WDT_CFG_8197F 0x03F8
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#define REG_HCI_MIX_CFG_8197F 0x03FC
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#define REG_STC_INT_CS_8197F 0x1300
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#define REG_ST_INT_CFG_8197F 0x1304
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#define REG_CMU_DLY_CTRL_8197F 0x1310
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#define REG_CMU_DLY_CFG_8197F 0x1314
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#define REG_H2CQ_TXBD_DESA_8197F 0x1320
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#define REG_H2CQ_TXBD_NUM_8197F 0x1328
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#define REG_H2CQ_TXBD_IDX_8197F 0x132C
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#define REG_H2CQ_CSR_8197F 0x1330
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#define REG_AXI_EXCEPT_CS_8197F 0x1350
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#define REG_AXI_EXCEPT_TIME_8197F 0x1354
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#define REG_Q0_INFO_8197F 0x0400
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#define REG_Q1_INFO_8197F 0x0404
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#define REG_Q2_INFO_8197F 0x0408
|
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#define REG_Q3_INFO_8197F 0x040C
|
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#define REG_MGQ_INFO_8197F 0x0410
|
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#define REG_HIQ_INFO_8197F 0x0414
|
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#define REG_BCNQ_INFO_8197F 0x0418
|
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#define REG_TXPKT_EMPTY_8197F 0x041A
|
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#define REG_CPU_MGQ_INFO_8197F 0x041C
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#define REG_FWHW_TXQ_CTRL_8197F 0x0420
|
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#define REG_BCNQ_BDNY_V1_8197F 0x0424
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#define REG_LIFETIME_EN_8197F 0x0426
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#define REG_SPEC_SIFS_8197F 0x0428
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#define REG_RETRY_LIMIT_8197F 0x042A
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#define REG_TXBF_CTRL_8197F 0x042C
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#define REG_DARFRC_8197F 0x0430
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#define REG_RARFRC_8197F 0x0438
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#define REG_RRSR_8197F 0x0440
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#define REG_ARFR0_8197F 0x0444
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#define REG_ARFR1_V1_8197F 0x044C
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#define REG_CCK_CHECK_8197F 0x0454
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#define REG_AMPDU_MAX_TIME_V1_8197F 0x0455
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#define REG_BCNQ1_BDNY_V1_8197F 0x0456
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#define REG_AMPDU_MAX_LENGTH_8197F 0x0458
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#define REG_ACQ_STOP_8197F 0x045C
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#define REG_NDPA_RATE_8197F 0x045D
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#define REG_TX_HANG_CTRL_8197F 0x045E
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#define REG_NDPA_OPT_CTRL_8197F 0x045F
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#define REG_RD_RESP_PKT_TH_8197F 0x0463
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#define REG_CMDQ_INFO_8197F 0x0464
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#define REG_Q4_INFO_8197F 0x0468
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#define REG_Q5_INFO_8197F 0x046C
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|
#define REG_Q6_INFO_8197F 0x0470
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#define REG_Q7_INFO_8197F 0x0474
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#define REG_WMAC_LBK_BUF_HD_V1_8197F 0x0478
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#define REG_MGQ_BDNY_V1_8197F 0x047A
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#define REG_TXRPT_CTRL_8197F 0x047C
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#define REG_INIRTS_RATE_SEL_8197F 0x0480
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#define REG_BASIC_CFEND_RATE_8197F 0x0481
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#define REG_STBC_CFEND_RATE_8197F 0x0482
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#define REG_DATA_SC_8197F 0x0483
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#define REG_MACID_SLEEP3_8197F 0x0484
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|
#define REG_MACID_SLEEP1_8197F 0x0488
|
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#define REG_ARFR2_V1_8197F 0x048C
|
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#define REG_ARFR3_V1_8197F 0x0494
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#define REG_ARFR4_8197F 0x049C
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|
#define REG_ARFR5_8197F 0x04A4
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#define REG_TXRPT_START_OFFSET_8197F 0x04AC
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#define REG_POWER_STAGE1_8197F 0x04B4
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#define REG_POWER_STAGE2_8197F 0x04B8
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#define REG_SW_AMPDU_BURST_MODE_CTRL_8197F 0x04BC
|
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#define REG_PKT_LIFE_TIME_8197F 0x04C0
|
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#define REG_STBC_SETTING_8197F 0x04C4
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#define REG_STBC_SETTING2_8197F 0x04C5
|
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#define REG_QUEUE_CTRL_8197F 0x04C6
|
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#define REG_SINGLE_AMPDU_CTRL_8197F 0x04C7
|
|
#define REG_PROT_MODE_CTRL_8197F 0x04C8
|
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#define REG_BAR_MODE_CTRL_8197F 0x04CC
|
|
#define REG_RA_TRY_RATE_AGG_LMT_8197F 0x04CF
|
|
#define REG_MACID_SLEEP2_8197F 0x04D0
|
|
#define REG_MACID_SLEEP_8197F 0x04D4
|
|
#define REG_HW_SEQ0_8197F 0x04D8
|
|
#define REG_HW_SEQ1_8197F 0x04DA
|
|
#define REG_HW_SEQ2_8197F 0x04DC
|
|
#define REG_HW_SEQ3_8197F 0x04DE
|
|
#define REG_NULL_PKT_STATUS_V1_8197F 0x04E0
|
|
#define REG_PTCL_ERR_STATUS_8197F 0x04E2
|
|
#define REG_NULL_PKT_STATUS_EXTEND_8197F 0x04E3
|
|
#define REG_VIDEO_ENHANCEMENT_FUN_8197F 0x04E4
|
|
#define REG_BT_POLLUTE_PKT_CNT_8197F 0x04E8
|
|
#define REG_PTCL_DBG_8197F 0x04EC
|
|
#define REG_TXOP_EXTRA_CTRL_8197F 0x04F0
|
|
#define REG_CPUMGQ_TIMER_CTRL2_8197F 0x04F4
|
|
#define REG_DUMMY_PAGE4_8197F 0x04FC
|
|
#define REG_Q0_Q1_INFO_8197F 0x1400
|
|
#define REG_Q2_Q3_INFO_8197F 0x1404
|
|
#define REG_Q4_Q5_INFO_8197F 0x1408
|
|
#define REG_Q6_Q7_INFO_8197F 0x140C
|
|
#define REG_MGQ_HIQ_INFO_8197F 0x1410
|
|
#define REG_CMDQ_BCNQ_INFO_8197F 0x1414
|
|
#define REG_USEREG_SETTING_8197F 0x1420
|
|
#define REG_AESIV_SETTING_8197F 0x1424
|
|
#define REG_BF0_TIME_SETTING_8197F 0x1428
|
|
#define REG_BF1_TIME_SETTING_8197F 0x142C
|
|
#define REG_BF_TIMEOUT_EN_8197F 0x1430
|
|
#define REG_MACID_RELEASE0_8197F 0x1434
|
|
#define REG_MACID_RELEASE1_8197F 0x1438
|
|
#define REG_MACID_RELEASE2_8197F 0x143C
|
|
#define REG_MACID_RELEASE3_8197F 0x1440
|
|
#define REG_MACID_RELEASE_SETTING_8197F 0x1444
|
|
#define REG_FAST_EDCA_VOVI_SETTING_8197F 0x1448
|
|
#define REG_FAST_EDCA_BEBK_SETTING_8197F 0x144C
|
|
#define REG_MACID_DROP0_8197F 0x1450
|
|
#define REG_MACID_DROP1_8197F 0x1454
|
|
#define REG_MACID_DROP2_8197F 0x1458
|
|
#define REG_MACID_DROP3_8197F 0x145C
|
|
#define REG_R_MACID_RELEASE_SUCCESS_0_8197F 0x1460
|
|
#define REG_R_MACID_RELEASE_SUCCESS_1_8197F 0x1464
|
|
#define REG_R_MACID_RELEASE_SUCCESS_2_8197F 0x1468
|
|
#define REG_R_MACID_RELEASE_SUCCESS_3_8197F 0x146C
|
|
#define REG_MGG_FIFO_CRTL_8197F 0x1470
|
|
#define REG_MGG_FIFO_INT_8197F 0x1474
|
|
#define REG_MGG_FIFO_LIFETIME_8197F 0x1478
|
|
#define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F 0x147C
|
|
#define REG_SHCUT_SETTING_8197F 0x1480
|
|
#define REG_SHCUT_LLC_ETH_TYPE0_8197F 0x1484
|
|
#define REG_SHCUT_LLC_ETH_TYPE1_8197F 0x1488
|
|
#define REG_SHCUT_LLC_OUI0_8197F 0x148C
|
|
#define REG_SHCUT_LLC_OUI1_8197F 0x1490
|
|
#define REG_SHCUT_LLC_OUI2_8197F 0x1494
|
|
#define REG_SHCUT_LLC_OUI3_8197F 0x1498
|
|
#define REG_CHNL_INFO_CTRL_8197F 0x14D0
|
|
#define REG_CHNL_IDLE_TIME_8197F 0x14D4
|
|
#define REG_CHNL_BUSY_TIME_8197F 0x14D8
|
|
#define REG_EDCA_VO_PARAM_8197F 0x0500
|
|
#define REG_EDCA_VI_PARAM_8197F 0x0504
|
|
#define REG_EDCA_BE_PARAM_8197F 0x0508
|
|
#define REG_EDCA_BK_PARAM_8197F 0x050C
|
|
#define REG_BCNTCFG_8197F 0x0510
|
|
#define REG_PIFS_8197F 0x0512
|
|
#define REG_RDG_PIFS_8197F 0x0513
|
|
#define REG_SIFS_8197F 0x0514
|
|
#define REG_TSFTR_SYN_OFFSET_8197F 0x0518
|
|
#define REG_AGGR_BREAK_TIME_8197F 0x051A
|
|
#define REG_SLOT_8197F 0x051B
|
|
#define REG_TX_PTCL_CTRL_8197F 0x0520
|
|
#define REG_TXPAUSE_8197F 0x0522
|
|
#define REG_DIS_TXREQ_CLR_8197F 0x0523
|
|
#define REG_RD_CTRL_8197F 0x0524
|
|
#define REG_MBSSID_CTRL_8197F 0x0526
|
|
#define REG_P2PPS_CTRL_8197F 0x0527
|
|
#define REG_PKT_LIFETIME_CTRL_8197F 0x0528
|
|
#define REG_P2PPS_SPEC_STATE_8197F 0x052B
|
|
#define REG_QUEUE_INCOL_THR_8197F 0x0538
|
|
#define REG_QUEUE_INCOL_EN_8197F 0x053C
|
|
#define REG_TBTT_PROHIBIT_8197F 0x0540
|
|
#define REG_P2PPS_STATE_8197F 0x0543
|
|
#define REG_RD_NAV_NXT_8197F 0x0544
|
|
#define REG_NAV_PROT_LEN_8197F 0x0546
|
|
#define REG_FTM_CTRL_8197F 0x0548
|
|
#define REG_FTM_TSF_CNT_8197F 0x054C
|
|
#define REG_BCN_CTRL_8197F 0x0550
|
|
#define REG_BCN_CTRL_CLINT0_8197F 0x0551
|
|
#define REG_MBID_NUM_8197F 0x0552
|
|
#define REG_DUAL_TSF_RST_8197F 0x0553
|
|
#define REG_MBSSID_BCN_SPACE_8197F 0x0554
|
|
#define REG_DRVERLYINT_8197F 0x0558
|
|
#define REG_BCNDMATIM_8197F 0x0559
|
|
#define REG_ATIMWND_8197F 0x055A
|
|
#define REG_USTIME_TSF_8197F 0x055C
|
|
#define REG_BCN_MAX_ERR_8197F 0x055D
|
|
#define REG_RXTSF_OFFSET_CCK_8197F 0x055E
|
|
#define REG_RXTSF_OFFSET_OFDM_8197F 0x055F
|
|
#define REG_TSFTR_8197F 0x0560
|
|
#define REG_FREERUN_CNT_8197F 0x0568
|
|
#define REG_ATIMWND1_8197F 0x0570
|
|
#define REG_TBTT_PROHIBIT_INFRA_8197F 0x0571
|
|
#define REG_CTWND_8197F 0x0572
|
|
#define REG_BCNIVLCUNT_8197F 0x0573
|
|
#define REG_BCNDROPCTRL_8197F 0x0574
|
|
#define REG_HGQ_TIMEOUT_PERIOD_8197F 0x0575
|
|
#define REG_TXCMD_TIMEOUT_PERIOD_8197F 0x0576
|
|
#define REG_MISC_CTRL_8197F 0x0577
|
|
#define REG_BCN_CTRL_CLINT1_8197F 0x0578
|
|
#define REG_BCN_CTRL_CLINT2_8197F 0x0579
|
|
#define REG_BCN_CTRL_CLINT3_8197F 0x057A
|
|
#define REG_EXTEND_CTRL_8197F 0x057B
|
|
#define REG_P2PPS1_SPEC_STATE_8197F 0x057C
|
|
#define REG_P2PPS1_STATE_8197F 0x057D
|
|
#define REG_P2PPS2_SPEC_STATE_8197F 0x057E
|
|
#define REG_P2PPS2_STATE_8197F 0x057F
|
|
#define REG_PS_TIMER0_8197F 0x0580
|
|
#define REG_PS_TIMER1_8197F 0x0584
|
|
#define REG_PS_TIMER2_8197F 0x0588
|
|
#define REG_TBTT_CTN_AREA_8197F 0x058C
|
|
#define REG_FORCE_BCN_IFS_8197F 0x058E
|
|
#define REG_TXOP_MIN_8197F 0x0590
|
|
#define REG_PRE_BKF_TIME_8197F 0x0592
|
|
#define REG_CROSS_TXOP_CTRL_8197F 0x0593
|
|
#define REG_TBTT_INT_SHIFT_CLI0_8197F 0x0594
|
|
#define REG_TBTT_INT_SHIFT_CLI1_8197F 0x0595
|
|
#define REG_TBTT_INT_SHIFT_CLI2_8197F 0x0596
|
|
#define REG_TBTT_INT_SHIFT_CLI3_8197F 0x0597
|
|
#define REG_TBTT_INT_SHIFT_ENABLE_8197F 0x0598
|
|
#define REG_ATIMWND2_8197F 0x05A0
|
|
#define REG_ATIMWND3_8197F 0x05A1
|
|
#define REG_ATIMWND4_8197F 0x05A2
|
|
#define REG_ATIMWND5_8197F 0x05A3
|
|
#define REG_ATIMWND6_8197F 0x05A4
|
|
#define REG_ATIMWND7_8197F 0x05A5
|
|
#define REG_ATIMUGT_8197F 0x05A6
|
|
#define REG_HIQ_NO_LMT_EN_8197F 0x05A7
|
|
#define REG_DTIM_COUNTER_ROOT_8197F 0x05A8
|
|
#define REG_DTIM_COUNTER_VAP1_8197F 0x05A9
|
|
#define REG_DTIM_COUNTER_VAP2_8197F 0x05AA
|
|
#define REG_DTIM_COUNTER_VAP3_8197F 0x05AB
|
|
#define REG_DTIM_COUNTER_VAP4_8197F 0x05AC
|
|
#define REG_DTIM_COUNTER_VAP5_8197F 0x05AD
|
|
#define REG_DTIM_COUNTER_VAP6_8197F 0x05AE
|
|
#define REG_DTIM_COUNTER_VAP7_8197F 0x05AF
|
|
#define REG_DIS_ATIM_8197F 0x05B0
|
|
#define REG_EARLY_128US_8197F 0x05B1
|
|
#define REG_P2PPS1_CTRL_8197F 0x05B2
|
|
#define REG_P2PPS2_CTRL_8197F 0x05B3
|
|
#define REG_TIMER0_SRC_SEL_8197F 0x05B4
|
|
#define REG_NOA_UNIT_SEL_8197F 0x05B5
|
|
#define REG_P2POFF_DIS_TXTIME_8197F 0x05B7
|
|
#define REG_MBSSID_BCN_SPACE2_8197F 0x05B8
|
|
#define REG_MBSSID_BCN_SPACE3_8197F 0x05BC
|
|
#define REG_ACMHWCTRL_8197F 0x05C0
|
|
#define REG_ACMRSTCTRL_8197F 0x05C1
|
|
#define REG_ACMAVG_8197F 0x05C2
|
|
#define REG_VO_ADMTIME_8197F 0x05C4
|
|
#define REG_VI_ADMTIME_8197F 0x05C6
|
|
#define REG_BE_ADMTIME_8197F 0x05C8
|
|
#define REG_EDCA_RANDOM_GEN_8197F 0x05CC
|
|
#define REG_TXCMD_NOA_SEL_8197F 0x05CF
|
|
#define REG_NOA_PARAM_8197F 0x05E0
|
|
#define REG_P2P_RST_8197F 0x05F0
|
|
#define REG_SCHEDULER_RST_8197F 0x05F1
|
|
#define REG_SCH_TXCMD_8197F 0x05F8
|
|
#define REG_PAGE5_DUMMY_8197F 0x05FC
|
|
#define REG_CPUMGQ_TX_TIMER_8197F 0x1500
|
|
#define REG_PS_TIMER_A_8197F 0x1504
|
|
#define REG_PS_TIMER_B_8197F 0x1508
|
|
#define REG_PS_TIMER_C_8197F 0x150C
|
|
#define REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8197F 0x1510
|
|
#define REG_CPUMGQ_TX_TIMER_EARLY_8197F 0x1514
|
|
#define REG_PS_TIMER_A_EARLY_8197F 0x1515
|
|
#define REG_PS_TIMER_B_EARLY_8197F 0x1516
|
|
#define REG_PS_TIMER_C_EARLY_8197F 0x1517
|
|
#define REG_WMAC_CR_8197F 0x0600
|
|
#define REG_WMAC_FWPKT_CR_8197F 0x0601
|
|
#define REG_BWOPMODE_8197F 0x0603
|
|
#define REG_TCR_8197F 0x0604
|
|
#define REG_RCR_8197F 0x0608
|
|
#define REG_RX_PKT_LIMIT_8197F 0x060C
|
|
#define REG_RX_DLK_TIME_8197F 0x060D
|
|
#define REG_RX_DRVINFO_SZ_8197F 0x060F
|
|
#define REG_MACID_8197F 0x0610
|
|
#define REG_BSSID_8197F 0x0618
|
|
#define REG_MAR_8197F 0x0620
|
|
#define REG_MBIDCAMCFG_1_8197F 0x0628
|
|
#define REG_MBIDCAMCFG_2_8197F 0x062C
|
|
#define REG_WMAC_TCR_TSFT_OFS_8197F 0x0630
|
|
#define REG_UDF_THSD_8197F 0x0632
|
|
#define REG_ZLD_NUM_8197F 0x0633
|
|
#define REG_STMP_THSD_8197F 0x0634
|
|
#define REG_WMAC_TXTIMEOUT_8197F 0x0635
|
|
#define REG_MCU_TEST_2_V1_8197F 0x0636
|
|
#define REG_USTIME_EDCA_8197F 0x0638
|
|
#define REG_MAC_SPEC_SIFS_8197F 0x063A
|
|
#define REG_RESP_SIFS_CCK_8197F 0x063C
|
|
#define REG_RESP_SIFS_OFDM_8197F 0x063E
|
|
#define REG_ACKTO_8197F 0x0640
|
|
#define REG_CTS2TO_8197F 0x0641
|
|
#define REG_EIFS_8197F 0x0642
|
|
#define REG_NAV_CTRL_8197F 0x0650
|
|
#define REG_BACAMCMD_8197F 0x0654
|
|
#define REG_BACAMCONTENT_8197F 0x0658
|
|
#define REG_LBDLY_8197F 0x0660
|
|
#define REG_WMAC_BACAM_RPMEN_8197F 0x0661
|
|
#define REG_WMAC_BITMAP_CTL_8197F 0x0663
|
|
#define REG_RXERR_RPT_8197F 0x0664
|
|
#define REG_WMAC_TRXPTCL_CTL_8197F 0x0668
|
|
#define REG_CAMCMD_8197F 0x0670
|
|
#define REG_CAMWRITE_8197F 0x0674
|
|
#define REG_CAMREAD_8197F 0x0678
|
|
#define REG_CAMDBG_8197F 0x067C
|
|
#define REG_SECCFG_8197F 0x0680
|
|
#define REG_RXFILTER_CATEGORY_1_8197F 0x0682
|
|
#define REG_RXFILTER_ACTION_1_8197F 0x0683
|
|
#define REG_RXFILTER_CATEGORY_2_8197F 0x0684
|
|
#define REG_RXFILTER_ACTION_2_8197F 0x0685
|
|
#define REG_RXFILTER_CATEGORY_3_8197F 0x0686
|
|
#define REG_RXFILTER_ACTION_3_8197F 0x0687
|
|
#define REG_RXFLTMAP3_8197F 0x0688
|
|
#define REG_RXFLTMAP4_8197F 0x068A
|
|
#define REG_RXFLTMAP5_8197F 0x068C
|
|
#define REG_RXFLTMAP6_8197F 0x068E
|
|
#define REG_WOW_CTRL_8197F 0x0690
|
|
#define REG_PS_RX_INFO_8197F 0x0692
|
|
#define REG_WMMPS_UAPSD_TID_8197F 0x0693
|
|
#define REG_LPNAV_CTRL_8197F 0x0694
|
|
#define REG_WKFMCAM_CMD_8197F 0x0698
|
|
#define REG_WKFMCAM_RWD_8197F 0x069C
|
|
#define REG_RXFLTMAP0_8197F 0x06A0
|
|
#define REG_RXFLTMAP1_8197F 0x06A2
|
|
#define REG_RXFLTMAP_8197F 0x06A4
|
|
#define REG_BCN_PSR_RPT_8197F 0x06A8
|
|
#define REG_RXPKTMON_CTRL_8197F 0x06B0
|
|
#define REG_STATE_MON_8197F 0x06B4
|
|
#define REG_ERROR_MON_8197F 0x06B8
|
|
#define REG_SEARCH_MACID_8197F 0x06BC
|
|
#define REG_BT_COEX_TABLE_8197F 0x06C0
|
|
#define REG_RXCMD_0_8197F 0x06D0
|
|
#define REG_RXCMD_1_8197F 0x06D4
|
|
#define REG_WMAC_RESP_TXINFO_8197F 0x06D8
|
|
#define REG_BBPSF_CTRL_8197F 0x06DC
|
|
#define REG_P2P_RX_BCN_NOA_8197F 0x06E0
|
|
#define REG_ASSOCIATED_BFMER0_INFO_8197F 0x06E4
|
|
#define REG_ASSOCIATED_BFMER1_INFO_8197F 0x06EC
|
|
#define REG_TX_CSI_RPT_PARAM_BW20_8197F 0x06F4
|
|
#define REG_TX_CSI_RPT_PARAM_BW40_8197F 0x06F8
|
|
#define REG_TX_CSI_RPT_PARAM_BW80_8197F 0x06FC
|
|
#define REG_BCN_PSR_RPT2_8197F 0x1600
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#define REG_BCN_PSR_RPT3_8197F 0x1604
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#define REG_BCN_PSR_RPT4_8197F 0x1608
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#define REG_A1_ADDR_MASK_8197F 0x160C
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#define REG_MACID2_8197F 0x1620
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#define REG_BSSID2_8197F 0x1628
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#define REG_MACID3_8197F 0x1630
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#define REG_BSSID3_8197F 0x1638
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#define REG_MACID4_8197F 0x1640
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#define REG_BSSID4_8197F 0x1648
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#define REG_NOA_REPORT_8197F 0x1650
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#define REG_PWRBIT_SETTING_8197F 0x1660
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#define REG_WMAC_MU_BF_OPTION_8197F 0x167C
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#define REG_WMAC_PAUSE_BB_CLR_TH_8197F 0x167D
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#define REG_WMAC_MU_ARB_8197F 0x167E
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#define REG_WMAC_MU_OPTION_8197F 0x167F
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#define REG_WMAC_MU_BF_CTL_8197F 0x1680
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#define REG_WMAC_MU_BFRPT_PARA_8197F 0x1682
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#define REG_WMAC_ASSOCIATED_MU_BFMEE2_8197F 0x1684
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#define REG_WMAC_ASSOCIATED_MU_BFMEE3_8197F 0x1686
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#define REG_WMAC_ASSOCIATED_MU_BFMEE4_8197F 0x1688
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#define REG_WMAC_ASSOCIATED_MU_BFMEE5_8197F 0x168A
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#define REG_WMAC_ASSOCIATED_MU_BFMEE6_8197F 0x168C
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#define REG_WMAC_ASSOCIATED_MU_BFMEE7_8197F 0x168E
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#define REG_TRANSMIT_ADDRSS_0_8197F 0x16A0
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#define REG_TRANSMIT_ADDRSS_1_8197F 0x16A8
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#define REG_TRANSMIT_ADDRSS_2_8197F 0x16B0
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#define REG_TRANSMIT_ADDRSS_3_8197F 0x16B8
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#define REG_TRANSMIT_ADDRSS_4_8197F 0x16C0
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#define REG_MACID1_8197F 0x0700
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#define REG_BSSID1_8197F 0x0708
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#define REG_BCN_PSR_RPT1_8197F 0x0710
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#define REG_ASSOCIATED_BFMEE_SEL_8197F 0x0714
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#define REG_SND_PTCL_CTRL_8197F 0x0718
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#define REG_RX_CSI_RPT_INFO_8197F 0x071C
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#define REG_NS_ARP_CTRL_8197F 0x0720
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#define REG_NS_ARP_INFO_8197F 0x0724
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#define REG_BEAMFORMING_INFO_NSARP_V1_8197F 0x0728
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#define REG_BEAMFORMING_INFO_NSARP_8197F 0x072C
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#define REG_WMAC_RTX_CTX_SUBTYPE_CFG_8197F 0x0750
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#define REG_WMAC_SWAES_CFG_8197F 0x0760
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#define REG_BT_COEX_V2_8197F 0x0762
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#define REG_BT_COEX_8197F 0x0764
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#define REG_WLAN_ACT_MASK_CTRL_8197F 0x0768
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#define REG_BT_COEX_ENHANCED_INTR_CTRL_8197F 0x076E
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#define REG_BT_ACT_STATISTICS_8197F 0x0770
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#define REG_BT_STATISTICS_CONTROL_REGISTER_8197F 0x0778
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#define REG_BT_STATUS_REPORT_REGISTER_8197F 0x077C
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#define REG_BT_INTERRUPT_CONTROL_REGISTER_8197F 0x0780
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#define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8197F 0x0784
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#define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8197F 0x0785
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#define REG_BT_INTERRUPT_STATUS_REGISTER_8197F 0x078F
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#define REG_BT_TDMA_TIME_REGISTER_8197F 0x0790
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#define REG_BT_ACT_REGISTER_8197F 0x0794
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#define REG_OBFF_CTRL_BASIC_8197F 0x0798
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#define REG_OBFF_CTRL2_TIMER_8197F 0x079C
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#define REG_LTR_CTRL_BASIC_8197F 0x07A0
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#define REG_LTR_CTRL2_TIMER_THRESHOLD_8197F 0x07A4
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#define REG_LTR_IDLE_LATENCY_V1_8197F 0x07A8
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#define REG_LTR_ACTIVE_LATENCY_V1_8197F 0x07AC
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#define REG_ANTENNA_TRAINING_CONTROL_REGISTER_8197F 0x07B0
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#define REG_WMAC_PKTCNT_RWD_8197F 0x07B8
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#define REG_WMAC_PKTCNT_CTRL_8197F 0x07BC
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#define REG_IQ_DUMP_8197F 0x07C0
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#define REG_WMAC_FTM_CTL_8197F 0x07CC
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#define REG_IQ_DUMP_EXT_8197F 0x07CF
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#define REG_OFDM_CCK_LEN_MASK_8197F 0x07D0
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#define REG_RX_FILTER_FUNCTION_8197F 0x07DA
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#define REG_NDP_SIG_8197F 0x07E0
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#define REG_TXCMD_INFO_FOR_RSP_PKT_8197F 0x07E4
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#define REG_SEC_OPT_V2_8197F 0x07EC
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#define REG_RTS_ADDRESS_0_8197F 0x07F0
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#define REG_RTS_ADDRESS_1_8197F 0x07F8
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#define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8197F 0x1700
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#define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8197F 0x1704
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#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8197F 0x1708
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#endif
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